a FEATURES 4 or 8 Analog Input Channels Built-In Track-and-Hold Function 10 kHz Signal Handling on Each Channel Fast Microprocessor Interface Single 5 V Supply Low Power: 50 mW Fast Conversion Rate: 2.5 s/Channel Tight Error Specification: 1/2 LSB LC2MOS High Speed 4- and 8-Channel 8-Bit ADCs AD7824/AD7828 FUNCTIONAL BLOCK DIAGRAM VREF (+) AIN1 AIN4 DB7 DB6 DB5 DB4 4-BIT FLASH ADC (4MSB) VREF (-) VREF (+) 16 AIN8 THREESTATE DRIVERS 4-BIT DAC MUX* DB3 DB2 DB1 DB0 4-BIT FLASH ADC (4LSB) ADDRESS LATCH DECODE TIMING AND CONTROL CIRCUITRY A0 A1 A2** RDY CS INT RD *AD7824 - 4-CHANNEL MUX **AD7828 - 8-CHANNEL MUX A2 - AD7828 ONLY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7824 and AD7828 are high speed, multichannel, 8-bit ADCs with a choice of four (AD7824) or eight (AD7828) multiplexed analog inputs. A half-flash conversion technique gives a fast conversion rate of 2.5 s per channel, and the parts have a built-in track-and-hold function capable of digitizing full-scale signals of 10 kHz (157 mV/s slew rate) on all channels. The AD7824 and AD7828 operate from a single 5 V supply and have an analog input range of 0 V to 5 V, using an external 5 V reference. 1. 4- or 8-channel input multiplexer gives cost effective, space-saving multichannel ADC system. Microprocessor interfacing of the parts is simple, using standard Chip Select (CS) and Read (RD) signals to initiate the conversion and read the data from the three-state data outputs. The half-flash conversion technique means that there is no need to generate a clock signal for the ADC. The AD7824 and AD7828 can be interfaced easily to most popular microprocessors. 2. Fast conversion rate of 2.5 s/channel features a per-channel sampling frequency of 100 kHz for the AD7824 or 50 kHz for the AD7828. 3. Built-in track-and-hold function allows handling of four or eight channels up to 10 kHz bandwidth (157 mV/s slew rate). 4. Tight total unadjusted error spec and channel-to-channel matching eliminate the need for user trims. 5. Single 5 V supply simplifies system power requirements. 6. Fast, easy-to-use digital interface allows connection to most popular microprocessors with minimal external components. No clock signal is required for the ADC. The AD7824 and AD7828 are fabricated in an advanced, all ion-implanted, linear compatible CMOS process (LC2MOS) and have low power dissipation of 40 mW (typ). The AD7824 is available in a 0.3" wide, 24-lead "skinny" DIP, while the AD7828 is available in a 0.6" wide, 28-lead DIP and in 28-terminal surfacemount packages. REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. (V = 5 V, V (+) = 5 V, V AD7824/AD7828-SPECIFICATIONS noted. All specifications T to T , unless otherwise noted. Specifications apply to Mode 0.) DD MIN ACCURACY Resolution Total Unadjusted Error2 Minimum Resolution for which No Missing Codes Are Guaranteed Channel-to-Channel Mismatch VREF (-) Input Voltage Range ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance3 LOGIC INPUTS RD, CS, A0, A1, and A2 VINH VINL IINH IINL Input Capacitance3 LOGIC OUTPUTS DB0-DB7 and INT VOH VOL IOUT (DB0-DB7) Output Capacitance3 RDY VOL4 IOUT Output Capacitance SLEW RATE, TRACKING3 POWER SUPPLY VDD IDD5 Power Dissipation Power Supply Sensitivity REF (-) = GND = O V, unless otherwise MAX Parameter REFERENCE INPUT Input Resistance VREF (+) Input Voltage Range REF K Version1 L Version B, T Versions C, U Versions Unit 8 1 8 1/2 8 1 8 1/2 Bits LSB max 8 1/4 8 1/4 8 1/4 8 1/4 Bits LSB max 1.0/4.0 VREF (-)/ VDD GND/ VREF (+) 1.0/4.0 VREF (-)/ VDD GND/ VREF (+) 1.0/4.0 VREF (-)/ VDD GND/ VREF (+) 1.0/4.0 VREF (-)/ VDD GND/ VREF (+) k min/k max V min/V max VREF (-)/ VREF (+) 3 45 VREF (-)/ VREF (+) 3 45 VREF (-)/ VREF (+) 3 45 VREF (-)/ VREF (+) 3 45 A max pF typ Analog Input Any Channel 0 V to 5 V 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 V min V max A max A max pF max Typically 5 pF 4.0 0.4 3 8 4.0 0.4 3 8 4.0 0.4 3 8 4.0 0.4 3 8 V min V max A max pF max ISOURCE = 360 A ISINK = 1.6 mA Floating State Leakage Typically 5 pF 0.4 3 8 0.4 3 8 0.4 3 8 0.4 3 8 V max A max pF max ISINK = 2.6 mA Floating State Leakage Typically 5 pF 0.7 0.157 0.7 0.157 0.7 0.157 0.7 0.157 V/s typ V/s max 5 5 5 5 V 16 50 80 1/4 16 50 80 1/4 20 50 100 1/4 20 50 100 1/4 mA max mW typ mW max LSB max Conditions/Comments V min/V max V min/V max 5% for Specified Performance CS = RD = 2.4 V 1/16 LSB typ VDD = 5 V 5% NOTES 1 Temperature ranges are as follows: K, L Versions: 0C to 70C B, C Versions: -40C to +85C T, U Versions: -55C to +125C 2 Total Unadjusted Error includes offset, full-scale and linearity errors. 3 Sample tested at 25C by Product Assurance to ensure compliance. 4 RDY is an open-drain output. 5 See Typical Performance Characteristics. Specifications subject to change without notice. -2- REV. F AD7824/AD7828 TIMING CHARACTERISTICS1 (V DD = 5 V; VREF(+) = 5 V; VREF(-) = GND = 0 V, unless otherwise noted.) Parameter Limit at 25C (All Grades) Limit at TMIN, TMAX (K, L, B, C Grades) Limit at TMIN, TMAX (T, U Grades) Unit Conditions/Comments tCSS tCSH tAS tAH tRDY2 0 0 0 30 40 0 0 0 35 60 0 0 0 40 60 ns min ns min ns min ns min ns max tCRD tACC13 tACC23 tlNTH2 2.0 85 50 40 75 60 500 60 600 2.4 110 60 65 100 70 500 80 500 2.8 120 70 70 100 70 600 80 400 s max ns max ns max ns typ ns max ns max ns min ns min ns max CS to RD Setup Time CS to RD Hold Time Multiplexer Address Setup Time Multiplexer Address Hold Time CS to RDY Delay. Pull-Up Resistor 5 k. Conversion Time, Mode 0 Data Access Time after RD Data Access Time after INT, Mode 0 RD to INT Delay tDH4 tP tRD Data Hold Time Delay Time between Conversions Read Pulsewidth, Mode 1 NOTES 1 Sample tested at 25C to ensure compliance. All input control signals are specified with t RISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 CL = 50 pF. 3 Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice. Test Circuits DBN DBN 3k 3k 100pF 10pF DGND DGND a. VOH to High-Z a. High-Z to VOH 5V 5V 3k 3k DBN DBN 100pF 10pF DGND DGND b. High-Z to VOL b. VOL to High-Z Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test REV. F -3- AD7824/AD7828 Operating Temperature Range Commercial (K, L Versions) . . . . . . . . . . . . . . 0C to 70C Industrial (B, C Versions) . . . . . . . . . . . . . -40C to +85C Extended (T, U Versions) . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300C Power Dissipation (Any Package) to 75C . . . . . . . . . 450 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/C ABSOLUTE MAXIMUM RATINGS* (TA = 25C, unless otherwise noted.) VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V Digital Input Voltage to GND (RD, CS, A0, A1, and A2) . . . . . . . . . -0.3 V, VDD + 0.3 V Digital Output Voltage to GND (DB0, DB7, RDY, and INT) . . . . . . . -0.3 V, VDD + 0.3 V VREF (+) to GND . . . . . . . . . . . . . . . . . VREF (-), VDD + 0.3 V VREF (-) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VREF (+) Analog Input (Any Channel) . . . . . . . . . . -0.3 V, VDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although AD7824/AD7828 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS 1 24 VDD AIN6 1 28 AIN7 2 AIN3 2 23 NC AIN5 27 AIN8 AIN2 3 22 A0 AIN4 3 26 VDD AIN1 4 21 A1 AIN3 4 25 A0 NC 5 20 DB7 AIN2 5 24 A1 DB0 6 AIN1 6 23 A2 DB1 TOP VIEW 19 DB6 (Not to Scale) 18 DB5 7 DB2 8 17 DB4 TOP VIEW 22 DB7 DB0 8 (Not to Scale) 21 DB6 DB3 9 16 CS DB1 9 20 DB5 RD 10 15 RDY DB2 10 19 DB4 INT 11 14 VREF (+) DB3 11 18 CS GND 12 13 VREF (-) RDY AD7824 AD7828 NC 7 NC = NO CONNECT RD 12 17 INT 13 16 VREF (+) GND 14 15 VREF (-) NC = NO CONNECT AIN5 AIN6 AIN7 3 2 1 28 27 26 VDD AIN4 AIN8 AIN3 PLCC 4 PIN 1 IDENTIFIER AIN2 5 AIN1 6 ESD SENSITIVE DEVICE ORDERING GUIDE DIP/SOIC/SSOP AIN4 WARNING! 25 A0 Model Temperature Range Total Unadjusted Package Error (LSBs) Option AD7824KN AD7824LN AD7824KR AD7824BQ AD7824CQ AD7824TQ* AD7824UQ* 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 1 1/2 1 1 1/2 1 1/2 N-24 N-24 R-24 Q-24 Q-24 Q-24 Q-24 AD7828KN AD7828LN AD7828KP AD7828LP AD7828BQ AD7828CQ AD7828BR AD7828LRS AD7828TQ* AD7828UQ* AD7828TE* AD7828UE* 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C 0C to 70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C 1 1/2 1 1/2 1 1/2 +1 1/2 1 1/2 1 1/2 N-28 N-28 P-28A P-28A Q-28 Q-28 R-28 RS-28 Q-28 Q-28 E-28A E-28A 24 A1 2 1 28 27 26 VDD AIN8 AIN7 3 AIN2 5 25 A0 AIN1 6 24 A1 NC 7 AD7828 23 A2 DB0 8 TOP VIEW (Not to Scale) 22 DB7 21 DB6 DB2 10 20 DB5 DB3 11 19 DB4 DB1 9 CS RDY VREF (+) 12 13 14 15 16 17 18 VREF (-) NC = NO CONNECT 4 GND 18 LCCC RD 17 CS VREF (-) GND RD INT 16 RDY 19 DB4 VREF (+) 20 DB5 DB3 11 AIN6 21 DB6 DB2 10 AIN5 22 DB7 (Not to Scale) AIN4 TOP VIEW DB1 9 AIN3 DB0 8 12 13 14 15 *Available to /883B processing only. Contact our local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing #5692-88764. 23 A2 AD7828 INT NC 7 NC = NO CONNECT -4- REV. F Typical Performance Characteristics-AD7824/AD7828 14 13 IDD - SUPPLY CURRENT - mA tCRD - CONVERSION TIME - s 3 2 VDD = 5V 12 VDD = 5V VDD = 5.25V 11 10 9 VDD = 4.75V 1 -100 -50 0 50 100 TA - AMBIENT TEMPERATURE - C 8 -100 150 TPC 1. Conversion Time vs. Temperature -50 0 50 100 TA - AMBIENT TEMPERATURE - C TPC 4. Power Supply Current vs. Temperature (Not Including Reference Ladder) 2.0 2.0 VDD = 5V VREF = 5V TA = 25C 1.5 LINEARITY ERROR - LSB LINEARITY ERROR - LSB* VDD = 5V TA = 25C 1.0 0.5 0 150 0 *1LSB = 1 2 3 4 1.5 1.0 0.5 0 300 5 VREF - V VREF 400 500 600 700 800 900 tP - ns 256 TPC 2. Accuracy vs. VREF [VREF = VREF (+) - VREF (-)] TPC 5. Accuracy vs. tP -36 10 ENCODE RATE = 400kHz INPUT SIGNAL = 5V p-p MEASUREMENT BANDWIDTH = 80kHz -38 VDD = 5V 8 OUTPUT CURRENT - mA -40 SNR - dB -42 -44 -46 -48 ISOURCE, V OUT = 2.4V 6 4 ISINK, V OUT = 0.4V 2 -50 -52 1 2 3 4 5 7 10 20 30 40 50 70 INPUT FREQUENCY - kHz 0 -100 100 TPC 3. Signal Noise Ratio vs. Input Frequency REV. F -50 0 50 100 TA - AMBIENT TEMPERATURE - C TPC 6. Output Current vs. Temperature -5- 150 AD7824/AD7828 OPERATIONAL DIAGRAM APPLYING THE AD7824/AD7828 REFERENCE AND INPUT The AD7824 is a 4-channel 8-bit ADC and the AD7828 is an 8-channel 8-bit ADC. Operational diagrams for both of these devices are shown in Figures 3 and 4. The addition of just a 5 V reference allows the devices to perform the analog-to-digital function. ANALOG INPUTS 0V TO 5V 1 AIN4 VDD 24 2 AIN3 NC 23 3 AIN2 A0 22 4 AIN1 A1 21 5 NC P 4LSB DATA BUS AD7824 P CONTROL INPUT STATUS OUTPUT 5V P ADDRESS BUS This reference flexibility also allows the input channel voltage span to be offset from zero. The voltage at VREF (-) sets the input level for all channels, which produces a digital output of all zeroes. Therefore, although the analog inputs are not themselves differential, they have nearly differential input capability in most measurement applications because of the reference design. Figures 5 to 7 show some of the configurations that are possible. DB7 20 6 DB0 DB6 19 7 DB1 DB5 18 8 DB2 DB4 17 9 DB3 The two reference inputs on the AD7824/AD7828 are fully differential and define the zero to full-scale input range of the ADC. As a result, the span of the analog input voltage for all channels can easily be varied. By reducing the reference span, VREF (+) to VREF (-), to less than 5 V, the sensitivity of the converter can be increased (e.g., if VREF = 2 V then 1 LSB = 7.8 mV). The input/ reference arrangement also facilitates ratiometric operation. CS 16 10 RD RDY 15 11 INT VREF (+) 14 12 GND VREF (-) 13 P 4MSB DATA BUS P CONTROL INPUT STATUS OUTPUT 5V NC = NO CONNECT VIN (+) AIN1 VIN (-) GND AD7824* Figure 3. AD7824 Operational Diagram AD7828* 5V VDD 0.1F ANALOG INPUTS 0V TO 5V P 4LSB DATA BUS 1 AIN6 AIN7 28 2 AIN5 AIN8 27 3 AIN4 VDD 26 4 AIN3 A0 25 5 AIN2 A1 24 AIN1 7 NC 8 DB0 DB6 21 9 DB1 DB5 20 10 DB2 DB4 19 11 DB3 CS 18 AD7828 VREF (+) VREF (-) 5V *ADDITIONAL PINS OMITTED FOR CLARITY. ONLY CHANNEL 1 SHOWN. P ADDRESS BUS A2 23 6 47F ANALOG INPUTS 0V TO 5V Figure 5. Power Supply as Reference DB7 22 P CONTROL INPUT 12 RD RDY 17 STATUS OUTPUT 13 INT VREF (+) 16 14 GND VREF (-) 15 P 4MSB DATA BUS P CONTROL INPUT VIN (+) AIN1 VIN (-) GND AD7824* AD7828* 5V VDD STATUS OUTPUT 0.1F 47F 5V AD580 VREF (+) 0.1F 10F VREF (-) NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY. ONLY CHANNEL 1 SHOWN. Figure 4. AD7828 Operational Diagram Figure 6. External Reference Using the AD580, Full-Scale Input is 2.5 V CIRCUIT INFORMATION BASIC DESCRIPTION The AD7824/AD7828 uses a half-flash conversion technique whereby two 4-bit flash ADCs are used to achieve an 8-bit result. Each 4-bit flash ADC contains 15 comparators that compare the unknown input to a reference ladder to get a 4-bit result. For a full 8-bit reading to be realized, the upper 4-bit flash, the most significant (MS) flash, performs a conversion to provide the four most significant data bits. An internal DAC, driven by the four MSBs, then recreates an analog approximation of the input voltage. This analog result is subtracted from the input, and the difference is converted by the lower flash ADC, the least significant (LS) flash, to provide the four least significant bits of the output data. The most significant flash ADC also has one additional comparator to detect overrange on the analog input. VIN (+) AIN1 GND AD7824* AD7828* 5V VDD 0.1F 47F DB7 V1 VREF (+) V2 VREF (-) DATA DB0 *ADDITIONAL PINS OMITTED FOR CLARITY. ONLY CHANNEL 1 SHOWN. DATA = VIN (+) 256 (FOR ALL CHANNELS) V1 - V2 Figure 7. Input Not Referenced to GND -6- REV. F AD7824/AD7828 INPUT CURRENT Due to the novel conversion techniques employed by the AD7824/ AD7828, the analog input behaves somewhat differently than in conventional devices. The ADC's sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. The equivalent input circuit of the AD7824/AD7828 is shown in Figure 8. When a conversion starts (CS and RD going low), all input switches close, and the selected input channel is connected to the most significant and least significant comparators. Therefore, the analog input is simultaneously connected to 31 input capacitors of 1 pF each. CS 2pF RS R MUX AIN1 VIN CS 12pF 1pF RON TO LS LADDER * * * 1pF 15LSB COMPARATORS 1pF RON AD7824/ AD7828 TO MS LADDER * * * 1pF 16MSB COMPARATORS Figure 8. AD7824/AD7828 Equivalent Input Circuit The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 3 k to 6 k). In addition, about 14 pF of input stray capacitance must be charged. The analog input for any channel can be modelled as an RC network, as shown in Figure 9. As RS increases, it takes longer for the input capacitance to charge. RS VIN AIN1 R MUX 800 CS1 12pF Suitable op amps for driving the AD7824/AD7828 are the AD544 or AD644. INHERENT SAMPLE-HOLD A major benefit of the AD7824's and AD7828's analog input structure is its ability to measure a variety of high speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain stable to at least 1/2 LSB throughout the conversion process if rated accuracy is to be maintained. Consequently, for many high speed signals, this signal must be externally sampled and held stationary during the conversion. The AD7824/AD7828 input comparators, by nature of their input switching, inherently accomplish this sample-and-hold function. Although the conversion time for AD7824/AD7828 is 2 s, the time for which any selected analog input must be 1/2 LSB stable is much smaller. The AD7824/AD7828 tracks the selected input channel for approximately 1 s after conversion start. The value of the analog input at that instant (1 s from conversion start) is the measured value. This value is then used in the least significant flash to generate the lower four bits of data. SINUSOIDAL INPUTS The AD7824/AD7828 can measure input signals with slew rates as high as 157 mV/s to the rated specifications. This means that the analog input frequency can be up to 10 kHz without the aid of an external sample-and-hold. Furthermore, the AD7828 can measure eight 10 kHz signals without a sample-and-hold. The Nyquist criterion requires that the sampling rate be twice the input frequency (i.e., 2 x 10 kHz). This requires an ideal antialiasing filter with an infinite roll-off. To ease the problem of antialiasing filter design, the sampling rate is usually much greater than the Nyquist criterion. The maximum sampling rate (FMAX) for the AD7824/AD7828 can be calculated as follows: RON 350 CS2 2pF 31pF Figure 9. RC Network Model The time for which the input comparators track the analog input is approximately 1 s at the start of conversion. Because of input transients on the analog inputs, it is recommended that a source impedance no greater than 100 be connected to the analog inputs. The output impedance of an op amp is equal to the open loop output impedance divided by the loop gain at the frequency of REV. F interest. It is important that the amplifier driving the AD7824/ AD7828 analog inputs have sufficient loop gain at the input signal frequency as to make the output impedance low. FMAX = 1 tCRD + t P FMAX = 1 = 400 kHz 2E - 6 + 0.5E - 6 tCRD = AD7824/AD7828 Conversion Time tP = Minimum Delay Between Conversion This permits a maximum sampling rate of 50 kHz for each of the eight channels when using the AD7828 and 100 kHz for each of the four channels when using the AD7824. -7- AD7824/AD7828 UNIPOLAR OPERATION 25k The analog input range for any channel of the AD7824/AD7828 is 0 V to 5 V as shown in the unipolar operational diagram of Figure 10. Figure 11 shows the designed code transitions that occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV. VIN 5V 40k 27k AD544 12k AIN1 VREF (+) 5V 5V VDD 0.1F 47F VREF (-) 0.1F 47F V REF 5V VIN 0V TO 5V VREF (+) *ADDITIONAL PINS OMITTED FOR CLARITY. ONLY CHANNEL 1 SHOWN. AD7824* AD7828* AIN1 Figure 12. AD7824/AD7828 Bipolar 4 V Operation DB7 VREF (-) DB7 DB0 GND VDD 5V AD7824* AD7828* DB0 GND 11111111 *ADDITIONAL PINS OMITTED FOR CLARITY. ONLY CHANNEL 1 SHOWN. FS = 8V 1LSB = FS/256 11111110 11111101 OUTPUT CODE Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation FULL-SCALE TRANSITION 11111111 10000010 10000001 10000000 01111111 01111110 11111101 00000010 OUTPUT CODE 11111110 +FS 2 -FS + 1LSB 2 00000001 00000000 1LSB = FS 256 0V AIN, INPUT VOLTAGE - LSB 00000011 Figure 13. Ideal Input/Output Transfer Characteristic for 4 V Operation 00000010 00000001 00000000 0 1LSB 2LSB 3LSB TIMING AND CONTROL FS The AD7824/AD7828 has two digital inputs for timing and control. These are Chip Select (CS) and Read (RD). A READ operation brings CS and RD low, which starts a conversion on the channel selected by the multiplexer address inputs (see Table I). There are two modes of operation as outlined by the timing diagrams of Figures 14 and 15. Mode 0 is designed for microprocessors that can be driven into a WAIT state. A READ operation (i.e., CS and RD are taken low) starts a conversion and data is read when conversion is complete. Mode l does not require microprocessor WAIT states. A READ operation initiates a conversion and reads the previous conversion results. FS - 1LSB AIN, INPUT VOLTAGE - LSB Figure 11. Ideal Input/Output Transfer Characteristic for Unipolar 0 V to 5 V Operation BIPOLAR OPERATION The circuit of Figure 12 is designed for bipolar operation. An AD544 op amp conditions the signal input (VIN) so that only positive voltages appear at AIN1. The closed loop transfer function of the op amp for the resistor values shown is given below: AIN 1 = (2.5 - 0.625VIN ) Volts Table I. Truth Table for Input Channel Selection The analog input range is 4 V and the LSB size is 31.25 mV. The output code is complementary offset binary. The ideal input/output characteristic is shown in Figure 13. AD7824 A1 A0 0 0 1 1 -8- 0 1 0 1 A2 0 0 0 0 1 1 1 1 AD7828 A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Channel AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 REV. F AD7824/AD7828 MODE 0 MODE 1 Figure 14 shows the timing diagram for Mode 0 operation. This mode can only be used for microprocessors that have a WAIT state facility, whereby a READ instruction cycle can be extended to accommodate slow memory devices. A READ operation brings CS and RD low, which starts a conversion. The analog multiplexer address inputs must remain valid while CS and RD are low. The data bus (DB7-DB0) remains in the three-state condition until conversion is complete. There are two converter status outputs on the AD7824/AD7828, interrupt (INT) and ready (RDY), which can be used to drive the microprocessor READY/WAIT input. The RDY is an open-drain output (no internal pull-up device) that goes low on the falling edge of CS and goes high impedance at the end of conversion when the 8-bit conversion result appears on the data outputs. If the RDY status is not required, the external pull-up resistor can be omitted and the RDY output tied to GND. The INT goes low when conversion is complete and returns high on the rising edge of CS or RD. Mode 1 operation is designed for applications where the microprocessor is not forced into a WAIT state. A READ operation takes CS and RD low, which triggers a conversion (see Figure 15). The multiplexer address inputs are latched on the rising edge of RD. Data from the previous conversion is read from the three-state data outputs (DB7-DB0). This data may be disregarded if not required. Note that the RDY output (open drain output) does not provide any status information in this mode and must be connected to GND. At the end of conversion, INT goes low. A second READ operation is required to access the new conversion result. This READ operation latches a new address into the multiplexer inputs and starts another conversion. INT returns high at the end of the second READ operation, when CS or RD returns high. A delay of 2.5 s must be allowed between READ operations. CS tCSH tCSS tCSS RD tP tAS ANALOG CHANNEL ADDRESS ADDRESS VALID tAS ADDRESS VALID tAH RDY tRDY tINTH INT tCRD tACC2 HIGH IMPEDANCE DATA tDH DATA VALID Figure 14. Mode 0 Timing Diagram CS tCSS tCSH tRD tCSS tRD tCSH RD tP tAS ANALOG CHANNEL ADDRESS tAS ADDRESS VALID ADDRESS VALID tAH tAH tCRD tINTH tINTH INT tACC1 DATA tDH tACC1 OLD VALID Figure 15. Mode 1 Timing Diagram REV. F tDH NEW VALID -9- AD7824/AD7828 MICROPROCESSOR INTERFACING The AD7824/AD7828 is designed to interface to microprocessors as Read Only Memory (ROM). Analog channel selection, conversion start, and data read operations are controlled by CS, RD, and the channel address inputs. These signals are common to all memory peripheral devices. Z80 MICROPROCESSOR to any of the addresses in Table II starts a conversion and reads the conversion result. MOVE x B $C000, D0 Once conversion has begun, the MC68000 inserts WAIT states until INT goes low, asserting DTACK at the end of conversion. The microprocessor then places the conversion results into the D0 register. Figure 16 shows a typical AD7824/AD7828-Z80 interface. The AD7824/AD7828 is operating in Mode 0. Assume the ADC is assigned a memory block starting at address C000. The following LOAD instruction to any of the addresses listed in Table II will start a conversion of the selected channel and read the conversion result. A23 A1 ADDRESS BUS A1 A0 EN ADDRESS DECODE AS LD B, (C000) ADDRESS BUS A1 A2** RD CLR MC68000 7474 AD7824* AD7828* 5V D 5k DTACK Q CK RDY D7 A15 A1 CS R/W At the beginning of the instruction cycle when the ADC address is selected, RDY asserts the WAIT input so that the Z80 is forced into a WAIT state. At the end of conversion, RDY returns high and the conversion result is placed in the B register of the microprocessor. A2 A0 DB7 DATA BUS A2 D0 DB0 A0 A0 EN MREQ ADDRESS DECODE A0 A1 A2** *LINEAR CIRCUITRY OMITTED FOR CLARITY. ** FOR THE AD7828 ONLY 5V Z80 CS 5k AD7824* AD7828* Figure 17. AD7824/AD7828-MC68000 Interface RDY WAIT RD RD D7 TMS32010 MICROCOMPUTER DB7 A TMS32010 interface is shown in Figure 18. The AD7824/ AD7828 is operating in Mode 1 (i.e., no P WAIT states). The ADC is mapped at a port address. The following I/O instruction starts a conversion and reads the previous conversion result into the accumulator. DATA BUS DB0 D0 IN, A PA (PA = PORT ADDRESS) *LINEAR CIRCUITRY OMITTED FOR CLARITY. ** FOR THE AD7828 ONLY The port address (000 to 111) selects the analog channel to be converted. When conversion is complete, a second I/O instruction (IN, A PA) reads the up-to-date data into the accumulator and starts another conversion. A delay of 2.5 s must be allowed between conversions. Figure 16. AD7824/AD7828-Z80 lnterface Table II. Address Channel Selection Address C000 C001 C002 C003 C004 C005 C006 C007 AD7824 Channel AD7828 Channel 1 2 3 4 1 2 3 4 5 6 7 8 PA2 A2** PA1 A1 PA0 A0 MEN CS DEN RD TMS32010 D7 AD7824* AD7828* DB7 DATA BUS D0 DB0 MC68000 MICROPROCESSOR Figure 17 shows an MC68000 interface. The AD7824/AD7828 is operating in Mode 0. Assume the ADC is again assigned a memory block starting at address C000. A MOVE instruction *LINEAR CIRCUITRY OMITTED FOR CLARITY. ** FOR THE AD7828 ONLY Figure 18. AD7824/AD7828-TMS32010 Interface -10- REV. F AD7824/AD7828 5V BAND-PASS FILTER 1 BAND-PASS FILTER 2 SPEECH INPUT VDD AIN1 VDD DB7 AIN1 AIN2 AIN3 AIN4 AD7828 DATA BAND-PASS FILTER 7 AIN7 DB0 BAND-PASS FILTER 8 AIN8 A2 A1 A0 5V VREF (+) 15V 10V RD AIN2 AMP SAMPLE PULSE 5V CS CS RD WR INT DB7 DB7 DB0 AD7824 VREF AD7226 DB0 VREF (+) VREF (-) GND VDD A1 A1 A0 A0 VOUT A VOUT B VOUT C VOUT D VSS VO1 VO 2 VO 3 VO 4 DGND AGND VREF (-) GND Figure 20. 4-Channel Fast Infinite Sample-and-Hold Figure 19. Speech Analysis Using Real-Time Filtering OUTLINE DIMENSIONS 24-Lead Plastic Dual-in-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 24 13 1 12 0.180 (4.57) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.100 (2.54) BSC 0.060 (1.52) SEATING 0.050 (1.27) PLANE 0.045 (1.14) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MO-095AG CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Plastic Dual-in-Line Package [PDIP] (N-28) Dimensions shown in inches and (millimeters) 1.565 (39.7) 1.380 (35.1) 15 28 0.580 (14.73) 0.485 (12.32) 1 14 0.100 (2.54) BSC 0.625 (15.87) 0.600 (15.24) 0.015 (0.39) MIN 0.195 (4.95) 0.125 (3.18) 0.250 (6.35) MAX 0.200 (5.05) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.70 (1.77) 0.30 (0.77) SEATING PLANE 0.015 (0.381) 0.008 (0.204) COMPLIANT TO JEDEC STANDARDS MS-011AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. F -11- AD7824/AD7828 OUTLINE DIMENSIONS 24-Lead Standard Small Outline Package [SOIC] Wide Body (R-24) Dimensions shown in millimeters and (inches) 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 12 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 45 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.020) 0.33 (0.013) 8 0 SEATING 0.32 (0.0126) PLANE 0.23 (0.0091) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 14 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 45 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 0 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) PLANE BSC 0.33 (0.0130) 0.23 (0.0091) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN -12- REV. F AD7824/AD7828 OUTLINE DIMENSIONS 24-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) 0.098 (2.49) MAX 0.005 (0.13) MIN 24 13 0.310 (7.87) 0.220 (5.59) PIN 1 1 0.200 (5.08) MAX 12 0.060 (1.52) 0.015 (0.38) 1.280 (32.51) MAX 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) SEATING PLANE 0.030 (0.76) 0.100 (2.54) BSC 0.023 (0.58) 0.014 (0.36) 0.015 (0.38) 0.008 (0.20) 15 0 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP] (Q-28) Dimensions shown in inches and (millimeters) 0.100 (2.54) MAX 0.005 (0.13) MIN 28 15 0.610 (15.49) 0.500 (12.70) PIN 1 1 0.225(5.72) MAX 14 1.490 (37.85) MAX 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) MIN 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.026 (0.66) 0.014 (0.36) 0.018 (0.46) 0.008 (0.20) 15 0 0.070 (1.78) SEATING 0.030 (0.76) PLANE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Terminal Ceramic Leaded Chip Carrier [LCC] (E-28A) Dimensions shown in inches and (millimeters) 0.100 (2.54) 0.064 (1.63) 0.300 (7.62) REF 0.075 (1.91) REF 0.020 (0.51) MIN 19 26 18 0.458 (11.63) SQ 0.442 (11.23) 0.458 (11.63) MAX SQ 0.05 (1.27) BSC BOTTOM VIEW 0.075 (1.91) REF 12 11 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.028 (0.71) 0.022 (0.56) 25 28 1 0.15 (3.81) REF 4 5 0.095 (2.41) 0.075 (1.90) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. F -13- AD7824/AD7828 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 1.85 1.75 1.65 2.00 MAX 0.10 COPLANARITY 0.25 0.09 0.38 0.22 0.65 BSC 0.05 MIN SEATING PLANE 8 4 0 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28A) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 0.048 (1.22) 0.042 (1.07) 26 25 5 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.020 (0.51) MIN 0.032 (0.81) 0.026 (0.66) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) 0.120 (3.05) 0.090 (2.29) 0.430 (10.9) 0.390 (9.9) BOTTOM VIEW (PINS UP) 0.040 (1.02) 0.025 (0.64) COMPLIANT TO JEDEC STANDARDS MO-047AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN -14- REV. F AD7824/AD7828 Revision History Location Page 1/03--Data Sheet changed from REV. E to REV. F. Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to DIP/SOIC/SSOP, LCCC, AND PLCC Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Circuit Information Basic Description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Input Current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edit to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4/02--Data Sheet changed from REV. D to REV. E. Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 REV. F -15- -16- PRINTED IN U.S.A. C01323-0-1/03 (F)