© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 4 1Publication Order Number:
NCP1937/D
NCP1937
Combination Power Factor
Correction and Quasi-
Resonant Flyback
Controllers for Adapters
This combination IC integrates power factor correction (PFC) and
quasi−resonant flyback functionality necessary to implement a
compact and highly efficient Switched Mode Power Supply for an
adapter application.
The PFC stage exhibits near−unity power factor while operating in a
Critical Conduction Mode (CrM) with a maximum frequency clamp.
The circuit incorporates all the features necessary for building a robust
and compact PFC stage while minimizing the number of external
components.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 4th valley and toggles to a frequency
foldback mode with a minimum frequency clamp beyond the 4th
valley to eliminate audible noise. Skip mode operation allows
excellent e fficiency in light load conditions while consuming very low
standby power consumption.
Common General Features
•Wide VCC Range from 9 V to 30 V with Built−in Overvoltage
Protection
•High−Voltage Startup Circuit and Active Input Filter Capacitor
Dischar ge Circuitry for Reduced Standby Power
•Integrated High−Voltage Brown−Out Detector
•Integrated High−Voltage Switch Disconnects PFC Feedback Resistor
Divider to Reduce Standby Power
•Fault Input for Severe Fault Conditions, NTC
Compatible (Latch and Auto−Recovery Options)
•0.5 A / 0.8 A Source / Sink Gate Drivers
•Internal Temperature Shutdown
•Power Savings Mode Reduces Supply Current
Consumption to 70 mA Enabling Very Low Input Power
Applications
PFC Controller Features
•Critical Conduction Mode with Constant On Time
Control (Voltage Mode) and Maximum Frequency
Clamp
•Accurate Overvoltage Protection
•Bi−Level Line−Dependent Output Voltage
•Fast Line / Load Transient Compensation
•Boost Diode Short−Circuit Protection
•Feed−Forward for Improved Operation across Line and
Load
•Adjustable PFC Disable Threshold Based on Output
Power
QR Flyback Controller Features
•Valley Switching Operation with Valley−Lockout for
Noise−Free Operation
•Frequency Foldback with Minimum Frequency Clamp
for Highest Performance in Standby Mode
•Minimum Frequency Clamp Eliminates Audible Noise
•Timer−Based Overload Protection (Latched or
Auto−Recovery options)
•Adjustable Overpower Protection
•Winding and Output Diode Short−Circuit Protection
•4 ms Soft−Start Timer
www.onsemi.com
SOIC−20
Narrow Body
CASE 751BS
MARKING DIAGRAM
HV/X2
BO/X2
QFB
PControl
PONOFF
QCT
Fault
PSTimer
PFBHV
PFBLV
GND
PCS/PZC
D
PDRV
QDRV
QCS
NCP1937 = Specific Device Code
xx = A1, A2, A3, B1, B2, B3, C1, C4 or C61
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
120
NCP1937xxG
AWLYWW
VCC
QZCD
See detailed ordering and shipping information on page 5 o
f
this data sheet.
ORDERING INFORMATION
NCP1937
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3
Figure 2. Functional Block Diagram
Disable PFC
PDRV
HV/X2
VCC
+
−
+
−
PFBHV
+
In Regulation
+
Timer
−
In Regulation
Brownout
VCC_OK
Low/High Line
PUVP
PILIM1
Counter
QRDRV
QCT
CT
Setpoint
QZCD
LEB1
+
−
nQILIM2
Fault
−
QFB
QCS
LEB1
LEB2
Counter
Frequency
Clamp
LEB2
Enable BO/X2
High Voltage
Startups,
Detection, and
Logic
PFBLV
+
−
+
PONOF
F
PFC
OVP
Detection
QZCD
Temperature
nPILIM2
PILIM2
PSKIP
−
+
−
+
+
−
+
+
−
+
−
13
QDRV
Line Removal
Line Removal
VCC
Management
VCC_OK
In PSM
Valley
Select
Logic
Valley
QSkip
VCO
VCO
QOVLD
TSD
ZCD
Detect
Valley
ZCD
Detect
PFCDRV
PILIM2
PZCD
Soft−start
Central
Logic Reset
Level
Shift
ON T ime
Ramp
PControl
Low
Clamp
Disable PFC
PUVP
POVP
PZCD
PFCDRV
S
RQ
Dominant
Reset Latch
POVP
Low/High Line
PUVP
PSKIP
PILIM1
PILIM2
PFCDRV
OVP
OTP
PSTIMER In PSM
Initial Discharge
PSM
Detection
VCC_OK
QRDRV
GND
S
RQ
Dominant
Reset
Latch
QILIM2
QILIM1
QSkip
QRDRV
VCC_OK
In PSM
Low/High Line
S
S
S
S
S
S
QOVLD
nPILIM2
nQILIM2
OVP
OTP
Brownout
Line Removal
R
R
R
Line Removal
Brownout
Fault
Logic
Latch
Auto−recovery
Latch
Auto−recovery
S
TSD
QR_EN
QR_EN Soft−start
Minimum
Frequency
Oscillator QRDRV
VCO
P
CS/PZCD
In_PSM
IPSTimer1/2
VFault(OTP_in)
IOTP
VFault(OVP)
VPILIM2
VPILIM1
+
−
VCCOVP
VCC(reset)
IPCS/PZCD
VPZCD
PFCDRV
tP(tout)
Q
tPFC(off)
VPREF(xL)
VPCONTROL(MAX)
KLOW KLOW(HYS)
PFCDRV
VQILIM1
PFC
IEA
VCC(reset)
VPFB(HYS)
VPFB(disable)
IPControl(boost)
KPOVP(xL)
DPOVP(xL)
VQILIM2
IQCS
VQILIM1
VQZCD
VQZCD
tQOVLD
tonQR(MAX)
In_PSM
IQFB RQFB
QVQZCD
tQ(toutx)
VQFB
IQCT
VQZCD(th)
VQZCD(hys)
QSkip
tdelay(QSKIP)
VQFB
Soft−Start
VPOFF
VPONHYS
IPONOFF
CCC
ICC(discharge)
VCCOVP
VCC(reset)
VDD
Istart
tPisable
VQFB
/KQFB
DVPSKIP
17
10
7
11
14
6
12
1
3
20
18
5
15
16
8
9
NCP1937
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Table 1. PIN FUNCTION DESCRIPTION
Pin Out Name Function
1 HV/X2 High voltage startup circuit input. It is also used to discharge the input filter capacitors.
2Removed for creepage distance.
3 BO/X2 Performs brown−out detection for the whole IC and it is also used to discharge the input filter capacitors
and detect the line voltage range.
4Removed for creepage distance.
5 PControl Output of the PFC transconductance error amplifier. A compensation network is connected between this
pin and ground to set the loop bandwidth.
6 PONOFF A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is com-
pared to an internal voltage signal proportional to the output power. The PFC disable threshold is de-
termined by the resistor on this pin and the internal pull–up current source, IPONOFF.
7 QCT An external capacitor sets the frequency in VCO mode for the QR flyback controller.
8 Fault The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A
precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a
latch or auto−recovery depending on device option.
9 PSTimer Power savings mode (PSM) control and timer adjust. Compatible with an optocoupler for secondary con-
trol of PSM. The device enters PSM if the voltage on this pin exceeds the PSM threshold, VPS_in. A capa-
citor between this pin and GND sets the delay time before the controller enters power savings mode.
Once the controller enters power savings mode the IC is disabled and the current consumption is re-
duced to a maximum of 70 mA. The input filter capacitor discharge function is available while in power
savings mode. The controller is enabled once VPSTimer drops below VPS_out.
10 QFB Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
11 QZCD Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the
overpower compensation.
12 VCC Supply input.
13 QCS Input to the cycle−by−cycle current limit comparator for the QR Flyback section.
14 QDRV QR flyback controller switch driver.
15 PDRV PFC controller switch driver.
16 PCS/PZCD Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the de-
magnetization detection for the PFC controller.
17 GND Ground reference.
18 PFBLV Low voltage PFC feedback input. An external resistor divider is used to sense the PFC bulk voltage. The
divider low side resistor connects to this pin. This voltage is compared to an internal reference. The refer-
ence voltage is 2.5 V at low line and 4 V at high line. An internal high−voltage switch disconnects the low
side resistor from the high side resistor chain when the PFC is disabled in order to reduce input power.
19 Removed for creepage distance.
20 PFBHV High voltage PFC feedback input. An external resistor divider is used to sense the PFC bulk voltage. The
divider high side resistor chain from the PFC bulk voltage connects to this pin. An internal high−voltage
switch disconnects the high side resistor chain from the low side resistor when the PFC is disabled in
order to reduce input power.
NCP1937
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Table 2. NCP1937 DEVICE OPTIONS
Device Overload
Protection Fault OTP VBO(start) VBO(stop)
PFC
Disable
Time
PFC
Frequency
Clamp Package Shipping†
NCP1937A1DR2G Auto−Recovery Latch 111 V 97 V 0.5 s 250 kHz
SOIC−20
(Pb−Free) 2500 / Tape
& Reel
NCP1937A2DR2G Auto−Recovery Latch 111 V 97 V 0.5 s 131 kHz
NCP1937A3DR2G Auto−Recovery Latch 111 V 97 V 4 s 131 kHz
NCP1937B1DR2G Auto−Recovery Auto−Recovery 111 V 97 V 0.5 s 250 kHz
NCP1937B2DR2G Auto−Recovery Auto−Recovery 111 V 97 V 0.5 s 131 kHz
NCP1937B3DR2G Auto−Recovery Auto−Recovery 111 V 97 V 4 s 131 kHz
NCP1937C1DR2G Latch Latch 111 V 97 V 0.5 s 250 kHz
NCP1937C4DR2G Latch Latch 111 V 97 V 13 s 131 kHz
NCP1937C61DR2G Latch Latch 101 V 87 V 4 s 131 kHz
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
Table 3. MAXIMUM RATINGS (Notes 1 − 6)
Rating Pin Symbol Value Unit
High Voltage Startup Circuit Input Voltage 1 VHV/X2 −0.3 to 700 V
High Voltage Startup Circuit Input Current 1 IHV/X2 20 mA
High Voltage Brownout Detector Input Voltage 3 VBO/X2 −0.3 to 700 V
High Voltage Brownout Detector Input Current 3 IBO/X2 20 mA
PFC High Voltage Feedback Input Voltage 20 VPFBHV −0.3 to 700 V
PFC High Voltage Feedback Input Current 20 IPFBHV 0.5 mA
PFC Low Voltage Feedback Input Voltage 18 VPFBLV −0.3 to 9 V
PFC Low Voltage Feedback Input Current 18 IPFBLV 0.5 mA
PFC Zero Current Detection and Current Sense Input Voltage (Note 1) 16 VPCS/PZCD −0.3 to
VPCS/PZCD(MAX) V
PFC Zero Current Detection and Current Sense Input Current 16 IPCS/PZCD −2/+5 mA
PFC Control Input Voltage 5 VPControl −0.3 to 5 V
PFC Control Input Current 5 IPControl 10 mA
Supply Input Voltage 12 VCC(MAX) −0.3 to 30 V
Supply Input Current 12 ICC(MAX) 30 mA
Supply Input Voltage Slew Rate 12 dVCC/dt 1 V/ms
Fault Input Voltage 8 VFault −0.3 to (VCC + 1.25) V
Fault Input Current 8 IFault 10 mA
QR Flyback Zero Current Detection Input Voltage 11 VQZCD −0.9 to (VCC + 1.25) V
QR Flyback Zero Current Detection Input Current 11 IQZCD −2/+5 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (VPCS/PZCD − 5 V) / (2 kW). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pins 1, 3, and 20 are rated to the maximum voltage of the part, or 700 V.
NCP1937
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Table 3. MAXIMUM RATINGS (Notes 1 − 6)
Rating UnitValueSymbolPin
QR Feedback Input Voltage 7 VQCT −0.3 to 10 V
QR Feedback Input Current 7 IQCT 10 mA
QR Flyback Current Sense Input Voltage 13 VQCS −0.3 to 10 V
QR Flyback Current Sense Input Current 13 IQCS 10 mA
QR Flyback Feedback Input Voltage 10 VQFB −0.3 to 10 V
QR Flyback Feedback Input Current 10 IQFB 10 mA
PSTimer Input Voltage 9 VPSTimer −0.3 to 10 V
PSTimer Input Current 9 IPSTimer 10 mA
PFC Driver Maximum Voltage (Note 2) 15 VPDRV −0.3 to VPDRV(high) V
PFC Driver Maximum Current 15 IPDRV(SRC)
IPDRV(SNK)
500
800 mA
Flyback Driver Maximum Voltage (Note 2) 14 VQDRV −0.3 to VQDRV(high) V
Flyback Driver Maximum Current 14 IQDRV(SRC)
IQDRV(SNK)
500
800 mA
PFC ON/OFF Threshold Adjust Input Voltage 6 VPONOFF −0.3 to 10 V
PFC ON/OFF Threshold Adjust Input Current 6 IPONOFF 10 mA
Operating Junction Temperature N/A TJ−40 to 125 _C
Storage Temperature Range N/A TSTG –60 to 150 _C
Power Dissipation (TA = 75_C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit
Copper Clad)
Plastic Package SOIC−20NB
PD0.62 W
Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit
Copper Clad)
Plastic Package SOIC−20NB
RθJA 121
_C/W
ESD Capability (Note 6)
Human Body Model per JEDEC Standard JESD22−A114F.
Machine Model per JEDEC Standard JESD22−A115−A.
Charge Device Model per JEDEC Standard JESD22−C101E.
HBM
MM
CDM
3000
200
750
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (VPCS/PZCD − 5 V) / (2 kW). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pins 1, 3, and 20 are rated to the maximum voltage of the part, or 700 V.
NCP1937
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics Conditions Pin Symbol Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage Startup Threshold
Regulation Level in PSM
Minimum Operating Voltage
Operating Hysteresis
Delta Between PSM and VCC(off) Levels
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
VCC increasing
VQFB = 0, VPSTimer = 3 V
VCC decreasing
VCC(on) − VCC(off)
VCC(PS_on) − VCC(off)
VCC decreasing
VCC increasing,
IHV/X2 = 650 mA
12 VCC(on)
VCC(PS_on)
VCC(off)
VCC(HYS)
VCC(DPS_off)
VCC(reset)
VCC(inhibit)
16
–
8.2
7.7
1.65
4.5
0.3
17
11
8.8
–
2.20
5.5
0.7
18
–
9.4
–
2.75
7.5
0.95
V
Startup Current in Inhibit Mode VCC = 0 V, VBO/X2 = 0 V
VCC = 0 V, VHV/X2 = 0 V 12
12 Istart1A
Istart1B
0.20
0.20 0.50
0.50 0.65
0.65 mA
Startup Current Operating Mode
PSM Mode
VCC = VCC(on) – 0.5 V
VHV/X2 = 100 V,
VBO/X2 = VCC
VBO/X2 = 100 V,
VHV/X2 = VCC
VHV/X2 = 100 V,
VBO/X2 = 0 V
VBO/X2 = 100 V,
VHV/X2 = 0 V
12
12
Istart2A
Istart2B
Istart2A_PSM
Istart2B_PSM
2.5
2.5
9
9
15
15
5
5
20
20
mA
Startup Circuit Off−State Leakage Current V HV/X2 = 500 V 1 IHV/X2 (off) – – 3 mA
Minimum Startup Voltage Istart2A = 1 mA, VCC =
VCC(on) – 0.5 V
Istart2B = 1 mA, VCC =
VCC(on) – 0.5 V
1
3
VHV/X2(MIN)
VBO/X2(MIN)
–
–
–
–
40
40
V
Minimum Startup Voltage in PSM Istart = 9 mA, VCC =
VCC(PS_on) – 0.5 V
Istart = 9 mA, VCC =
VCC(PS_on) – 0.5 V
1
3
VHV/X2(MIN)
VBO/X2(MIN)
–
–
–
–
60
60
V
VCC Overvoltage Protection Threshold 12 VCC(OVP) 27 28 29 V
VCC Overvoltage Protection Delay 12 tdelay(VCC_OVP) 30.0 ms
Supply Current In Power Savings Mode
Before Startup, Fault or Latch
Flyback in Skip, PFC Disabled
Flyback in Skip, PFC in Skip
Flyback Enabled, QDRV Low, PFC Disabled
Flyback Enabled, QDRV Low, PFC in Skip
PFC and Flyback switching at 70 kHz
PFC and Flyback switching at 70 kHz
VCC = VCC(on) – 0.5 V
VQFB = 0.35 V
VQFB = 0.35 V,
VPControl < VPSKIP
VQZCD = 1 V,
VQZCD = 1 V,
VPControl < VPSKIP
CQDRV = CPDRV = open
12 ICC1a
ICC2
ICC3a
ICC3b
ICC4
ICC5
ICC6
ICC7
– –
0.15
0.3
0.5
0.85
1.1
1.5
2.8
0.07
0.25
0.4
1.0
1.35
1.8
4.0
5.2
mA
INPUT FILTER DISCHARGE
Current Consumption in Discharge Mode VCC = VCC(off) + 200 mV 12 ICC(discharge) 8.0 11.5 15.0 mA
Line Voltage Removal Detection Threshold VBO/X2 decreasing 3 Vlineremoval 20 30 40 V
Line Voltage Removal Detection Delay VBO/X2 stays above
Vlineremoval 3 tlineremoval 130 200 270 ms
NCP1937
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
BROWN−OUT DETECTION
System Brown−out Thresholds
(See Table 2 for device options) VBO/X2 increasing
VBO/X2 decreasing 3 VBO(start)
VBO(stop) 102
86 111
101 120
116 V
System Brown−out Thresholds
(See Table 2 for device options) VBO/X2 increasing
VBO/X2 decreasing 3 VBO(start)
VBO(stop) 83
79 97
87 111
95 V
Brown−out Hysteresis VBO/X2 increasing 3 VBO(hys) 4 16 V
Brown−out Detection Blanking Time VBO/X2 decreasing,
duration below VBO(stop)
for a Brown−out fault
3 tBO(stop) 43 54 65 ms
Brown−out Drive Disable Threshold VBO/X2 decreasing,
threshold to disable
switching
3 VBO(DRV_disable) 20 30 40 V
Line Level Detection Threshold
Line Level Detection Threshold (C61) VBO/X2 increasing 3 VBO(lineselect) 216
199 240
221 264
243 V
High to Low Line Mode Selector Timer VBO/X2 decreasing 3 thigh to low line 43 54 65 ms
Low to High Line Mode Selector Timer VBO/X2 increasing 3 tlow to high line 200 350 450 ms
Brownout Pin Off State Leakage Current V BO/X2 = 500 V 3 IBO/X2(off) – – 42 mA
PFC MAXIMUM OFF TIME TIMER
Maximum Off Time VPCS/PZCD > VPILIM2
15 tPFC(off1)
tPFC(off2)
100
700 200
1000 300
1300 ms
PFC CURRENT SENSE
Cycle by Cycle Current Sense Threshold 16 VPILIM1 0.45 0.50 0.55 V
Cycle by Cycle Leading Edge
Blanking Duration 16 tPCS(LEB1) 250 325 400 ns
Cycle by Cycle Current Sense
Propagation Delay 16 tPCS(delay1) 100 200 ns
Abnormal Overcurrent Fault Threshold 16 VPILIM2 1.12 1.25 1.38 V
Abnormal Overcurrent Fault Leading Edge
Blanking Duration 16 tPCS(LEB2) 100 175 250 ns
Abnormal Overcurrent Fault Propagation Delay 16 tPCS(delay2) 100 200 ns
Number of Consecutive Abnormal Overcurrent
Faults to Enter Latch Mode 15 nPILIM2 – 4 –
Pull−up Current Source VPCS/PZCD = 1.5 V 16 IPCS/PZCD 0.7 1.0 1.3 mA
PFC REGULATION BLOCK
Reference Voltage VBO/X2 > VBO(lineselect)
VBO/X2 < VBO(lineselect)
18 VPREF(HL)
VPREF(LL)
3.92
2.45 4.00
2.50 4.08
2.55 V
Error Amplifier Current Source
Sink
Source
Sink
PFC Enabled
VPFBLV = 0.96 x VPREF(HL)
VPFBLV = 1.04 x VPREF(HL)
VPFBLV = 0.96 x VPREF(LL)
VPFBLV = 1.04 x VPREF(LL)
5 IEA(SRCHL)
IEA(SNKHL)
IEA(SRCLL)
IEA(SNKLL)
16
16
10
10
32
32
20
20
48
48
30
30
mA
Open Loop Error Amplifier Transconductance VPFBLV = VPREF(LL) ± 4%
VPFBLV = VPREF(HL) ± 4% 5 gm
gm_HL
100
100 200
200 300
300 mS
Maximum Control Voltage VPFBLV * KLOW(PFCxL),
CPControl = 10 nF 5 VPControl(MAX) – 4.5 – V
Minimum Control Voltage (PWM Offset) VPFBLV * KPOVP(xL),
CPControl = 10 nF 5 VPControl(MIN) – 0.5 – V
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
PFC REGULATION BLOCK
EA Output Control Voltage Range VPControl(MAX) -
VPControl(MIN) 5DVPControl 3.8 4.0 4.2 V
Delta Between Minimum Control Voltage and
Lower Clamp PControl Voltages VPControl(MIN) −
VPClamp(lower) 5DVPClamp(lower) −125 −100 −75 mV
Ratio between the Vout Low Detect Threshold
and the Regulation Level VPFBLV decreasing,
VBOOST / VPREF(HL)
VPFBLV decreasing,
VBOOST / VPREF(LL)
18 KLOW(PFCHL)
KLOW(PFCLL)
0.940
0.940
0.945
0.945
0.950
0.950
Ratio between the Vout Low Exit Threshold
and the Regulation Level VPFBLV increasing 18 KLOW(HYSHL)
KLOW(HYSLL)
0.950
0.950 0.960
0.960 0.965
0.965
Source Current During Vout Low Detect 5 IPControl(boost) 190 240 290 mA
PFC In Regulation Threshold VPControl increasing 5 IIn_Regulation −6.5 – 0 mA
Resistance of Internal Pull Down Switch IPControl = 5 mA 5 RPControl 4 25 50 W
PFC SKIP MODE
Delta Between Skip Level and Lower Clamp
PControl Voltages VPControl decreasing,
measured from
VPClamp(lower)
5DVPSKIP 5 25 50 mV
PFC Skip Hysteresis VPControl increasing 5 VPSKIP(HYS) 25 50 75 mV
Delay Exiting Skip Mode Apply 1 V step from
VPClamp(lower) 5 tdelay(PSKIP) – 50 60 ms
PFC FAULT PROTECTION
Ratio between the Hard Overvoltage Pro-
tection Threshold and Regulation Level VPFBLV increasing
KPOVP(LL) =
VPFBLV/VPREF(LL)
KPOVP(HL) =
VPFBLV/VPREF(HL)
18 KPOVP(LL)
KPOVP(HL)
1.06
1.05
1.08
1.06
1.10
1.08
Soft Overvoltage Protection Threshold VPSOVP(LL) = soft
overvoltage level
DPOVP(LL) = KPOVP *
VPREF(LL) − VPSOVP(LL)
DPOVP(HL) = KPOVP *
VPREF(HL) − VPSOVP(HL)
18 DPOVP(LL)
DPOVP(HL)
20
20
–
–
55
55
mV
PFC Feedback Pin Disable Threshold VPFBLV decreasing 18 VPFB(disable) 0.225 0.30 0.35 V
PFC Feedback Pin Enable Threshold VPFBLV increasing 18 VPFB(enable) 0.275 0.35 0.40 V
PFC Feedback Pin Hysteresis VPFBLV increasing 18 VPFB(HYS) 25 50 mV
PFC Feedback Disable Delay 18 tdelay(PFB) 30 ms
PFC ON TIME CONTROL
PFC Maximum On Time VPControl = VPControl(MAX),
VBO/X2 = 163 V
VBO/X2 = 325 V
15 ton1a
ton1b
12.5
4.25 15
5.00 17.5
5.75
ms
Minimum On−Time VPControl = VPControl(MIN) 15 tP(on−time) – – 200 ns
PFC Frequency Clamp
(See Table 2 for device options) 15 fclamp(PFC) 112
215 131
250 150
285 kHz
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
PFC DISABLE
Voltage to Current Conversion Ratio VQFB = 3 V, Low Line
VQFB = 3 V, High Line 6 Iratio1(QFB/PON)
Iratio2(QFB/PON)
14
14 15
15 16
16 mA
PFC Disable Threshold VPONOFF decreasing 6 VPOFF 1.9 2.0 2.1 V
PFC Enable Hysteresis VPONOFF = increasing 6 VPONHYS 0.135 0.160 0.185 V
PONOFF Operating Mode Voltage tdemag/T = 70%,
RPONOFF = 191 kW,
CPONOFF = 1 nF
VQFB = 1.8 V (decreasing)
VQFB = 3 V (decreasing) 6 VPONOFF1
VPONOFF2
1.08
1.8 1.20
2.0 1.32
2.2
V
PFC Disable Timer
(See Table 2 for device options) Disable Timer 6 tPdisable 0.45
3.6
11.7
0.50
4
13
0.55
4.4
14.3
s
PFC Enable Filter Delay 6 tPenable(filter) 50 100 150 ms
PFC Enable Timer PONOFF Increasing 6 tPenable 200 – 500 ms
PFC Off−State Leakage Current VPONOFF = 1 V,
VPFBHV = 500 V 20 IPFBHV(off) – 0.1 3 mA
PFC Feedback Switch On Resistance VPFBHV = 4.25 V,
IPFBHV = 100 mA20 RPFBswitch(on) – – 10 kW
PFC GATE DRIVE
Rise T ime (10−90%) VPDRV from 10 to 90%
of VCC 15 tPDRV(rise) – 40 80 ns
Fall T ime (90−10%) 90 to 10% of VPDRV 15 tPDRV(fall) – 20 40 ns
Driver Resistance Source
Sink 15 RPDRV(SRC)
RPDRV(SNK)
13
7W
Current Capability Source
Sink VPDRV = 2 V
VPDRV = 10 V 15 IPDRV(SRC)
IPDRV(SNK)
–
–500
800 –
–mA
High State Voltage VCC = VCC(off) + 0.2 V,
RPDRV = 10 kW
VCC = 26 V,
RPDRV = 10 kW
15 VPDRV(high) 8
10
–
12
–
14
V
Low Stage Voltage VFault = 4 V 15 VPDRV(low) – – 0.25 V
PFC ZERO CURRENT DETECTION
Zero Current Detection Threshold VPCS/PZCD rising
VPCS/PZCD falling 16 VPZCD(rising)
VPZCD(falling)
675
200 750
250 825
300 mV
Hysteresis on Voltage Threshold VPZCD(rising) – VPZCD(falling) 16 VPZCD(HYS) 375 500 625 mV
Propagation Delay 16 tPZCD 50 100 170 ns
Input Voltage Excursion Upper Clamp
Negative Clamp IPCS/PZCD = 1 mA
IPCS/PZCD = −2 mA 16 VPCS/PZCD(MAX)
VPCS/PZCD(MIN)
6.5
−0.9 7
−0.7 7.5
0V
Minimum detectable ZCD Pulse Width 16 tSYNC – 70 200 ns
Missing Valley Timeout Timer Measured after last ZCD
transition 16 tP(tout) 8 10 12 ms
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
QR FLYBACK GATE DRIVE
Rise T ime (10−90%) VQDRV from 10 to 90% 14 tQDRV(rise) – 40 80 ns
Fall T ime (90−10%) 90 to 10% of VQDRV 14 tQDRV(fall) – 20 40 ns
Driver Resistance Source
Sink 14 RQDRV(SRC)
RQDRV(SNK)
13
7W
Current Capability Source
Sink VQDRV = 2 V
VQDRV = 10 V 14 IQDRV(SRC)
IQDRV(SNK)
–
–500
800 –
–mA
High State Voltage VCC = VCC(off) + 0.2 V,
RQDRV = 10 kW
VCC = 26 V,
RQDRV = 10 kW
14 VQDRV(high) 8
10
–
12
–
14
V
Low Stage Voltage VFault = 4 V 14 VQDRV(low) – – 0.25 V
QR FLYBACK FEEDBACK
Internal Pull−Up Current Source 10 IQFB 48 50 52 mA
Feedback Input Open Voltage 10 VQFB(open) 4.8 5.0 5.2 V
VQFB to Internal Current Setpoint Division Ratio 10 KQFB 3.95 4.0 4.15 –
QFB Pull Up Resistor VPSTimer = 3 V ;
VQFB = 0.4 V 10 RQFB 365 400 435 kW
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th valley to VCO
Transition from VCO to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
VQFB decreasing
VQFB decreasing
VQFB decreasing
VQFB decreasing
VQFB increasing
VQFB increasing
VQFB increasing
VQFB increasing
10 VH2D
VH3D
VH4D
VHVCOD
VHVCOI
VH4I
VH3I
VH2I
1.316
1.128
0.846
0.752
1.316
1.504
1.692
1.880
1.400
1.200
0.900
0.800
1.400
1.600
1.800
2.000
1.484
1.272
0.954
0.848
1.484
1.696
1.908
2.120
V
Skip Threshold VQFB decreasing 10 VQSKIP 0.35 0.40 0.45 V
Skip Hysteresis VQFB increasing 10 VQSKIP(HYS) 25 50 75 mV
Delay Exiting Skip Mode to 1st QDRV Pulse Apply 1 V step from VQSKIP 10 tdelay(QSKIP) – – 10 ms
Maximum On Time 14 tonQR(MAX) 26 32 38 ms
QR FLYBACK TIMING CAPACITOR
QCT Operating Voltage Range VQFB = 0.5 V 7 VQCT(peak) 3.815 4.000 4.185 V
On Time Control Source Current VQCT = 0 V 7 IQCT 18 20 22 mA
Minimum voltage on QCT Input 7 VQCT(min) – – 90 mV
Minimum Operating Frequency in VCO Mode VQCT = VQCT(peak) +
100 mV 7 fVCO(MIN) 23.5 27 30.5 kHz
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
QR FLYBACK DEMAGNETIZATION INPUT
QZCD threshold voltage VQZCD decreasing 11 VQZCD(th) 35 55 90 mV
QZCD hysteresis VQZCD increasing 11 VQZCD(HYS) 15 35 55 mV
Demagnetization Propagation Delay VQZCD step from
4.0 V to −0.3 V 11 tDEM – 150 250 ns
Input Voltage Excursion Upper Clamp
Negative Clamp IQZCD = 5.0 mA
IQZCD = −2.0 mA 11 VQZCD(MAX)
VQZCD(MIN)
12.4
−0.9 12.7
−0.7 13.25
0V
Blanking Delay After Turn−Off 11 tZCD(blank) 2 3 4 ms
Timeout After Last Demagnetization Detection During soft−start
After soft−start 14 tQ(tout1)
tQ(tout2)
80
5.1 100
6120
6.9 ms
QR FLYBACK CURRENT SENSE
Current Sense Voltage Threshold VQCS increasing
VQCS increasing,
VQZCD = 1 V
13 VQILIM1a
VQILIM1b
0.760
0.760 0.800
0.800 0.840
0.840 V
Cycle by Cycle Leading Edge Blanking
Duration 13 tQCS(LEB1) 220 275 350 ns
Cycle by Cycle Current Sense Propagation
Delay 13 tQCS(delay1) – 125 175 ns
Immediate Fault Protection Threshold VQCS increasing,
VQFB = 4 V 13 VQILIM2 1.125 1.200 1.275 V
Abnormal Overcurrent Fault Leading Edge
Blanking Duration 13 tQCS(LEB2) 90 120 150 ns
Abnormal Overcurrent Fault Propagation De-
lay 13 tQCS(delay2) – 125 175 ns
Number of Consecutive Abnormal Overcurrent
Faults to Enter Latch Mode 13 nQILIM2 – 4 –
Minimum Peak Current Level in VCO Mode VQFB = 0.4 V,
VQCS increasing 13 Ipeak(VCO) 11 12.5 14 %
Set point decrease for VQZCD = − 250 mV VQCS Increasing,
VQFB = 4 V 13 VOPP(MAX) 28 31.25 33 %
Overpower Protection Delay 11 tQOPP(delay) – 125 175 ns
Pull−up Current Source VQCS = 1.5 V 13 IQCS 0.7 1.0 1.3 mA
QR FLYBACK F AULT PROTECTION
Soft−Start Period 13 tSSTART 2.8 4.0 5.0 ms
Flyback Overload Fault Timer VQCS = VQILIM1 13 tQOVLD 60 80 100 ms
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Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VBO/X2 = 120 V, VHV/X2 = 120 V, VFault = open, VRPFBHV = 20 V,
VPFBLV = 2.4 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, VPSTimer = 0 V, RPFBHV = 200 kW,
CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25_C, for min/max values, TJ is – 40_C to 125_C,
unless otherwise noted)
Characteristics UnitMaxTypMinSymbolPinConditions
COMMON FAULT PROTECTION
Overvoltage Protection (OVP) Threshold VFault increasing 8 VFault(OVP) 2.79 3.00 3.21 V
Delay Before Fault Confirmation
Used for OVP Detection
Used for OTP Detection VFault increasing
VFault decreasing
8tdelay(Fault_OVP)
tdelay(Fault_OTP)
22.5
22.5 30.0
30.0 37.5
37.5
ms
Overtemperature Protection (OTP) Threshold
(Note 7) VFault decreasing 8 VFault(OTP_in) 0.38 0.40 0.42 V
Overtemperature Protection (OTP) Exiting
Threshold (Note 7) VFault increasing,
Options B and D 8 VFault(OTP_out) 0.874 0.920 0.966 V
OTP Pull−up Current Source (Note 7) VFault =
VFault(OTP_in) + 0.2 V
TJ = 110_C
8IFault(OTP)
IFault(OTP_110)
42.5
–45.5
45.5 48.5
–
mA
Fault Input Clamp Voltage VFault = open 8 VFault(clamp) 1.5 1.75 2.0 V
Fault Input Clamp Series Resistor RFault(clamp) 1.32 1.55 1.82 kW
POWER SAVINGS MODE
PSM Enable Threshold VPSTimer increasing 9 VPS_in 3.325 3.500 3.675 V
PSM Disable Threshold VPSTimer decreasing 9 VPS_out 0.45 0.50 0.55 V
PSTimer Pull Up Current Sources VPSTimer = 0.9 V
VPSTimer = 3.4 V 9 IPSTimer1
IPSTimer2
9
800 10
1000 11
1200 mA
IPSTimer2 Enable Threshold 9 VPSTimer2 0.95 1.0 1.05 V
Filter Delay Before Entering PSM 9 tdelay(PS_in) 40 ms
Startup Circuits Turn−on Thresholds in PSM VHV_X2 increasing
VBO_X2 increasing 1
3VHV_X2(PS)
VBO_X2(PS)
20
20 30
30 40
40 V
PSTimer Discharge Current VPSTimer = VPSTimer(off)
+ 10 mV 9 IPSTimer(DIS) 200 – – mA
PSTimer Discharge T urn Off Threshold VPSTimer decreasing 9 VPSTimer(off) 50 100 150 mV
THERMAL PROTECTION
Thermal Shutdown Temperature increasing N/A TSHDN 150 _C
Thermal Shutdown Hysteresis Temperature decreasing N/A TSHDN(HYS) 40 _C
7. NTC with R110 = 8.8 kW (TTC03−474)
NCP1937
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DETAILED OPERATING DESCRIPTION
Introduction
The NCP1937 is a combination critical mode (CrM)
power factor correction (PFC) and quasi−resonant (QR)
flyback controller optimized for off−line adapter
applications. This device includes all the features needed to
implement a highly efficient adapter with extremely low
input power in no−load conditions.
This device reduces standby input power by integrating an
active input filter capacitor discharge circuit and
disconnecting the PFC feedback resistor divider when the
PFC is disabled.
High Voltage Startup Circuit
The NCP1937 integrates two high voltage startup circuits
accessible by the HV_X2 and BO_X2 pins. The startup
circuits are also used for input filter capacitor discharge. The
BO_X2 input is also used for monitoring the ac line voltage
and detecting brown−out faults. The startup circuits are
rated at a maximum voltage of 700 V.
A startup regulator consists of a constant current source
that supplies current from the ac input terminals (Vin) to the
supply capacitor on the VCC pin (CCC). The startup circuit
currents (Istart2A/B) are typically 3.75 mA. Istart2A/B are
disabled if the VCC pin is below VCC(inhibit). In this
condition the startup current is reduced to Istart1A/B,
typically 0.5 mA. The internal high voltage startup circuits
eliminate the need for external startup components. In
addition, these regulators reduce no load power and increase
the system efficiency as they use negligible power in the
normal operation mode.
Once CCC is charged to the startup threshold, VCC(on),
typically 17 V, the startup regulators are disabled and the
controller is enabled. The startup regulators remain disabled
until VCC falls below the minimum operating voltage
threshold, VCC(off), typically 8.8 V. Once reached, the PFC
and flyback controllers are disabled reducing the bias
current consumption of the IC. Both startup circuits are then
enabled allowing VCC to charge back up.
In power savings mode VCC is regulated by enabling the
startup circuits once the supply voltage decays below
VCC(PS_on), typically 11 V. The startup circuit is disabled
once VCC exceeds VCC(PS_on). This provides enough
headroom from VCC(off) to maintain a supply voltage and
allow the controller to detect the line voltage removal in
order to discharge the input filter capacitor(s). In this mode,
the supply capacitor is charged by the startup circuit on the
HV_X2 and BO_X2 pins once the voltage on these pin
exceeds 30 V, typically. This reduces the average voltage
during which the startup circuit is enabled reducing power
consumption. Both startup circuits are enabled once the
controller exits power savings mode in order to quickly
charge V CC. A new startup sequence commences once VCC
reaches VCC(on).
A dedicated comparator monitors VCC when the QR stage
is enabled and latches off the controller if VCC exceeds
VCC(OVP), typically 28 V.
The controller is disabled once a fault is detected. The
controller will restart the next time VCC reaches VCC(on) and
all non−latching faults have been removed.
The supply capacitor provides power to the controller
during power up. The capacitor must be sized such that a
VCC voltage greater than VCC(off) is maintained while the
auxiliary supply voltage is building up. Otherwise, VCC will
collapse and the controller will turn off. The operating IC
bias current, ICC4, and gate charge load at the drive outputs
must be considered to correctly size CCC. The increase in
current consumption due to external gate charge is
calculated using Equation 1.
ICC(gate charge) +f@QG(eq. 1)
where f i s the operating frequency and QG is the gate char ge
of the external MOSFETs.
Line Voltage Sense
The BO/X2 pin provides access to the brown−out and line
voltage detectors. It also provides access to the input filter
capacitor discharge circuit. The brown−out detector detects
mains interruptions and the line voltage detector determines
the presence of either 1 10 V or 220 V ac mains. Depending
on the detected input voltage range device parameters are
internally adjusted to optimize the system performance.
This pin connects to either line or neutral to achieve
half−wave rectification as shown in Figure 3. A diode is used
to prevent the pin from going below ground. A resistor in
series with the BO/X2 pin can be used for protection, but a
low value (< 3 kW) resistor should be used to reduce the
voltage offset while sensing the line voltage.
Figure 3. Brown−out and Line Voltage Detectors
Configuration
The flyback stage is enabled once VBO_X2 is above the
brown−out threshold, VBO(start), and VCC reaches VCC(on).
The high voltage startups are immediately enabled when the
voltage on VBO_X2 crosses over the brown−out start
threshold, V BO(start), to ensure that device is enabled quickly
upon exiting a brown−out state. Figure 4 shows typical
power up waveforms.
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15
time
time
VCC
time
QDRV
Startup Startup
Startup turns on when
device exits a brown−out
Figure 4. Startup Timing Diagram
VBO_X2
VBO(start)
VBO/X2(MIN)
VCC(on)
VCC(off)
VCC(inhibit)
current = Istart1 current = Istart2
A timer is enabled once VBO_X2 drops below its stop
threshold, V BO(stop). If the timer, tBO, expires the device will
begin monitoring the voltage on VBO_X2 and disable the
PFC and flyback stages when that voltage is below the
Brown−out Drive Disable threshold, VBO(DRV_disable),
typically 3 0 V. This ensures that device switching is stopped
in a low energy state which minimizes inductive voltage
kick from the EMI components and ac mains. The timer, tBO,
typically 54 ms, is set long enough to ignore a single cycle
drop−out.
Line Voltage Detector
The input voltage range is detected based on the peak
voltage measured at the BO_X2 pin. Discrete values are
selected for the PFC stage gain (feedforward) depending on
the input voltage range. The controller compares VBO_X2 to
an internal line select threshold, VBO(lineselect). Once
VBO_X2 exceeds VBO(lineselect), the PFC stage operates in
“high line” (Europe/Asia) or “220 Vac” mode. In high line
mode the maximum on time is reduced by a factor of 3,
resulting in a maximum output power independent of input
voltage.
Figure 5 shows typical operation for the line voltage
detector. The default power−up mode of the controller is low
line. The controller switches to “high line” mode if VBO_X2
exceeds the line select threshold for longer than the low to
high line timer, t(low to high line), typically 300 ms, as long as
it was not previously in high line mode. If the controller has
switched from “high line” to “low line” mode, the low to
high line timer, t (low to high line), is inhibited until VBO/X2 falls
below VBO(stop). This prevents the controller from toggling
back to “high line” until at least one VBO(stop) transition has
occurred. The timer and logic is included to prevent
unwanted noise from toggling the operating line level.
In “high line” mode the high to low line timer, t (high to low
line), (typically 54 ms) is enabled once VBO_X2 falls below
VBO(lineselect). It is reset once VBO_X2 exceeds
VBO(lineselect). The controller switches back to “low line”
mode if the high to low line timer expires.
NCP1937
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16
time
High
Line
Entered
HL
transition
blanked by
tlow to high line
t(high to low line)
Line
Timer
Reset
Line
Timer
Starts Line
Timer
Starts
Low Line
Entered
Line
Timer
Expires
t(low to high line)
time
High Line Low Line
VBO/X2
Low Line
Low Line
Select
Timer
Operating
Mode
time
Transition to
High Line
Allowed? Yes No Yes
HL transition
blanked by
VBO(stop)
counter
VBO(stop)
Figure 5. Line Detector Waveforms
VBO(lineselect)
Input Filter Capacitor Discharge
Safety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. A
resistor network is the most common method to meet this
requirement. Unfortunately, the resistor network consumes
power across all operating modes and is a major contributor
to the total input power dissipation during light−load and
no−load conditions.
The NCP1937 eliminates the need for external discharge
resistors by integrating active input filter capacitor
discharge circuitry. A novel approach is used to reconfigure
the high voltage startup circuits to discharge the input filter
capacitors upon removal of the ac line voltage.
Once the controller detects the absence of the ac line
voltage, the controller is disabled and VCC is discharged by
a current source, ICC(discharge), typically 11.5 mA. This will
cause V CC to fall down to VCC(off). Upon reaching VCC(off),
both startup circuits are enabled. The startup circuits will
then source current from the BO_X2 and HV_X2 inputs to
the VCC pin and discharge the input filter capacitors by
transferring its charge to the VCC capacitor(s). The input
filter capacitor(s) are typically discharged once the startup
circuit turns on the 1st time because the energy stored in the
input filter capacitor(s) is significantly lower than the ener gy
needed to charge the VCC capacitor from VCC(off) to
VCC(on). After the initial discharge the controller enters a
low current mode (ICC2) once VCC drops to VCC(off).
In the event that the input filter capacitor is not fully
discharged, a l a rger VCC capacitor should be used. But, this
is not a concern for most applications because the supply
capacitor value will be large enough to maintain VCC during
skip operation. Figure 6 shows typical behavior of the filter
capacitor discharge when the ac line is removed.
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Figure 6. Input Filter Capacitor Discharge Waveforms
QDRV
HV Startups Turn OnAC Mains Unplugged
0 V
Input Filter Cap
Discharged
VCC(off)
VCC
VAC
ICC(discharge) Begins
tlineremoval
The d iode c onnecting t he A C l ine t o the B O_X2 p in s hould
be placed after the system fuse. A resistor in series with the
BO_X2 pin is recommended to limit the current during
transient e vents. A l ow value r esistor ( < 3 k W) s hould b e u sed
to r educe t he v oltage d rop w hen t he s tartup c ircuit i s e nabled.
Power Savings Mode
The NCP1937 has a low current consumption mode
known as power savings mode (PSM). The supply current
consumption in this mode is below 70 mA. PSM operation
is controlled by an external control signal. This signal is
typically generated on the secondary side of the power
supply and fed via an optocoupler.
The NCP1937 is configured as active on logic, that is it
enters PSM in the absence of the control signal. The control
signal is applied to the PSTimer pin. The block diagram for
NCP1937 PS Timer pin is shown in Figure 7. Power savings
mode operating waveforms for the NCP1937 are shown in
Figure 8.
The NCP1937 controller starts once VCC reaches VCC(on)
and no faults are present. At this time the current source on
the PSTimer pin, IPSTimer1, is enabled. IPSTimer1 is typically
10 mA. The current source charges the capacitor connected
from this pin to ground. Once VPSTimer reaches VPSTimer2 a
2nd current source, IPSTimer2, is enabled to speed up the
charge of CPSM. VPSTimer2 and IPSTimer2 are typically 1 V
and 1 mA, respectively. The controller enters PSM if the
voltage on VPSTimer exceeds VPS_in, typically 3.5 V. An
external optocoupler or switch needs to pull down on this pin
before its voltage reaches VPS_in to prevent entering PSM.
Once the controller enters PSM, IPSTimer1/2 is disabled. A
resistor between this pin and ground dischar ges the PSTimer
capacitor. The controller exits PSM once VPSTimer drops
below VPS_out, typically 0.5 V. Once the QR stage is
enabled, the capacitor on the PST imer pin is dischar ged with
an internal pull down transistor. The transistor is disabled
once VPSTimer falls below its minimum operating level,
VPSTimer(MIN) (maximum of 50 mV). The time to enter PSM
mode is calculated using Equations 2 through 4. The time to
exit PSM mode is calculated using Equation 5.
tPSM(in)
+
tPSM(in1)
)
tPSM(in2)
(eq. 2
)
t
PSM(in1) +−RPSMCPSM @In
ǒ
1− VPSTimer2
I
PSTimer1
@R
PSMǓ
(eq. 3
)
t
PSM(in2) [−RPSMCPSM @In
ǒ
1−VPS_in−VPSTimer2
IPSTimer2 @RPSM
Ǔ
(eq. 4
)
t
PSM(out) +−RPSMCPSM @InǒVPS_out
VPS_in Ǔ(eq. 5
)
In PSM the startup circuits on the HV_X2 and BO_X2
pins work to maintain VCC above VCC(off). The input filter
capacitor discharge circuitry continues operation in PSM.
The supply voltage is maintained in PSM by enabling one of
the startup circuits once VCC falls below VCC(PS_on)
(typically 11 V) and either VHV_X2 exceeds VHV_X2(PS) or
VBO_X2 exceeds VBO_X2(PS) (typically 30 V). The startup
circuit is disabled once VCC exceeds VCC(PS_on). A voltage
offset i s observed on VCC while the startup circuit is enabled
due to the capacitor ESR. This will cause the startup circuit
to turn off because VCC exceeds VCC(PS_on). Internal
circuitry prevents the startup circuit from turning on
multiple times during the same ac line half−cycle. The
complementary startup circuit will then turn on during the
next half−cycle. Eventually, VCC will be regulated several
millivolts below VCC(PS_on). The offset is dependent on the
capacitor ESR.
This architecture enables the startup circuit for the exact
amount of time needed to regulate VCC. This results in a
significant reduction in power dissipation because the
average input voltage is greatly reduced.
NCP1937
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19
Fault Input
The NCP1937 includes a dedicated fault input accessible
via the Fault pin. The controller can be latched by pulling the
pin above the upper fault threshold, VFault(OVP), typically
3.0 V. The controller is disabled if the Fault pin voltage,
VFault, is pulled below the lower fault threshold,
VFault(OTP_in), typically 0.4 V. The lower threshold is
normally used for detecting an overtemperature fault. The
controller operates normally while the Fault pin voltage is
maintained within the upper and lower fault thresholds.
Figure 9 shows the architecture of the Fault input.
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor . A pull up
current source IFault(OTP), (typically 45.5 mA) generates a
voltage drop across the thermistor. The resistance of the
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
VFault(OTP_in). Options A and C latch−off the controller after
an overtemperature fault is detected. In Options B and D the
controller is re−enabled once the fault is removed such that
VFault increases above VFault(OTP_out) and VCC reaches
VCC(on). Figure 10 shows typical waveforms related to the
latch option whereas Figure 11 shows waveforms of the
auto−recovery option.
An active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reach
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
RFault(clamp) at VFault(clamp)). The upper fault threshold is
intended to be used for an overvoltage fault using a Zener
diode and a resistor in series from the auxiliary winding
voltage, VAUX. The controller is latched once VFault exceeds
VFault(OVP).
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
blanking delays, tdelay(Fault_OVP) and tdelay(Fault_OTP) are
both typically 30 ms. A fault is detected if the fault condition
is asserted for a period longer than the blanking delay.
A bypass capacitor is usually connected between the Fault
and GND pins and it will take some time for VFault to reach
its steady state value once IFault(OTP) is enabled. Therefore,
a lower fault (i.e. overtemperature) is ignored during
soft−start. In Options B and D, IFault(OTP) remains enabled
while the lower fault is present independent of VCC in order
to provide temperature hysteresis. The controller can detect
an upper OVP fault once V CC exceeds VCC(reset). The OVP
fault detection remains active provided the device is not in
PSM.
Once the controller is latched, it is reset if a brown−out
condition is detected or if VCC is cycled down to its reset
level, VCC(reset). In the typical application these conditions
occur only if the ac voltage is removed from the system.
Prior to reaching VCC(reset), Vfault(clamp) is set at 0 V.
Figure 9. Fault Detection Schematic
VDD Latch
Soft−start
end
Fault
−
+blanking
blanking
−
+
S
R
Q
VAUX
NTC
Thermistor
Auto−restart
Control Auto−restart
BO_OK
Reset
Line Removal
Option
Hysteresis
Control
VFault(clamp)
RFault(clamp)
VFault(OTP)
IFault(OTP)
VFault(OVP)
tdelay(Fault_OVP)
tdelay(Fault_OTP)
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Figure 10. Latch−off Function Timing Diagram
QDRV
time
OTP
Fault
Flag
OTP Fault Detected
tdelay(Fault_OTP)
VCC(off)
VCC(on)
VCC
VFault
VFault(clamp)
VFault(OTP)
Figure 11. OTP Auto−recovery Timing Diagram
QDRV
time
OTP
Fault
Flag (OTP Fault
Ignored)
OTP Fault is Cleared
OTP Fault Detected tSSTART
tdelay(Fault_OTP)
VCC
VCC(on)
VCC(off)
VFault
VFault(clamp)
VFault(OTP_OUT)
VFault(OTP_IN)
VFault(OTP)
NCP1937
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21
QR Flyback Valley Lockout
The NCP1937 integrates a quasi−resonant (QR) flyback
controller. The power switch turn−off of a QR converter is
determined b y the peak current set by the feedback loop. The
switch turn−on is determined by the transformer
demagnetization. The demagnetization is detected by
monitoring the transformer auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized or reset reduces switching losses. Once the
transformer is demagnetized, the drain voltage starts ringing
at a frequency determined by the transformer magnetizing
inductance and the drain lump capacitance eventually
settling at the input voltage. A QR controller takes
advantage of the drain voltage ringing and turns on the
power switch at the drain voltage minimum or “valley” to
reduce switching losses and electromagnetic interference
(EMI).
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. That
is, a load reduction increases the operating frequency. This
tradionally requires a maximum frequency clamp to limit
the operating frequency. This causes the controller to
become unstable and jump (or hesitate) between two valleys
generating audible noise. The NCP1937 incorporates a
patent pending valley lockout circuitry to eliminate valley
jumping. Once a valley is selected, the controller stays
locked in this valley until the output power changes
significantly. Like a traditional QR flyback controller, the
frequency increases when the load decreases. Once a higher
valley is selected the frequency decreases very rapidly. It
will continue to increase if the load is further reduced. This
technique extends QR operation over a wider output power
range while maintaining good efficiency and limiting the
maximum operating frequency. Figure 12 shows a
qualitative frequency vs output power relationship.
Figure 13 shows the internal arrangement of the valley
lockout circuitry. The decimal counter increases each time
a valley is detected. The operating valley (1st, 2nd, 3 rd or 4th)
is determined by the QFB voltage. As VQFB decreases or
increases, the valley comparators toggle one after another to
select the proper valley. The activation of an “n” valley
comparator blanks the “n−1” or “n+1” valley comparator
output depending if VQFB decreases or increases,
respectively.
A valley is detected once VQZCD falls below the QR
flyback demagnetization threshold, VQZCD(th), typically 55
mV. The controller will switch once the valley is detected or
increment the valley counter depending on QFB voltage.
Figure 12. Valley Lockout Frequency vs. Output Power Relationship
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Figure 13. Valley Lockout Detection Circuitry Internal Schematic
Figure 14 shows the operating valley versus VQFB. Once
a valley is asserted by the valley selection circuitry, the
controller is locked in this valley until VQFB decreases or
increases such that VQFB reaches the next valley threshold.
A decrease in output power causes the controller to switch
from “n” to “n+1” valley until reaching the 4th valley.
A further reduction of output power causes the controller
to enter the voltage control oscillator (VCO) mode once
VQFB falls below VHVCOD. In VCO mode the peak current
is set as shown in Figure 15. The operating frequency in
VCO mode is adjusted to deliver the required output power.
A hysteresis between valleys provides noise immunity
and helps stabilize the valley selection in case of small
perturbations on VQFB.
Valley
VQFB
VQILIM1*KQFB
VH2D
VHVCOI
VH3D
VH4D
VHVCOD VH4I VH3I VH2I
4th
3rd
2nd
1st
VCO
Figure 14. Selected Operating Valley vs. VQFB
NCP1937
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23
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Peak current
Setpoint
2nd
3rd
4th
VCO
Mode QR Mode
Skip
VQFB
VQILIM1
Ipeak(VCO)*VQILIM1
VH2D
VH3D
VH4D
VHVCOD
VQFB(TH)
Fault
VQILIM1*KQFB
1st Valley
VQSKIP
Figure 15. Operating Valley vs. VQFB
Figure 16 through Figure 19 show drain voltage, VQFB
and VQCT simulation waveforms for a reduction in output
power. The transitions between 2nd to 3rd, 3rd to 4th and 4th
valley to VCO mode are observed without any instabilities
or valley jumping.
Figure 16. Operating Mode Transitions between 2nd to 3rd, 3rd to 4th and 4th Valley to VCO Mode
−100
100
300
500
700
vdrain in volts
Plot1
1
400m
800m
1.20
1.60
2.00
feedback in volts
Plot2
2
3.64m 4.91m 6.18m 7.45m 8.72m
time in seconds
−1.00
1.00
3.00
5.00
7.00
vct in volts
Plot3
3
NCP1937
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Figure 17. Zoom 1: 2nd to 3rd Valley Transition
1vdrain 2feedback 3vct
−100
100
300
500
700
vdrain in volts
Plot1
1
1.75
1.85
1.95
2.05
2.15
feedback in volts
Plot2
2
3.70m 3.78m 3.86m 3.94m 4.02m
time in seconds
−2.00
0
2.00
4.00
6.00
vct in volts
Plot3
3
Figure 18. Zoom 2: 3rd to 4th Valley Transition
1vdrain 2feedback 3vct
−100
100
300
500
700
Plot1
vdrain in volts
1
1.22
1.26
1.30
1.34
1.38
Plot2
feedback in volts
2
5.90m 5.95m 6.00m 6.05m 6.11m
time in seconds
0
1.00
2.00
3.00
4.00
tilt
vc n vo s
3
Figure 19. Zoom 3: 4th Valley to VCO Mode Transition
1vdrain 2feedback 3vct
−100
100
300
500
700
vdrain in volts
Plot1
1
719m
819m
919m
1.02
1.12
feedback in volts
2
Plot2
7.10m 7.21m 7.32m 7.43m 7.55m
time in seconds
0
2.00
4.00
6.00
8.00
vct in volts
3
Plot3
NCP1937
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VCO Mode
The controller enters VCO mode once VQFB falls below
VHVCOD and remains in VCO until VQFB exceeds VHVCOI.
In VCO mode the peak current is set to VQILIM1*Ipeak(VCO)
and the operating frequency is linearly dependent on VQFB.
The product of VQILIM1*Ipeak(VCO) is typically 12.5%. A
minimum frequency clamp, fVCO(MIN), typically 27 kHz,
prevents operation in the audible range. Further reduction in
output power causes the controller to enter skip operation.
The minimum frequency clamp is only enabled when
operating in VCO mode.
The VCO mode operating frequency is set by the timing
capacitor connected between the QCT and GND pins. This
capacitor is charged with a constant current source, IQCT,
typically 20 mA.
The capacitor voltage, VQCT, is compared to an internal
voltage level, Vf(QFB), inversely proportional to VQFB The
relationship between and Vf(QFB) and VQFB is given by
Equation 6.
Vf(QFB) +5*2@VQFB (eq. 6)
A drive pulse is generated once VQCT exceeds Vf(QFB)
followed by the immediate dischar ge of the timing capacitor.
The timing capacitor is also discharged once the minimum
frequency clamp is reached.
Figure 20 shows simulation waveforms of Vf(QFB),
VQDRV and output current while operating in VCO mode.
0
200m
400m
600m
800m
1
−1.00
1.00
3.00
5.00
7.00 2
3
7.57m 7.78m 7.99m 8.20m 8.40m
time in seconds
−10.0
0
10.0
20.0
30.0
5
VQDRV
Vf(QFB)
IOUT
Figure 20. VCO Mode Operating Waveforms
VQCT
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Flyback Timeout
In case of extremely damped oscillations, the QZCD
comparator may be unable to detect the valleys. In this
condition, drive pulses will stop waiting for the next valley
or ZCD event. The NCP1937 ensures continued operation
by incorporating a maximum timeout period after the last
demagnetization detection. The timeout signal is a substitute
for the ZCD signal for the valley counter. Figure 21 shows
the timeout period generator circuit schematic. The steady
state timeout period, tQ(tout2), is set at 6 ms to limit the
frequency step.
During startup, the voltage of fset added by the overpower
compensation diode, DOPP, prevents the QZCD Comparator
from accurately detecting the valleys. In this condition, the
steady state timeout period will be shorter than the inductor
demagnetization period causing continuous current mode
(CCM) operation. CCM operation lasts for a few cycles until
the voltage on the QZCD pin is high enough to detect the
valleys. A longer timeout period, tQ(tout1), (typically 100 ms)
is set during soft−start to limit CCM operation. Figure 22
and Figure 23 show the timeout period generator related
waveforms.
Figure 21. Timeout Period Generator Circuit Schematic
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4
3
14
12
15
16
17
The 3rd valley is
validated
The 3rd valley is not detected
by the QZCD Comparator
Timeout adds a pulse to account for
the missing 3rd valley
The 2nd valley is detected
by the QZCD Comparator
Figure 22. Timeout Operation with a Missing 3rd Valley
VQZCD(th)
VQZCD
2nd, 3rd
QZCD
Comparator
Output
Timeout
Clk
high
low
high
low
high
low
high
low
4
3
14
18
15
16
17
Timeout adds 2 pulses to account
for the missing 3rd and 4th valleys
The 4th valley is
validated
Figure 23. Timeout Operation with Missing 3rd and 4th Valleys
VQZCD(th)
VQZCD
3rd, 4th
QZCD
Comparator
Output
Timeout
Clk
high
low
high
low
high
low
high
low
NCP1937
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QR Flyback Current Sense and Overload
The power switch on time is modulated by comparing a
ramp proportional to the switch current to VQFB/KQFB using
the PWM Comparator. The switch current is sensed across
a current sense resistor, R SENSE, and the resulting voltage is
applied to the QCS pin. The current signal is blanked by a
leading edge blanking (LEB) circuit. The blanking period
eliminates the leading edge spike and high frequency noise
during the switch turn−on event. The LEB period,
tQCS(LEB1), is typically 275 ns. The drive pulse terminates
once the current sense signal exceeds VQFB/KQFB.
The Maximum Peak Current Comparator compares the
current sense signal to a reference voltage to limit the
maximum peak current of the system. The maximum peak
current reference voltage, VQILIM1, is typically 0.8 V. The
maximum peak current setpoint is reduced by the overpower
compensation circuitry. An overload condition causes the
output of the Maximum Peak Current Comparator to
transition high and enable the overload timer. Figure 24
shows the implementation of the current sensing circuitry.
Figure 24. Current Sensing Circuitry Schematic
PWM
Comparator
Peak Current
Comparator LEB
Fault
Over Current
Comparator
QFB
QCS
LEB
CSStop
QDRV
Counter
Reset
Count
Disable QDRV
Count Up
Count Down
Overload T imer
+
−
+
−
+
−
+
+VDD
VQILIM2
VQZCD
VQILIM1
IQCS
VQZCD
VDD
tQCS(LEB1)
tQCS(LEB2)
Skip
/KQFB
VQSKIP
VQFB
IQFB
RQFB
In_PSM
Ipeak(VCO) =
KQCS(VCO)
tQOVLD
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, tQOVLD, is typically 80 ms. If both
the PWM and Maximum Peak Current Comparators toggle
at the same time, the PWM Comparator takes precedence
and the overload timer counts down. The controller can latch
(options C and D) or allow for auto−recovery (options A and
B) once the overload timer expires. Auto−recovery requires
a VCC triple hiccup before the controller restarts. Figure 25
and Figure 26 show operating waveforms for latched and
auto−recovery overload conditions.
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30
A severe overload fault like a secondary side winding
short−circuit causes the switch current to increase very
rapidly during the on−time. The current sense signal
significantly exceeds VQILIM1. But, because the current sense
signal is blanked by the LEB circuit during the switch turn
on, the system current can get extremely high causing
system damage.
The NCP1937 protects against this fault by adding an
additional comparator, Fault Overcurrent Comparator. The
current sense signal is blanked with a shorter LEB duration,
tQCS(LEB2), typically 120 ns, before applying it to the Fault
Overcurrent Comparator. The voltage threshold of the
comparator, VQILIM2, typically 1.2 V, is set 50% higher than
VQILIM1, to avoid interference with normal operation. Four
consecutive faults detected by the Fault Overcurrent
Comparator causes the controller to enter latch mode. The
count to 4 provides noise immunity during surge testing. The
counter is reset each time a QDRV pulse occurs without
activating the Fault Overcurrent Comparator. A 1 mA
(typically) pull−up current source, IQCS, pulls up the QCS
pin to disable the controller if the pin is left open.
QR Flyback Soft−Start
Soft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to current sense signal. VSSTART
ramps up from 0 V once the controller powers up. The
soft−start duration, tSSTART, is typically 4 ms.
During soft−start the timeout duration is extended and the
lower latch or OTP Comparator signal (typically for
overtemperature) is blanked. Soft−start ends once VSSTART
exceeds the peak current sense signal threshold.
QR Flyback Overpower Compensation
The input voltage of the QR flyback stage varies with the
line voltage and operating mode of the PFC converter. At
low line the PFC bulk voltage is 250 V and at high line it is
400 V. In addition, the PFC can be disabled at light loads to
reduce input power at which point the PFC bulk voltage is
set by the rectified peak line voltage.
An integrated overpower circuit provides a relative
constant output power across PFC bulk voltage, Vbulk. It
also reduces the variation on VQFB during the PFC stage
enable or disable transitions. Figure 27 shows the circuit
schematic for the overpower detector.
The auxiliary winding voltage during the power switch on
time is a reflection of the input voltage scaled by the primary
to auxiliary winding turns ratio, NP,AUX, as shown in
Figure 28.
Figure 27. Overpower Compensation Circuit Schematic
QZCD
QZCD Comparator
+
QCS LEB
Other Faults
Disable
QDRV
PWM
Comparator
QFB
Peak Current
Comparator
+
−
+
−
/4
++
−
VQZCD(th)
VQILIM1
KQCS(VCO)
tQCS(LEB1)
DOPP
LAUX
RQCZD
ROPPU
ROPPL
Figure 28. Auxiliary Winding Voltage Waveform
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Overpower compensation is achieved by scaling down the
on−time reflected voltage and applying it to the QZCD pin.
The voltage is scaled down using ROPPU and ROPPL. The
negative voltage applied to the pin is referred to as VOPP.
The internal current setpoint is the sum of VOPP and peak
current sense threshold, VQILIM1. VOPP is also subtracted
from VQFB to compensate for the PWM Comparator delay
and improve the PFC on/off accuracy.
The current setpoint is calculated using Equation 7. For
example, a VOPP of −0.15 V results in a current setpoint of
0.65 V.
Current setpoint +VQILIM1 )VOPP (eq. 7)
To ensure optimal zero−crossing detection, a diode is
needed to bypass ROPPU during the off−time. Equation 8 is
used to calculate ROPPU and ROPPL.
RQZCD )ROPPU
ROPPL +*NP,AUX @Vbulk *VOPP
VOPP (eq. 8)
ROPPU is selected once a value is chosen for ROPPL.
ROPPL is selected large enough such that enough voltage is
available for the zero crossing detection during the off−time.
It is recommended to have at least 8 V applied on the QZCD
pin for good detection. The maximum voltage is internally
clamped t o V CC. The o ff−time voltage on the QZCD is given
by Equation 9.
VQZCD +ROPPL
RQZCD )ROPPL @ǒVAUX *VFǓ(eq. 9)
Where VAUX is the voltage across the auxiliary winding a nd
VF is the DOPP forward voltage drop.
The ratio between RQZCD and ROPPL is given by
Equation 10. It is obtained combining Equations 8 and 9.
RQZCD
ROPPL +VAUX *VF*VQZCD
VQZD (eq. 10)
A design example is shown below:
System Parameters:
VAUX = 18 V
VF = 0.6 V
NP,AUX = 0.18
The ratio between RQZCD and ROPPL is calculated using
Equation 10 for a minimum VQZCD of 8 V.
RQZCD
ROPPL +18 *0.6 *8
8[1.2
RQZCD is arbitrarily set to 1 kW. ROPPL is also set to 1 kW
because the ratio between the resistors is close to 1.
The NCP1937 maximum overpower compensation or
peak current setpoint reduction is 31.25% for a VOPP of
−250 mV. We will use this value for the following example:
Substituting values in Equation 8 and solving for ROPPU
we obtain,
RQZCD )ROPPU
ROPPL +*0.18 @370 *(−0.25)
(−0.25) +271
ROPPU +271 @ROPPL *RQZCD
ROPPU +271 @1k*1k+270 k
Power Factor Correction
The PFC stage operates in critical conduction mode
(CrM). In CrM, the PFC inductor current, IL(t) reaches zero
at the end of each switch cycle. Figure 29 shows the PFC
inductor current while operating in CrM. The average input
current, Iin(t), is in phase with the ac line voltage, Vin(t), to
achieve power factor correction.
Figure 29. Inductor Current in CrM
High power factor is achieved in CrM by maintaining a
constant on time (ton) for a given RMS input voltage
(Vac(RMS)) and load condition. Equation 11 shows the
relationship between on t ime and system o perating conditions.
ton +2@Pout @L
h@Vac(RMS)2(eq. 11)
where Pout is the output power, L is the PFC choke
inductance and η is the system efficiency.
PFC Feedback
The PFC feedback circuitry is shown in Figure 30. A
transconductance error amplifier regulates the PFC output
voltage, V bulk, by comparing the PFC feedback signal to an
internal reference voltage, VPREF. The feedback signal is
applied to the inverting input and the reference is connected
to the non−inverting input of the error amplifier. A resistor
divider consisting of R1 and R2 scales down Vbulk to
generate the PFC feedback signal. VPREF is trimmed during
manufacturing to achieve an accuracy of ± 2%.
The P FC stage i s disabled at l ight loads to r educe input power .
The NCP1937 integrates a 700 V switch, PFC FB Switch,
between the PFBHV and PFBLV pins. The PFC FB Switch
is in series between R1 and R2 to disconnect the resistors and
reduce input power when the PFC stage is disabled.
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Figure 30. PFC Regulation Circuit Schematic
Error
Amplifier
+
−
PFBHV
Stop
Latchoff
PILIM1, PILIM2
PFCDRV
S
RQ
Dominant
Reset
Latch
Enable PFC
Delay
PFBLV
PFC Faults
and
Disable Signals
R1
R2
PFC FB
Switch
PFC UVP
Comparator
High
Clamp
Low
Clamp
PUVP
Disable PFC
PUVP
PControl
+
−
Vbulk
VDD
VPREF
VPFB(disable)
Q
tPenable
The maximum on resistance of the PFC FB Switch,
RPFBswitch(on), is 10 kW. Because the PFC FB Switch is in
series with R1 and R1’s value is several orders of
magnitudes la rger, the switch introduces minimum error o n
the regulation level. The off state leakage current of the PFC
FB Switch, IPFBSwitch(off), is less than 3 mA.
The NCP1937 safely disables the controller if the PFBLV
pin is grounded. A short pin detector disables the controller
if VPFBLV is below the disable threshold, VPFB(disable),
typically 0.3 V. If the PFBLV pin is open, the PFC FB Switch
will raise VPFBLV above the overvoltage threshold and
disable the controller. Equation 12 shows the relationship
between the PFC output voltage, the PFC reference
threshold, R1 and R2.
VPFC +VPREF(xL) @R1 )R2
R2 (eq. 12)
PFC Error Amplifier
A transconductance amplifier has a voltage−to−current
gain, g m. That is, the amplifier’s output current is controlled
by the differential input voltage. The NCP1937 amplifier
has a typical gm of 200 mS. The PControl pin provides access
to the amplifier output for compensation. The compensation
network is ground referenced allowing the PFC feedback
signal to be used to detect an overvoltage condition.
The compensation network on the PControl pin is selected
to filter the bulk voltage ripple such that a constant control
voltage is maintained across the ac line cycle. A capacitor
between the PControl pin and ground sets a pole. A pole at
or below 20 Hz is enough to filter the ripple voltage for a 50
and 60 Hz system. The low frequency pole, fp, of the system
is calculated using Equation 13.
fp+gm
2pCPControl (eq. 13)
where, CPControl is the capacitor on the PControl pin to
ground.
The output of the error amplifier is held low when the PFC
is disabled by means of an internal pull−down transistor. The
pull down transistor is disabled once the PFC stage is
enabled. An internal voltage clamp is then enabled to
quickly raise VPControl to its minimum voltage,
VPClamp(lower).
PFC On−Time
The PFC on time is controlled by VPControl. The PFC
On−T ime Comparator terminates the drive pulse once the
PFC on−time ramp voltage plus offset exceeds VPControl.
The ramp is generated by charging an internal timing
capacitor, CPCT, with a constant current source, IPCT. The
capacitor ramp is level shifted to achieve 0 duty ratio (stop
drive pulses) at the minimum VPControl. VPControl is
proportional to the output power and it is fixed for a given
RMS line voltage and output load, satisfying Equation 11.
Lower and upper voltage clamps limit the excursion of
VPControl. The maximum on−time, ton(MAX), occurs when
VPControl is at its maximum value, VPControl(MAX). The PFC
drive pulses are inhibited once VPControl is below its
minimum value, VPControl(MIN). The maximum PFC
on−time in the NCP1937 is set internally. The maximum on
time at low line is typically 15 ms.
NCP1937
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33
PFC Transient Response
The PFC bandwidth is set low enough to achieve good
power factor. A low bandwidth system is slow and fast load
transients can result in large output voltage excursions. The
NCP1937 incorporates dedicated circuitry to help mantain
regulation of the output voltage independent of load
transients.
An undervoltage detector monitors Vbulk and prevents it
from dropping below from its regulation level. Once the
ratio between VPFBLV and V PREF(xL) exceeds KLOW(PFCxL),
typically 5.5%, a pull−up current source on the PControl pin,
IPControl(boost), is enabled to speed up the charge of the
compensation capacitor(s). This results in an increased
on−time and thus output power. IPControl(boost) is typically
240 mA. The boost current source is disabled once the ratio
between V PFBLV and VPREF(xL) drops below KLOW(PFCxL),
typically 4%.
The boost current source becomes active as soon as the
PFC is enabled. Coupled with the lower control clamp, the
current provided by the boost current source assists in
rapidly bringing VPControl to its set point to allow the bulk
voltage to quickly reach regulation. Achieving regulation is
detected by monitoring the error amplifier output current.
The error amplifier output current drops to zero once the
PFC output voltage reaches the target regulation level.
The maximum PFC output voltage is limited by the
overvoltage protection circuitry. The NCP1937
incorporates both soft and hard overvoltage protection. The
hard overvoltage protection function immediately
terminates and prevents further PFC drive pulses when
VPFBLV exceeds the hard−OVP level, VPREF(xL) *
KPOVP(xL). Soft−OVP reduces the on−time proportional to
the delta between VPFBLV and the hard−OVP level.
Soft−OVP is enabled once the delta, DPOVP(xL), between
VPFBLV and the hard−OVP level, is between 20 and 55 mV.
Figure 31 shows the circuit schematic of the boost and
Soft−OVP circuits.
Figure 31. Boost and Soft−OVP Circuit Schematics
During power up, VPControl exceeds the regulation level
due to the system’s inherently low bandwidth. This causes
the bulk voltage to rapidly increase and exceed its
regulation. The on time starts to decrease when soft−OVP i s
activated. Once the bulk voltage decreases to its regulation
level the PFC on time is no longer controlled by the
soft−OVP circuitry.
PFC Current Sense and Zero Current Detection
The NCP1937 uses a novel architecture combining the
PFC current sense and zero current detectors (ZCD) in a
single input terminal. Figure 32 shows the circuit schematic
of the current sense and ZCD detectors.
NCP1937
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34
Figure 32. PFC Current Sense and ZCD Detectors Schematic
To PDRV Set
Frequency
Clamp
Timer
CLK
DQ
ZCD
Comparator
PDRV Reset
+
−PFC T imeout
Reset
PDRV
PCS/PZCD
PFC Inductor
PFC Switch
PDRV
LEB1 Current Limit
Comparator
Short Circuit
Detector
LEB2
Latchoff
Boost Diode
Counter
Count
Reset
PILIM2
R
SQ
Dominant
Reset
Latch
Other Latching Faults
PFC Boost
Diode
+
−
ZCD_LAT
PILIM1
PDRV
PDRV
CLK
DQ
R
VDD
PDRVRST
PILIM2
RPZCD
RPCS
RPsense
VZCD
Q
Q
tPCS(LEB2)
tPCS(LEB1)
VPILIM2
VPILIM1
Q
tPFC(out)
tPFC(off) Timer
PFC Current Sense
The PFC Switch current is sensed across a sense resistor,
RPsense, and the resulting voltage ramp is applied to the
PCS/PZCD pin. The current signal is blanked by a leading
edge blanking (LEB) circuit. The blanking period eliminates
the leading edge spike and high frequency noise during the
switch turn−on event. The LEB period, tPCS(LEB1), is
typically 325 ns. The Current Limit Comparator disables the
PFC driver once the current sense signal exceeds the PFC
current sense reference, VPILIM1, typically 0.5 V.
A severe overload fault like a PFC boost diode short
circuit causes the switch current to increase very rapidly
during the on−time. The current sense signal significantly
exceeds VPILIM1. But, because the current sense signal is
blanked by the LEB circuit during the switch turn on, the
system current can get extremely high causing system
damage.
The NCP1937 protects against this fault by adding an
additional comparator, PFC Short Circuit Comparator. The
current sense signal is blanked with a shorter LEB duration,
tPCS(LEB2), typically 175 ns, before applying it to the PFC
Short Circuit Comparator. The voltage threshold of the
comparator, VPILIM2, typically 1.25 V, is set 250% higher
than VPILIM1, to avoid interference with normal operation.
Four consecutive faults detected by the Short Circuit
Comparator causes the controller to enter latch mode. The
count to 4 provides noise immunity during surge testing. The
counter is reset each time a PDRV pulse occurs without
activating the Short Circuit Comparator.
The PFC watchdog timer duration increases to tPFC(off2)
(typically 1 ms) when a VPILIM2 fault is detected
independent of the PFC ZCD state.
PFC Zero Current Detection
The off−time in a CrM PFC topology varies with the
instantaneous line voltage and is adjusted every switching
cycle to allow the inductor current to reach zero before the
next switching cycle begins. The inductor is demagnetized
once its current reaches zero. Once the inductor is
demagnetized the drain voltage of the PFC switch begins to
drop. The inductor demagnetization is detected by sensing
the voltage across the inductor using an auxiliary winding.
This winding is commonly known as a zero crossing
detector (ZCD) winding. This winding provides a scaled
version of the inductor voltage. Figure 33 shows the ZCD
winding arrangement.
NCP1937
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35
Figure 33. ZCD Winding Implementation
The ZCD voltage, VZCD, is positive while the PFC Switch
is off and current flows through the PFC inductor. VZCD
drops to and rings around zero volts once the inductor is
demagnetized. The next switching cycle begins once a
negative transition is detected on the PCS/PZCD pin. A
positive transition (corresponding to the PFC switch turn
off) arms the ZCD detector to prevent false triggering. The
arming of the ZCD detector, VPZCD(rising), is typically
0.75 V (VPCS/PZCD increasing). The trigger threshold,
VPZCD(falling), is typically 0.25 V (VPCS/PZCD decreasing).
The PCS/PZCD pin is internally clamped to 5 V with a
Zener diode and a 2 kW resistor. A resistor in series with the
PCS/PZCD pin is required to limit the current into pin. The
Zener diode also prevents the voltage from going below
ground. Figure 34 shows typical ZCD waveforms.
During startup there are no ZCD transitions to set the PFC
PWM Latch and generate a PDRV pulse. A watchdog timer,
tPFC(off1), starts the drive pulses in the absence of ZCD
transitions. Its duration is typically 200 ms. The timer is also
useful i f the line voltage transitions from low line to high line
and while operating at light load because the amplitude of
the ZCD signal may be too small to cross the ZCD arming
threshold. The watchdog timer is reset at the beginning of a
PFC drive pulse. It is disabled during a PFC hard
overvoltage and feedback input short circuit condition.
Figure 34. ZCD Winding Waveforms
The watchdog timer duration increases to tPFC(off2),
typically 1 ms, when a VPILIM2 fault is detected.
PFC Frequency Clamp
The PFC operating frequency naturally increases when
the line voltage gets near to zero due to the reduced
demagnetization time or when the PFC is operating at light
loads. A maximum frequency clamp, fclamp(PFC), limits the
PFC frequency to improve efficiency and facilitate
compliance with EMI requirements. The NCP1937 has
options for PFC frequency clamp values of 131 kHz or
250 kHz.
The PDRV pulse is blanked until the frequency clamp
timer expires. Once expired, the controller waits for the next
ZCD transition to initiate PDRV. This ensures valley
switching to reduce switching losses. A timeout timer,
tP(tout), starts the next PDRV pulse in the absence of a ZCD
transition. The timeout timer duration is typically 10 ms. The
timer is reset at every ZCD event. Figure 35 shows the block
diagram of the PFC frequency clamp.
Figure 35. PFC Frequency Clamp Schematic
To PDRV Set
Frequency
Clamp
Timer
CLK
DQ
ZCD
Comparator
PDRV Reset
+
−PFC T imeout
Reset
PDRV
PCS/PZCD
PFC Inductor
PFC Switch
PDRV
PFC Boost
Diode
ZCD_LAT
CLK
DQ
R
VDD
PILIM2
RPZCD
RPCS
RPsense
VZCD
Q
Q
tPFC(out)
tPFC(off) Timer
NCP1937
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36
PFC Enable & Disable
In some applications it is desired to disable the PFC at
lighter loads to increase the overall system efficiency. The
NCP1937 integrates a novel architecture that allows the user
to p rogram t he P FC d isable t hreshold b ased o n t he p ercentage
of QR output power. The PFC enable circuitry is inactive
until the QR flyback soft start period has ended. A voltage
to current (V−I) converter generates a current proportional
to VQFB. This current is pulse width modulated by the
demagnetization time of the flyback controller to generate
a current, IPONOFF, proportional to the output power. An
external resistor , RPONOFF, between the PONOFF and GND
pins generate a voltage proportional to the output power.
This resistor is used to scale the output power signal. A
capacitor , C PONOFF, in parallel with RPONOFF is required t o
average the signal on this pin. A good compromise between
voltage ripple and speed is achieved by setting the time
constant of CPONOFF and RPONOFF to 160Ăms.
The PONOFF pin voltage, VPONOFF, is compared to an
internal reference, VPOFF (typically 2 V) to disable the PFC
stage. The PFC disable point is typically set between 25 and
50% or between 50 and 75% of the maximum system load.
These setpoints provide the best system efficiency across
low line and high line.
Once VPONOFF decreases below VPOFF, the PFC disable
timer, tPdisable, is enabled. The NCP1937 has options for
500 ms, 4 s, or 13 s PFC disable timer. The PFC stage is
disabled once the timer expires. The PFC stage is enabled
once VPONOFF exceeds VPOFF by VPONHYS for a period
longer than the PFC enable filter, t Penable(filter), typically 100
ms. A shorter delay for the PFC enable threshold is used to
reduce the bulk capacitor requirements during a step load
response. Figure 36 shows the block diagram of the PFC
disable circuit.
Figure 36. PFC On/Off Control Circuitry
Disable PFC
PONOFF
Reset
PFC Disable
Timer
QFB
Demag
Time
Calculator
PFC Enable
Timer
Dominant
Reset
Latch
S
R
Q
QDRV Enable
PONOFF
Comparator
Soft−Start Complete
QZCD
−
+
+
−
Hysteresis Control
VPOFF
CPONOFF
RCPONOFF
IPONOFF
V to I
Converter
Release
PControl
Turn on
PFC FB Switch
QtPenable
tPdisable
tPenable(filter)
Filter Delay
PFC Skip
The PFC stage incorporates skip cycle operation at light
loads t o reduce input power. Skip operation disables the PFC
stage if the PControl voltage decreases below the skip
threshold. The skip threshold voltage is typically 25 mV
(DVPSKIP) above the PControl lower voltage clamp,
Vclamp(lower). The PFC stage is enabled once VPControl
increases above the skip threshold by the skip hysteresis,
VPSKIP(HYS). PFC skip is disabled during any initial PFC
startup and when the PFC is in a UVP. Skip operation will
become active after the PFC has reached regulation.
PFC and Flyback Drivers
The NCP1937 maximum supply voltage, VCC(MAX), is
30 V. Typical high voltage MOSFETs have a maximum gate
voltage rating of 20 V. Both the PFC and flyback drivers
incorporate an active voltage clamp to limit the gate voltage
on the external MOSFETs. The PFC and flyback voltage
clamps, VPDRV(high) and VQDRV(high), are typically 12 V
with a maximum limit of 14 V.
Auto Recovery
The controller is disabled and enters “triple−hiccup”
mode if V CC drops below VCC(off). The controller will also
enter “triple−hiccup” mode if an overload fault is detected
on the non−latching version. A hiccup consists of VCC
falling down to VCC(off) and charging up to VCC(on). The
controller needs to complete 3 hiccups before restarting.
Temperature Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
threshold, TSHDN, typically 150_C. A continuous VCC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next VCC(on) once the IC
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 40_C.
The thermal shutdown fault is also cleared if VCC drops
below VCC(reset), a brown−out fault is detected or if the line
voltage is removed. A new power up sequences commences
at the next VCC(on) once all the faults are removed.
NCP1937
www.onsemi.com
37
PACKAGE DIMENSIONS
ÇÇÇÇ
ÇÇÇÇ
SOIC20 NB LESS PINS 2, 4 & 19
CASE 751BS
ISSUE O
6.30
17X
0.53
17X
0.85
1.00
DIMENSIONS: MILLIMETERS
1
PITCH
20
10
11
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.10 TOTAL IN EXCESS
OF THE b DIMENSION. DIMENSION b APPLIES TO THE FLAT
PORTION OF THE LEAD AND SHALL BE MEASURED BETWEEN
0.13 AND 0.25 FROM THE TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS BUT DO INCLUDE MOLD
MISMATCH. MOLD FLASH, PROTRUSIONS, OR GATE BURRS
SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND
E1 ARE DETERMINED AT DATUM H.
5. DATUMS A AND B ARE TO BE DETERMINED AT DATUM H.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEAT
ING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
7. CHAMFER FEATURE IS OPTIONAL. IF NOT PRESENT, THEN A
PIN ONE IDENTIFIER MUST BE LOCATED IN THIS AREA.
110
20 11
SEATING
PLANE
L
h
NOTE 7
A1
A
DIM MIN MAX
MILLIMETERS
A--- 1.70
b0.31 0.51
L0.40 0.85
D9.90 BSC
c0.10 0.25
A1 0.00 0.20
M0 8
h0.25 0.50
__
b17X
A
B
C
E6.00 BSC
E1 3.90 BSC
e1.00 BSC
L2 0.25 BSC
EE1
DD
A-B
M
0.25 DC
0.20 C
RECOMMENDED
NOTE 4
NOTE 4
NOTE 5
NOTE 5
e
0.10 C A-B
0.10 C A-B
NOTE 3
0.10 C
0.10 C
M
c
h
DET AIL A
H
SEATING
PLANE
C
L2
DETAIL A
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