© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 11
1Publication Order Number:
MC10EL34/D
MC10EL34, MC100EL34
5V ECL P2, P4, P8 Clock
Generation Chip
Description
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip−flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
The 100 Series contains temperature compensation.
Features
•50 ps Output-to-Output Skew
•Synchronous Enable/Disable
•Master Reset for Synchronization
•PECL Mode Operating Range:
♦VCC = 4.2 V to 5.7 V with VEE = 0 V
•NECL Mode Operating Range:
♦VCC = 0 V with VEE = −4.2 V to −5.7 V
•Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR
•These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC−16
D SUFFIX
CASE 751B−05
1
16
MARKING DIAGRAMS*
1
16
10EL34G
AWLYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
1
16
100EL34G
AWLYWW
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*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device Package Shipping
MC10EL34DG SOIC−16
Pb-Free)
48 Units/Tube
MC100EL34DG SOIC−16
(Pb-Free)
48 Units/Tube
MC10EL34, MC100EL34
www.onsemi.com
2
VCC
Figure 1. Logic Diagram and Pinout Assignment
Q0 Q1 VCC Q2
1516 14 13 12 11 10
2
134567
VCC
9
8
Q2
Q0
EN NC CLK CLK VBB MR VEE
D
QR
QR
÷2QR
÷4QR
÷8
Q1
*All VCC pins are tied together on the die.
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Table 1. FUNCTION TABLE
CLK* EN*MR*Function
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0−3
Reset Q0−3
*Pins will default low when left open.
Z = Low-to-High Transition
ZZ = High-to-Low Transition
Table 2. PIN DESCRIPTION
Pin Function
CLK, CLK ECL Diff Clock Inputs
EN ECL Sync Enable
MR ECL Master Reset
Q0, Q0 ECL Diff ÷2 Outputs
Q1, Q1 ECL Diff ÷4 Outputs
Q2, Q2 ECL Diff ÷8 Outputs
VBB Reference Voltage Output
VCC Positive Supply
VEE Negative Supply
NC No Connect
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 KW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charge Device Model
> 1 KV
> 100 V
> 2 KV
Moisture Sensitivity (Note 1) Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count 191 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
MC10EL34, MC100EL34
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3
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 8 V
VEE NECL Mode Power Supply VCC = 0 V −8 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
6
−6
V
Iout Output Current Continuous
Surge
50
100
mA
IBB VBB Sink/Source ± 0.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−16 130
75
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−16 33 to 36 °C/W
Tsol Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 5. 10EL SERIES PECL DC CHARACTERISTICS (VCC = 5.0 V; VEE = 0 V (Note 1))
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 39 39 39 mA
VOH Output HIGH Voltage (Note 2) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV
VOL Output LOW Voltage (Note 2) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV
VIH Input HIGH Voltage (Single-Ended) 3770 4110 3870 4190 3940 4280 mV
VIL Input LOW Voltage (Single-Ended) 3050 3500 3050 3520 3050 3555 mV
VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.81 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
3.0 4.6 3.0 4.6 3.0 4.6 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.3 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
MC10EL34, MC100EL34
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4
Table 6. 10EL SERIES NECL DC CHARACTERISTICS (VCC = 0 V; VEE = −5.0 V (Note 1))
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 39 39 39 mA
VOH Output HIGH Voltage (Note 2) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV
VOL Output LOW Voltage (Note 2) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV
VIH Input HIGH Voltage (Single-Ended) −1230 −890 −1130 −810 −1060 −720 mV
VIL Input LOW Voltage (Single-Ended) −1950 −1500 −1950 −1480 −1950 −1445 mV
VBB Output Voltage Reference −1.43 −1.30 −1.35 −1.25 −1.31 −1.19 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
−2.0 −0.4 −2.0 −0.4 −2.0 −0.4 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.3 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / −0.5 V.
2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 7. 100EL SERIES PECL DC CHARACTERISTICS (VCC = 5.0 V; VEE = 0 V (Note 1))
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 39 39 42 mA
VOH Output HIGH Voltage (Note 2) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV
VOL Output LOW Voltage (Note 2) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV
VIH Input HIGH Voltage (Single-Ended) 3835 4120 3835 4120 3835 4120 mV
VIL Input LOW Voltage (Single-Ended) 3190 3525 3190 3525 3190 3525 mV
VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
2.2 4.6 2.2 4.6 2.2 4.6 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
MC10EL34, MC100EL34
www.onsemi.com
5
Table 8. 100EL SERIES NECL DC CHARACTERISTICS (VCC = 0 V; VEE = −5.0 V (Note 1))
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 39 39 42 mA
VOH Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
VOL Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV
VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
−2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 9. AC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 1))
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Toggle Frequency 1.1 1.1 1.1 GHz
tPLH
tPHL
Propagation
CLK to Q0
Delay to
CLK to Q1,2
Output
MR to Q
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
970
910
790
1210
1150
1090
ps
tSKEW Within-Device Skew (Note 2) 100 100 100 ps
tJITTER Cycle-to-Cycle Jitter 1.0 1.0 1.0 ps
tSSetup Time EN 400 400 400 ps
tHHold Time EN 250 250 250 ps
tRR Set/Reset Recovery 400 200 400 200 400 200 ps
VPP Input Swing (Note 3) 150 1000 150 1000 150 1000 mV
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
225 475 225 475 225 475 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary +0.06 V / −0.5 V.
100 Series: VEE can vary +0.8 V / −0.5 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. VPPmin is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
MC10EL34, MC100EL34
www.onsemi.com
6
There are two distinct functional relationships between the Master Reset and Clock:
CASE 1: If the MR is De-asserted (H−L), While the Clock is Still High, the
Outputs will Follow the First Ensuing Clock Rising Edge.
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal
divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
CASE 2: If the MR is De−asserted (H−L), After the Clock has Transitioned Low, the
Outputs will Follow the Second Ensuing Clock Rising Edge.
CASE 1 CASE 2
Figure 2. Timing Diagrams
CLOCK
OUTPUT
MR
TRR
CLOCK
OUTPUT
MR
TRR
Figure 3. Reset Recovery Time
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR
MC10EL34, MC100EL34
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7
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
Resource Reference of Application Notes
AN1405/D −ECL Clock Distribution Techniques
AN1406/D −Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D −Metastability and the ECLinPS Family
AN1568/D −Interfacing Between LVDS and ECL
AN1672/D −The ECL Translator Guide
AND8001/D −Odd Number Counters Design
AND8002/D −Marking and Date Codes
AND8020/D −Termination of ECL Logic Devices
AND8066/D −Interfacing with ECLinPS
AND8090/D −AC Characteristics of ECL Devices
MC10EL34, MC100EL34
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8
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
15. EMITTER
16. COLLECTOR
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
16. CATHODE
STYLE 3:
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
15. EMITTER, #4
16. COLLECTOR, #4
STYLE 4:
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
STYLE 5:
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
STYLE 7:
PIN 1. SOURCE N‐CH
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
9. SOURCE P‐CH
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
16
89
8X
*For additional information on our Pb-Free
strategy and soldering details, please
download the ON Semiconductor Soldering
and Mounting Techniques Reference Man-
ual, SOLDERRM/D.
MC10EL34, MC100EL34
www.onsemi.com
9
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