Hybrid Systems HS 1010 CMOS 16 x 16 Multiplier/Accumulator DESCRIPTION The HS 1010 is a 16 x 16 parallel multiplier-accumulator (MAC). Fabricated using advance Molybdenum CMOS VLSI technology, the HS 1010 is pin-for-pin functional replacement for TRWs TDC 1010, TMC2010, WTL1010, and AMD29510. The input data may be specified as two's compiement or unsigned magnitude, yielding a full precision 32-Bit product. Products may be accumulated to a 35-Bit result. FEATURES individually clocked input and output registers are pro- vided to maximize system throughput and simplify bus interfacing. These registers are positive-edge-triggered D-type flip-flops. The result is divided into a 3-Bit eXTended Product (XTP), and a 16-Bit Most Significant Product (MSP). Individual three-state output ports are provided for the XTP and the MSP, the LSP is multi- plexed with the Y input. The output register can be pre- loaded directly via the output ports. BENEFITS 1. High Speed: 75 nsec Typ, 100 nsec Max 2. Low Power Consumption: 125 mW Typ, 200 mW Max 3. Three-State Output 4. Pin and Function Compatible with TRW TDC 1010, TMC2010, WTL1010 and AMD295010 1. Suitable as Central Building Block for Digital Signal Processing Applications Including Digital Filtering and FFTs. 2. Reduces System Level Power Requirements 3. Allows Direct Interface to 4 P Bus Structures Without the Need for External Latches 4, Superior Low Power Replacement FUNCTIONAL DIAGRAM x 16 x REGISTER 16 35 XTP cLKP REGISTER PREL SC REGISTER. 16 x 16 MULTIPLIER ARRAY MSP REGISTER Y/LSP 16 RAND Yv REGISTER 16 32 ADDER 35 HS 1010 LSP REGISTER LATCH LATCH MUX MUX 35FUNCTIONAL DESCRIPTION GENERAL INFORMATION The HS 1010 consists of four functional sections: input registers, an asynchronous multiplier, an adder, and output registers. The input registers store the two 16-Bit numbers which are to be multiplied, and the control lines which control the input numerical format (2s complement or unsigned magnitude), output rounding, accumulation, and subtraction. The round control is used when a single-word output is desired. Each number is independently stored, simplifying multiplica- tion by a constant. The output registers can be pre- loaded with a constant to provide the sum of products plus a constant. The asynchronous muitipler consists of the Booths encoder and the Wallace tree adders, which has been designed to handle 2s complement or unsigned magnitude numbers. The output registers hold the product as two 16-Bit words and one 3-Bit word: the Most Significant Product (MSP), the Least Significant Product (LSP), and the eXTended Product (XTP). Three-state output drivers permit the HS 1010 to be used on a bus, or allow the outputs to be multi- plexed over the same 16-Bit lines. The Least Significant Product (LSP) is multiplexed with the Y input. POWER The HS 1010 operates from a single +5 volt supply. All power and ground lines must be connected. NAME FUNCTION VALUE PIN NO. Voc Positive Supply Voltage +5.0V 49 GND Ground 0.0V 16 DATA INPUTS The HS 1010 has two 16-Bits 2s complement or un- signed magnitude data inputs, labeled X and Y. The Most Significant Bits (MSBs), denoted X14 through Xo and Y14 through Yo (with Xo and Yo the Least Signifi- cant Bits). Data present at the X and Y inputs is clocked into the input registers at the rising edge of the appro- priate clock. The input and output formats for fractional 2s complement notation, fractional unsigned magni- tude notation, integer 2s complement notation, and in- teger unsigned magnitude notation are shown in Figures 1 through 4, respectively. X DATA Y DATA TTL COMPATIBLE | PIN NO. | TTL COMPATIBLE | PIN NO. X15 MSB 56 Yis MSB 24 X14 57 Y14 23 X13 58 Y13 22 X42 59: Y12 21 Xa 60 Vu1 20 X10 61 Y10 19 9 62 Yo 18 Xe 63 Ys 17 x7 64 7 15 Xs 1 Ye 14 Xs 2 Ys 13 X4 3 Ys 12 X3 4 Y3 11 Xe 5 Yo 10 X 6 4 9 Xp LSB 7 Yo LSB 8 36 DATA OUTPUTS The HS 1010 has a 35-Bit 2s complement or unsigned magnitude result that is the sum of the products of the two input data values and the previous products which have been accumulated. The output is divided into two 16-Bit output words, the Most Significant Product (MSP) and Least Significant Products (LSP), and one 3-Bit word, the eXTended Product (XTP). The Most Significant Bit (MSB) of the XTP is the sign bit if 2s complement notation is used. The input and output for- mats for fractional 2s complement notation, fractional unsigned magnitude notation, integer 2s complement notation, and integer unsigned magnitude notation are shown in Figures 1 through 4, respectively. PRODUCT DATA PRODUCT DATA TTL COMPATIBLE | PIN NO. | TTL COMPATIBLE | PIN NO. P34 MSB 43 P.g MSB 25 Pas 42 Pus 24 P32 41 Pra 23 Pai 40 P43 22 Psp 39 Pie 22 Pag 38 Pay 20 Pos 37 Pio 19 Paz 36 Py 18 Pog 35 Ps 17 Pos 34 P; 15 Pog 33 Pg 14 Pag 32 Ps 13 Pap 31 Py 12 Pay 30 Ps 11 Pao 29 Pa 10 Pig 28 P, 9 Pag 27 Py LSB 8 Paz 26 CLOCK The HS 1010 has three clock lines, one for each of the input registers and one for the product register. Data present at the inputs of these registers is loaded into the registers at the rising edge of the appropriate clock. The RouND (RND), Twos Complement (TC), ACCumulate (ACC), and SUBtract (SUB) inputs are registered, with all four bits clocked in at the rising edge of the logical OR of both CLK X and CLK Y. Spe- cial attention to the clock signals is required if normally HIGH clock signals are used. Problems with the load- ing of these four control signals can be avoided by the use of normally LOW clocks. NAME FUNCTION VALUE PIN NO. CLKX Clock Input Data X TTL 51 CLKY Clock Input Data Y TTL 50 CLK P Clock Product Register TTL 44CONTROLS The HS 1010 has eight control lines. TSX, TSM, and TSL are three-state enable lines for the XTP, the MSP, and the LSP respectively. The output driver is in the high impedance state when TSX, TSM, or TSL is HIGH, and enabled when the appropriate control is LOW. PREload (PREL) is an active-high control which has several effects when active (see Table 1). First, all out- put buffers are forced into the high impedance state. Second, when any or all of TSX, TSM, and TSL are also HIGH, external data present at the output pins will be preloaded into the corresponding section of the out- put register on the rising edge of CLK P. Normal data setup and hold times apply both to the logical AND of PREL and the relevant three-state control (TSX, TSM, TSL) and to the data being preloaded. These setup and hold times are with respect to the rising edge of CLK P. RouND (RND) controls the addition of a 1 to the MSB of the LSP for rounding. When RND is HIGH, a 1 is added to the MSB of the LSP for rounding the product in the MSB and XTP (if appropriate) rather than trun- cating it. Twos Complement (TC) controls how the device inter- prets data on the X and Y inputs. TC LOW makes both inputs 2s complement inputs, while TC HIGH makes both inputs magnitude only inputs. When ACCumulate (ACC) is high, the content of the output register is added to or subtracted from the next product generated, and their sum is stored back into the output registers at the next rising edge of CLK P. When ACC is LOW, multiplication without accumula- tion is performed, and the next product generated is stored into the output registers directly. This operation is used for the first term in a summation to avoid a separate clear operation. The SUBtract (SUB) control is used in conjunction with the ACC control. When both the ACC and SUB con- trols are HIGH, the content of the output register is subtracted from the next product generated and the difference is stored back into the output register. Note that the previous output is subtracted from the product, not the product from the previous output. The RND, TC, ACC, and SUB inputs are registered, with all 4 bits clocked in at the rising edge of the logical OR of both CLK X and CLK Y. Special attention to the clock signals is required if normally HIGH clock signals are used. Problems with the loading of these four con- trol signals can be avoided by the use of normally LOW clocks. NAME FUNCTION VALUE PIN NO, TSX XTP 3-State Control TTL 47 TSM MSP 3-State Control TTL 45 TSL LSP 3-State Control TTL 55 PREL Preload Control! TTL 46 RND Round Control Bit TTL 54 TC 2's Complement Control TTL 48 ACC Accumulate Control TTL 52 SUB Subtract Control TTL 53 APPLICATIONS INFORMATION ABSOLUTE MAXIMUM RATINGS (Beyond which the device will be damaged) Supply Voltage . 6... eee eee O.5to +7.0V Input Voltage ..... 00... ee eee (GND) -0.5to (Vcc) +0.5V Operating Temperature (Tamibient)..-- ++... +++ 55C to + 125C Storage Temperature . 00.0.0... eee 65C to + 150C Lead Temperature (Soldering 10sec) ...............04. +300C NOTE: Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. OPERATING CONDITIONS Voc, Supply Voltage... 0.6... ee. +4.75to +5,.25V TopR, Operating Temperature: Commercial Tambient) ......0000 000000 c eee OCto +70C Military Tambient)..............0.0.00000. 55C to + 125C VIH High Level Input Voltage............ 0.00.2 eae 2.0V min Vi_, Low Level Input Voltage ..................0.000. 0.8V max tow, Clock Pulse Width... eee 25ns min ig, Input Register Setup Time ...........0.00.0.-.00-- 25 ns min th, Input Register HoldTime .................0....000.- 3ns min PIN CONFIGURATION x6 I e [64] X7 x5 [3] 63] x8 x4 [3] = x9 x (4 61] x10 x2 [ x11 x1 [Le] 59] X12 xo [7] [58] X13 yo.po (| [57] x14 vues 9] 56] X15 y2.P2 (0! 55] TSL ya.p3 [41] [54] AND va.pa (12 153} SUB ys.P5 [13] 52] Acc ve.pe [14 a CLK X Y7.P7 5 [50] CLK Y GND [6] [49] voc ye.es [17] [48] Tc Yo.p9 [78] TSX Yio.Pia = (79) aE PREL 11.P11 [20] | 45] TSM vi2.p12 [31] [aa] CLK P Y13.P13 [22 [43] P34 y14.Pi4 = [23] | 42] P33 v15.P15 [24] [47] P32 Pig = [25] a0} P31 P17 [26] /39] P30 pis [27] [38] P29 P19 (28 [37] P28 p20 [25 36) P27 p2i [Bo [35] P26 p22 [31] [34] P25 P23 [32] [33] P24 37APPLICATIONS INFORMATION (cont.) BINARY Figure 1. Fractional Two's Complement Notation Xa [Xra] Mag | Xr2 | X19 | X10 | Xo | Xe | Xr Xs | Xa | Xa | Xe] Xi | Xo | SIGNAL 2-0}2-1] 22 | 2-3] 2-4 | 2-6 | 2-8 | 2-7 | 2-8) 20 | 2-10] 2-11) 2-12) 2-13] 2-141 2-15 | DIGIT VALUE Yip 1sa] Yia | Yi2 1Y11 | Yao | Yo | Ye | Yr | Ye | Ys | Yo | Ya | Yo | Ys | Yo | SIGNAL x =2-0]2-1 | 2-2 | 2-3 [2-4 $25.) 2-8 | 2-7 | 2-8 | 2-0 | 2-10 | 2-11 | 2-12 | 2-13 | 2-14] 2-15 | DIGIT VALUE SIGNAL Ps [Pas {Ps2| Ps: | Pao |P20| P2e| Por | P20 | Pes | Pea | Pea} Pee | Par | Peo} Pio} Pis | Piz} Pre | Pas | Pra} Pris] Pia] Par | Pro] Po} Pe} Pr | Po| Ps} Pa} Ps | Po | Pr j Po 24l a3 [22] 21 | 20 [a+] 22] 2-9 [2-4] 25 | 28 | 2-7 | 2-8 | 2-0 | 2-10] 2-11] o-12| 2-13] 2-14] 2-15 [2-16] 2-17] 2-18] 2-10] 2-20] 2-21 | 2-22] 2-23 2-24] 2-25] 2-26] 2-27 | 2-28 | 2-204 2-30 xTP msP LSP DIGIT VALUE any Figure 2. Fractional Unsigned Magnitude Notation Xs | X14] Xia | X12 | Xtra | X10 | Xo | Xe | Xz | Xe | Xs | Xa] Xa | Xo | Xi | Xo | SIGNAL as|o2| 23] 24] 25 [20] 27 | 20] 20 | 2-10] 2-1 | o-12{ 213] 214] 2-15] 2-16 | DIGIT VALUE Yas | Ysa] Yia | Yi2 | Yi | Yto | Yo | Ya | Yr | Yo | Ys | Ya | Yo | Yo f Ys. | Yo | SIGNAL x 2+] 22/23] 2+] 25] 28 [27 [2 | 22] 2-10] 2-1 | 2-2] 2-19] 2-4] 2-15] 2-6 | DIGIT VALUE SIGNAL = | Pas] Psa] Paz} Par | Pao} Peo | Pze | Per | Pos | Pas | P2s | Pos | Pee | Pa | Pzo} Pio| Pra] Piz | Pre] Pis | Pro Prof Pro] Pas] Pro] Po | Pe | Pr | Pe Ps} Pa | Ps | Po | Pi] Po a2 | 21] 20] 2+] o2| 23| 24] 25] 26 | 2-7 fo0 | 2-9 | 2-10] 2-11] 2-12] 2-03] 2-14] 2-15] 2-16] 2-17 | 2-18] 2-19 2-20} 2-21 | 2-22] 2-23] 2-24] 9-25 | 2-28] 2-27] 2-28] 2-20] 2-90] 2-31] 2-32 XTP MSP LSP OIGIT VALUE . : BINARY Figure 3. Integer Two's Complement Notation POINT SIGNAL Xs X14 Xa X12 Xu X10 Xo Xe X7 Xe Xs Xe Xa Xe X Xo 218] 214 | 213 | at2 | 211] 210] 29 | 28 | 27 | oe | 2b | 26 | 29 | a2 | 21 | 20 DIGIT VALUE SIGNAL Yis |Y1a4 Yaa | Y12 | Yard Yio | Yo | Yo | Y7 | Ye | Ys | Ya | Ya | Ye | 1 | Yo x 215] 214 | 219 | a2] 211] 210 | 20 | 28] 27 | 26 | 25 | 24 | 29 | 22 | 21 | 20 DIGIT VALUE SIGNAL =| Pos [Pas | Paz | Ps: | Pso | Poe} Poa | Paz} Pos | Pas | P2a | Pzsj Paz| Par] Pao| Pro} Pre} Piz | Pro | Pas [Pra | Pra | Pre] Pav Pio} Po | Pa} Pr | Pe} Ps | Pa} Pa | Po] Pi Po 294] 223 | 232 | 291 | 220 | 220 | 220 | 227| gee] 225 | 224 | 223] 222) per} 220 | a1 | 218 | 217 J ave | 215 | 24 | 213 | 212] 211) 210] 29 | 28 | 27 | 26] 28 | 24] 23 | 22] 21 | 20 xTP mMsP tsp DIGIT VALUE . . aan . BINARY Figure 4. Integer Unsigned Magnitude Notation POINT 4 SIGNAL Xas | Xtra] Xia] Xr2] X11 Xo] Xo ] Xa] Xr | Xe Xs | Xa | Xo | Xe | Xr fe Xo 15 | ova] ara | o12] a1] 20 | 20 | 28 | 27] 26 | 25 | 26] 29] 22] 21 | 20 DIGIT VALUE SIGNAL Yis | Ysa | Yaa | Y12 | Yur | Yio | Yo | Ya Yr | Yo | Ys | Ya | Ya | Yo | Ys | Yo * gis | 214] 213 | a12| au | 200] 29 | 28 | 27 | 26} 25 | 24] 23 | 22 | 2t | 20 DIGIT VALUE SIGNAL ~ | Pse | Psa] Paz] Par} Pao | Poo | Pes | Per} Poe | Pas | Pas} Pas] Paz | Pa | Poo| Pie | Pra| Pr | Pre | Pre | Pea | Pas | Piz | Pas Pio] Po] Pa | Pr | Pa} Ps | Pay Ps | Po} Pr | Po 334 | 233] 232 | 23 | 290 | 920 | 228 [ 227 | oze | 205 | 224 | 2234 222 | 221 | 220} 219 | are) 217 | ave | a1 | 24 | 213 | 12] a1 | 200 | 20 | 28] 27 | 2e| 26 | 24] 23) 22] 21 | 20 XTP mMsP LSP DIGIT VALUE 38APPLICATIONS INFORMATION (cont.) vec nsSUB f ELECTRICAL CHARACTERISTICS ot (within specified operating conditions) p+ COMMERCIAL MILITARY TEST INOA/AA __ PARAMETER CONDITIONS | MIN TYP MAX] MIN | TYP] MAX| UNIT n+ locp Supply Current | Vog = 5.0V, D2 L- F = 10 MHz 25 40 25 | 50] mA locg Quiescent Voc = 5.0v, pWELL 4 VIN'= ov , TSL, TSM, A + TSX = 5.0V 100 250 | yA GND GND ILIH High Level Vec = max, input Current VIN'= 5.0V 5 25| yA . . wet npurwurreny Figure 6. Equivalent Input Circuit iLL Low Level Veco = max, Input Current VIN = OV 5 25] vA {02H Three-State | Voc = max, Leakage Current HIGH Z, VIN = 5.0V 10 50] wA Vec loz, Three-State Voc = max, Leakage Current HIGH Z, nSuUB VIN = OV 10 50] uA Vou High Level Veo = min, Output Voltage IOH = -1.0 mal 2.4 2.4 Vv Voi Low Level Voc = min, Output Volta lol = 4.0 mA 0.4 08] V utpu' ge OL m out SWITCHING CHARACTERISTICS (within specified operating conditions) a pWELL COMMERCIAL MILITARY GNO TEST . . sens if PARAMETER CONDITIONS | MIN| TYP | MAX | MIN| TYP | MAX | UNIT Figure 7. Equivalent Output Circuit tp Output Delay } Voc = min load 1 25 | 45 25 55 | ns tena Three-State +Vec Enable Delay Voc = min load 1 25] 45 25 55 | nS tpig Three-State Disable Delay Voc = min load 2 20 | 40 20 | 50] ns tac Multiply/ 8102 Accumulate Time | Voc = min load 1 78 | 100 7& | 120 ns To OUTPUT q- PIN Cy 40 pF 1N3062 TIMING DIAGRAM \ CONTROL \ INPUT AND DATA IN Gnp ew INPUT OUTPUT CLOCK PRELOAD 3-STATE CTRL 1ENA~ | tois ~ OUTPUT HIGH IMPEDANCE ~~ cLock j--tew \ wo \ / \ tpw \ l | | ! t bp fF Ne 1 | ( ! I ' | ts, eth is jwie tH 1 Dis} | PRELOAD DATA iN Figure 8. Test Load To output L_---- PIN 40 pF GND Figure 9. Three-State Delay Test Load 39APPLICATIONS INFORMATION (cont.) PREL' TSx! TSM' Tsu XTP mMsP LsP L L L L Register Register - Register Output Pin Output Pin Output Pin L L L H Register - Register Hi-Z Output Pin Output Pin L L H L Register - Hi - Z Register - Output Pin Output Pin L L H H Register - Hi-Z Hi-Z Output Pin L H L L Hi-Z Register - Register - Output Pin Output Pin L H L H Hi-Z Register - Hi-Z Output Pin L H H L Hi-Z Hi-Z Register - Output Pin L H H H Hi-Z Hi-Z Hi-Z H2 L L L Hi-Z Hi-Z Hi-Z H2 L L H Hi-Z Hi-Z Hi-Z Preload He L H L Hi-Z Hi-Z Hi-Z Preload H2 H L L Hi-Z Hi-Z Hi-Z Preload H2 H L H Hi-Z Hi-Z Hi-Z Preload Preload H2 H H L Hi-Z Hi-Z Hi-Z Preload Pretoad H2 H H H Hi-Z Hi-Z Hi -Z Preload Preload Preload NOTES: 1. PREL, TSX, TSM and TSL are not registered. 2. PREL Hi inhibits any change at output register for those outputs in which the three-state control Is low. Table 1. Preload Truth Table PACKAGE OUTLINES 64 PIN CERAMIC DIP UNITS: mm DIMENSIONS 0.140 nA80. MAX 0.25 79-132), : INCHES (mm) 0.05 0.019 + 9.005 0.125 + 0.025 ~ 0.002 3.175 + 0.635 0.049 + 0.029 0.888 . + + lo9.66 /YP 1.24 + 0.73 n D1 D b 5 B b D E ssw coool B 0.10 + 0.010-! 2.54 + 0.25 99 ae Tye ll Tr: 0.019 + o.oo} | 0.48 + 0.1 t WUC LOO OOO OOo Loon ono onoonan. OTS SSIS ORI ey l. | jo ORDERING INFORMATION PRODUCT TEMPERATURE NUMBER RANGE SCREENING PACKAGE HS 1010 CD 0C to +70C Commercial 64 lead DIP HS 1010 MD 55C to + 125C Military 64 lead DIP HS 1010 MD/883 55C to + 125C MIL-STD-883 64 lead DIP Contact factory for availability of the pin grid array or any special package or processing requirement. 40 40 (mA) 30 20 (ns) 100 70 (ns) 40 30 20 10 (ns) 20 15 10 TYPICAL IccD VS. FREQUENCY Vcc = 5.0V Ta = 25C ! | | 8 10 12 14 (MHz) TYPICAL Tmac VS. Ta Vcc = 5.0V | l | l | -50 0 50 100 1500 (C) TYPICAL THREE-STATE DELAY, OUTPUT DELAY VS. Ta pe os | j ! | i -50 0 50 100 150 = (C) Ta TYPICAL SETUP TIME VS. Ta Le ts | | | | 1 -50 0 50 100 150 (C) Ta