1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
N.C.
V
EE
HCPL-3140/HCPL-0314
Features
• 0.4 A minimum peak output current
• High speed response:
0.7 µs maximum propagation delay over temperature
range
• Ultra high CMR: minimum 25 kV/µs at VCM = 1 kV
• Bootstrappable supply current: maximum 3 mA
• Wide operating temperature range: –40°C to 100°C
• Wide VCC operating range: 10 V to 30 V over temp.
range
• Available in DIP8 and SO8 package
• Safety approvals: UL approval, 3750 Vrms for 1 minute.
CSA approval. IEC/EN/DIN EN 60747-5-2 approval
VIORM = 630 Vpeak (HCPL-3140)
Applications
•Isolated IGBT/Power MOSFET gate drive
•AC and brushless DC motor drives
•Inverters for home appliances
•Industrial inverters
•Switch Mode Power Supplies (SMPS)
Truth Table
LED VO
OFF LOW
ON HIGH
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage
and/or degradation which may be induced by ESD.
Functional Diagram
HCPL-3140, HCPL-0314
0.4 Amp Output C urrent IGB T Ga te Drive Optocoupler
Data Sheet
Description
The HCPL-3140/HCPL-0314 family of devices consists
of a GaAsP LED optically coupled to an integrated
circuit with a power output stage. These opto-
couplers are ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter
applications. The high operating voltage range of the
output stage provides the drive voltages required by
gate controlled devices. The voltage and current
supplied by this optocoupler makes it ideally suited for
directly driving small or medium power IGBTs. For
IGBTs with higher ratings, the HCPL-3150 (0.5 A) or
HCPL-3120 (2.0 A) opto-couplers can be used.
A 0.1 µF bypass capacitor must be
connected between pins VCC and VEE.
2
Package Outline Drawings
HCPL-3140 Standard DIP Package
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
OPTION CODE*
UL
RECOGNITION
UR
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
Ordering Information
HCPL-3140 and HCPL-0314 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS Non RoHS Surface Gull Tape IEC/EN/DIN
Number Compliant Compliant Package Mount Wing & Reel EN 60747-5-2 Quantity
HCPL-3140 -000E No option 50 per tube
-300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E #560 X X X X 1000 per reel
HCPL-0314 -000E No option X 100 per tube
-500E #500 X X 1500 per reel
-060E #060 X X 100 per tube
-560E #560 X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from
the option column to form an order entry.
Example 1:
HCPL-3140-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel
packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-3140 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for
information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th
July 2001 and RoHS compliant option will use ‘-XXXE’.
HCPL-3140 300 mil
DIP-8
HCPL-0314 SO-8
3
HCPL-0314 Small Outline SO-8 Package
HCPL-3140 Gull Wing Surface Mount Option 300 Outline Drawing
XXX
YWW
8765
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050)BSC
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012)MIN.
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
*
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
4
Solder Reflow Temperature Profile
Regulatory Information
The HCPL-3140/HCPL-0314 have
been approved by the following
organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
(Option 060 only)
UL
Approval under UL 1577,
component recognition program
up to VISO = 2500 Vrms. File
E55361.
CSA
Approval under CSA Component
Acceptance Notice #5, File CA
88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3140 Option 060)
Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I - IV
for rated mains voltage ≤ 300 Vrms I - III
for rated mains voltage ≤ 600 Vrms I-II
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 630 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with VPR 1181 Vpeak
tm=1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec, VPR 945 Vpeak
Partial discharge < 5 pC
Highest Allowable Overvoltage VIOTM 6000 Vpeak
(Transient Overvoltage tini = 10 sec)
Safety-limiting values - maximum values allowed in the
event of a failure.
Case Temperature TS175 °C
Input Current** IS,INPUT 230 mA
Output Power** PS, OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS>109Ω
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.
** Refer to the following figure for dependence of PS and IS on ambient temperature.
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°CPEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
Recommended Pb-Free IR Profile
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTU AL
PEAK TEMPERA TURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Note: Non-halide flux should be used.
5
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
125
100
300
500
700 I
S
(mA)
Insulation and Safety Related Specifications
Parameter Symbol HCPL-3140 HCPL-0314 Units Conditions
Minimum External Air Gap L(101) 7.1 4.9 mm Measured from input terminals
(Clearance) to output terminals, shortest
distance through air.
Minimum External Tracking L(102) 7.4 4.8 mm Measured from input terminals
(Creepage) to output terminals, shortest
distance path along body.
Minimum Internal Plastic Gap 0.08 0.08 mm Through insulation distance
(Internal Clearance) conductor to conductor, usually
the straight line distance
thickness between the emitter
and detector.
Tracking Resistance CTI >175 >175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa IIIa Material Group (DIN VDE
0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current (<1 µs pulse IF(TRAN) 1.0 A
width, 300pps)
Reverse Input Voltage VR5V
“High” Peak Output Current IOH(PEAK) 0.6 A 2
“Low” Peak Output Current IOL(PEAK) 0.6 A 2
Supply Voltage VCC-VEE -0.5 35 V
Output Voltage VO(PEAK) -0.5 VCC V
Output Power Dissipation PO250 mW 3
Input Power Dissipation PI45 mW 4
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Package Outline Drawings section
6
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
High Level Output Current IOH 0.2 A Vo = VCC- 4 2 5
0.4 0.5 Vo = VCC-10 3 2
Low Level Output Current IOL 0.2 0.4 A Vo = VEE+2.5 5 5
0.4 0.5 Vo = VEE+10 6 2
High Level Output Voltage VOH VCC-4 VCC-1.8 V Io = -100 mA 1 6,7
Low Level Output Voltage VOL 0.4 1 V Io = 100 mA 4
High Level Supply Current ICCH 0.7 3 mA Io = 0 mA 7,8 14
Low Level Supply Current ICCL 1.2 3 mA Io = 0 mA
Threshold Input Current IFLH 7 mA Io = 0 mA, 9,15
Low to High Vo>5 V
Threshold Input Voltage VFHL 0.8 V
High to Low
Input Forward Voltage VF1.2 1.5 1.8 V IF = 10 mA 16
Temperature Coefficient of DVF/DTA–1.6 mV/°C
Input Forward Voltage
Input Reverse Breakdown BVR5VI
R = 10 µA
Voltage
Input Capacitance CIN 60 pF f = 1 MHz,
VF = 0 V
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Power Supply VCC-VEE 10 30 V
Input Current (ON) IF(ON) 812mA
Input Voltage (OFF) VF(OFF) -3.6 0.8 V
Operating Temperature TA-40 100 °C
7
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Propagation Delay Time to tPLH 0.1 0.2 0.7 µs Rg = 47 Ω, 10,11, 14
High Output Level Cg = 3 nF, 12,13,
Propagation Delay Time to tPHL 0.1 0.3 0.7 µsf = 10 kHz, 14,17
Low Output Level Duty Cycle =
Propagation Delay PDD -0.5 0.5 µs50%, 10
Difference Between Any IF = 8 mA,
Two Parts or Channels VCC = 30 V
Rise Time tR50 ns
Fall Time tF50 ns
Output High Level Common
|CMH| 25 35 kV/µsT
A = 25°C, 18 11
Mode Transient Immunity VCM = 1 kV
Output Low Level Common
|CML| 25 35 kV/µs1812
Mode Transient Immunity
Package Characteristics
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Input-Output Momentary VISO 3750 Vrms TA=25°C, 8,9
Withstand Voltage RH<50% for
Input-Output Resistance RI-O 1012 ΩVI-O=500 V 9
Input-Output Capacitance CI-O 0.6 pF Freq=1 MHz
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.4 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection
current limit II-O ≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output
will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
8
Figure 1. VOH vs. temperature. Figure 2. IOH vs. temperature. Figure 3. VOH vs. IOH.
Figure 4. VOL vs. temperature. Figure 5. IOL vs. temperature. Figure 6. VOL vs. IOL.
Figure 7. ICC vs. temperature. Figure 8. ICC vs. VCC. Figure 9. IFLH vs. temperature.
(V
OH
-V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-50
-2.5
T
A
– TEMPERATURE – °C
125-25
0
0 25 75 10050
-2.0
-1.5
-1.0
-0.5
IOH – OUTPUT HIGH CURRENT – A
-50
0.30
TA – TEMPERATURE – °C
125-25
0.40
0 25 75 10050
0.32
0.34
0.36
0.38
0
-6
IOH – OUTPUT HIGH CURRENT – A
0.6
0
0.2 0.4
-5
-4
-3
-1
(VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V
-2
VOH
V
OL
– OUTPUT LOW VOLTAGE – V
-50
0.39
T
A
– TEMPERATURE – °C
125-25
0.44
0 25 75 10050
0.40
0.41
0.42
0.43
I
OL
– OUTPUT LOW CURRENT – A
-50
0.440
T
A
– TEMPERATURE – °C
125-25
0.470
0 25 75 10050
0.450
0.455
0.460
0.465
0.445
I
CC
– SUPPLY CURRENT – mA
-50
0
T
A
– TEMPERATURE – °C
125-25
1.4
0 25 75 10050
0.4
0.6
0.8
1.2
0.2
1.0
I
CC
L
I
CC
H
ICC – SUPPLY CURRENT – mA
10
0
VCC – SUPPLY VOLTAGE – V
3015
1.2
20 25
0.4
0.8
0.2
0.6
1.0
ICCL
ICCH
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-50
1.5
T
A
– TEMPERATURE – °C
125-25
3.5
0 25 75 10050
2.0
2.5
3.0
V
OL
– OUTPUT LOW VOLTAGE – V
0
0
I
OL
– OUTPUT LOW CURRENT – mA
700100
25
400 500
5
20
200 300 600
15
10
9
Figure 10. Propagation delay vs. VCC. Figure 11. Propagation delay vs. IF. Figure 12. Propagation delay vs. temperature.
Figure 13. Propagation delay vs. Rg. Figure 14. Propagation delay vs. Cg. Figure 15. Transfer characteristics.
Figure 16. Input current vs. forward voltage.
T
P
– PROPAGATION DELAY – ns
6
0
I
F
– FORWARD LED CURRENT – mA
18
400
91512
100
200
300
-50
0
T
A
– TEMPERATURE – °C
125-25
500
0 25 75 10050
100
200
300
400
T
P
– PROPAGATION DELAY – ns
T
PLH
T
PHL
TP – PROPAGATION DELAY – ns
0
200
Rg – SERIES LOAD RESISTANCE – Ω
200
400
50 150100
250
300
350
TPLH
TPHL
I
F
– FORWARD CURRENT – mA
1.2
0
V
F
– FORWARD VOLTAGE – V
1.8
25
1.4 1.6
5
10
15
20
TP – PROPAGATION DELAY – ns
0
0
Cg – LOAD CAPACITANCE – nF
100
400
20 8060
100
200
300
TPLH
TPHL
40
T
P
– PROPAGATION DELAY – ns
10
0
V
CC
– SUPPLY VOLTAGE – V
30
400
15 2520
100
200
300
T
PLH
T
PHL
VO – OUTPUT VOLTAGE – V
0
-5
IF – FORWARD LED CURRENT – mA
6
25
15
1
35
234
5
5
0
10
20
30
10
Figure 17. Propagation delay test circuit and waveforms.
Figure 18. CMR test circuit and waveforms.
0.1 µF V
CC
= 15
to 30 V
47 Ω
1
3
I
F
= 7 to 16 mA
V
O
+
–
+
–
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
3 nF
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
0.1 µF
VCC = 30 V
1
3
IF
VO+
–
+
–
2
4
8
6
7
5
A
+
–
B
VCM = 1500 V
5 V
VCM
∆t
0 V
VO
SWITCH AT B: IF = 0 mA
VO
SWITCH AT A: IF = 10 mA
VOL
VOH
∆t
VCM
δV
δt=
11
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF VCC = 15 V
1
3
+
–
2
4
8
6
7
5
HCPL-3140/HCPL-0314
Rg
Q1
Q2
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
Applications Information
Eliminating Negative IGBT Gate
Drive
To keep the IGBT firmly off,
the HCPL-3140/HCPL-0314 has a
very low maximum VOL
specification of 1.0 V. Minimizing
Rg and the lead inductance from
the HCPL-3140/HCPL-0314 to
the IGBT gate and emitter
(possibly by mounting the
HCPL-3140/HCPL-0314 on a
small PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in many
applications as shown in
Figure 19. Care should be taken
with such a PC board design to
avoid routing the IGBT collector
or emitter traces close to the
HCPL-3140/HCPL-0314 input as
this can result in unwanted
coupling of transient signals into
the input of HCPL-3140/
HCPL-0314 and degrade
performance. (If the IGBT
drain must be routed near the
HCPL-3140/HCPL-0314 input,
then the LED should be reverse
biased when in the off state, to
prevent the transient signals
coupled from the IGBT drain
from turning on the HCPL-3140/
HCPL-0314.)
Figure 19. Recommended LED drive and application circuit for HCPL-3140/HCPL-0314.
12
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT
and Rg in Figure 19 can be analyzed as a simple RC circuit with a
voltage supplied by the HCPL-3140/HCPL-0314.
The VOL value of 5 V in the previous equation is the VOL at the peak
current of 0.6A. (See Figure 6).
Step 2: Check the HCPL-3140/HCPL-0314 power dissipation and
increase Rg if necessary. The HCPL-3140/HCPL-0314 total power
dissipation (PT) is equal to the sum of the emitter power (PE) and the
output power (PO).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO(SWITCHING) = ICC •
VCC + ESW (Rg,Qg)• f
= (ICCBIAS + KICC •
Qg •
f) •
VCC + ESW (Rg,Qg) •
f
where KICC •
Qg •
f is the increase in ICC due to switching and KICC is a
constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF
(worst case) = 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%,
Qg = 100 nC, f = 20 kHz and TAMAX = 85°C:
PE = 10 mA • 1.8 V • 0.8 = 14 mW
PO = (3 mA + (0.001 mA/(nC • kHz)) • 20 kHz • 100 nC) • 24 V +
0.4
µ
J • 20 kHz = 128 mW
< 250 mW (PO(MAX) @ 85°C)
The value of 3 mA for ICC in the previous equation is the max. ICC over
entire operating temperature range.
Since PO for this case is less than PO(MAX), Rg = 32 Ω is alright for the
power dissipation.
= 24 V – 5 V
0.6A
= 32 Ω
Figure 20. Energy dissipated in the
HCPL-0314 and for each IGBT switching
cycle.
LED Drive Circuit Considerations for
Ultra High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC
as shown in Figure 21. The
HCPL-3140/HCPL-0314 improves
CMR performance by using a
detector IC with an optically
transparent Faraday shield, which
diverts the capacitively coupled
current away from the sensitive
IC circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and
opto-coupler pins 5-8 as shown in
Figure 22. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 19), can achieve
10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
Rg
≥
VCC – VOL
IOLPEAK
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
1.5
20
4.0
40
1.0
60 80
3.5 Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.0
0.5
2.5
13
Figure 21. Optocoupler input to output capacitance model
for unshielded optocouplers. Figure 22. Optocoupler input to output capacitance model
for shielded optocouplers.
Figure 23. Equivalent circuit for Figure 17 during common mode transient.
Figure 24. Not recommended open collector drive circuit. Figure 25. Recommended LED drive circuit for ultra-high CMR IPM
dead time and propagation delay specifications.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
ILEDP
CLEDP
CLEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+5 V
+
–V
CC = 18 V
• • •
• • •
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
CLEDP
CLEDN
SHIELD
+5 V
Q1
ILEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
14
CMR with the LED On (CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED
current of 8 mA provides
adequate margin over the
maximum IFLH of 5 mA to
achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive
circuit must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 23, the current flowing
through CLEDP also flows
through the RSAT and VSAT of the
logic gate. As long as the low
state voltage developed across
the logic gate is less than VF(OFF)
the LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 24, can not keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is
not recommended for
applications requiring ultra high
CMR1 performance. The
alternative drive circuit which
like the recommended
application circuit (Figure 19),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
IPM Dead Time and Propagation
Delay Specifications
The HCPL-3140/HCPL-0314
includes a Propagation Delay
Difference (PDD) specification
intended to help designers
minimize “dead time” in their
power inverter designs. Dead
time is the time high and low
side power transistors are off.
Any overlap in Ql and Q2
conduction will result in large
currents flowing through the
power devices from the high-
voltage to the low-voltage motor
rails. To minimize dead time in a
given design, the turn on of
LED2 should be delayed (relative
to the turn off of LED1) so that
under worst-case conditions,
transistor Q1 has just turned off
when transistor Q2 turns on, as
shown in Figure 26. The amount
of delay necessary to achieve this
condition is equal to the
maximum value of the
propagation delay difference
specification, PDD max, which is
specified to be 500 ns over the
operating temperature range of
-40° to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum
propagation delay difference
specification as shown in
Figure 27. The maximum dead
time for the HCPL-3140/HCPL-
0314 is 1 µs (= 0.5 µs - (-0.5 µs))
over the operating temperature
range of –40°C to 100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test conditions
since the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
15
Figure 26. Minimum LED skew for zero dead time.
Figure 27. Waveforms for dead time.
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
-
t
PHL MIN
) + (t
PLH MAX
-
t
PLH MIN
)
= (t
PHL MAX
-
t
PLH MIN
) – (t
PHL MIN
-
t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
(t
PHL-
t
PLH
)
MAX
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHL MAX
-
t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0366EN
AV02-0162EN April 26, 2007
