Device Engineering Incorporated DEI1066 OCTAL GND/OPEN INPUT, SERIAL OUTPUT INTERFACE IC 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com FEATURES * * * * * * Eight GND/OPEN discrete inputs o Meet electrical requirements for ABD0100 GND/OPEN discrete input. o Hysteresis provides noise immunity o Internal pull up resistor with 1mA source current to prevent dry relay contacts. o Internal isolation diode o Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3. 3-wire serial interface (/CS, CLK, DO) o Direct interface to Serial Peripheral Interface (SPI) port. o TTL/CMOS compatible inputs and Tristate output o 10MHz Data Rate o Serial input to expand Shift Register Logic Supply Voltage (VCC): 3.3V or 5V Analog Supply Voltage (VDD): 5V to 18V 16L NB SOIC package 16L Ceramic SO Package PIN ASSIGNMENTS DIN1 DIN2 1 16 DEI1066 VDD GND DIN3 VCC DIN4 GND DIN5 SDIN DIN6 /CS DIN7 SCLK DIN8 DOUT Figure 1 DEI1066 Pin Assignment (16 Lead NB SOIC) (c)2006 Device Engineering Inc Page 1 of 11 DS-MW-01066-01 Rev E 08/25/2006 FUNCTIONAL DESCRIPTION The DEI1066 is an eight-channel discrete-to digital interface BICMOS device. It senses eight Ground/Open discrete signals of the type commonly found in avionic systems. The data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus. Table 1 Pin Descriptions Pins 8-1 Name DIN[8:1] 9 DOUT 10 SCLK 11 /CS 12 SDIN 13 14 15 16 GND VCC GND VDD Description Parallel data inputs. Eight Ground/Open format discrete signals. These have an internal pull-up to VDD. The logic threshold and hysteresis characteristics are determined by the applied VDD voltage. Serial data output. This pin is the output from the last stage of the shift register. This is a 3-state output. Serial Shift Clock. A low-to-high transition on this input shifts data on the serial data input into the shift register and data in stage 8 is shifted out DOUT, being replaced by the data previously stored in stage 7. Chip Select. A high-to-low transition on this input loads data from the parallel DIN[8:1] inputs into the shift register. A low level on this input enables the DOUT 3-state output and the shift register. A high level on this input forces DOUT to the high impedance state and disables the shift register so SCLK transitions have no effect. Serial Data Input. Data on this input is shifted into the shift register on the rising edge of the SCLK input if the /CS input is low. This input has an internal pull-down resistor to GND. Logic Ground. Logic Supply Voltage. Analog Ground. Analog Supply Voltage. SDIN SDIN DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 INPUT RESISTORS, COMPARATORS, FILTERING, AND LIGHTNING PROTECTION (8 CHANNELS) DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 Q8 DOUT SHIFT REG SCLK SCK /CS SH/LD Figure 2 DEI1066 LOGIC DIAGRAM (c)2006 Device Engineering Inc Page 2 of 11 DS-MW-01066-01 Rev E 08/25/2006 Typical DINn Threshold Voltage & Hystersis R1 2K Vdd R2 DINn 12K Comparator with RC filter Vout D1 (to Shift Reg) Vdd Reference and Hysteresis DIN Threshold Voltage (V) Vdd 18 16 14 12 10 8 6 4 2 0 Vth+ Vth- 0 5 10 15 20 Vdd Supply Voltage (V) Figure 3 DINn Input Circuit Figure 4 DIN Threshold vs Vdd Table 2 Truth Table /CS 1 SCLK X X SDIN X X 0 0 0 X 0 1 X X DIN[8:1] X Sampled into Shift Register X X X X SREG Q1 X DIN1 0 1 No Change No Change DOUT HI-Z Enabled DIN8 SREG Q8 SREG Q8 No Change Disabled to HI-Z DIN[8:1] Input Structure Each of the eight discrete inputs consist of the circuit shown in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to the comparator IN+. The reference and hysteresis voltage is developed at the comparator IN-. Some notable features are: * * * * When Vdd is +15V, the circuit shall source >1mA to a grounded input. This current will prevent a "dry" relay contact. The input threshold voltage and hysteresis varies with the Vdd supply. o For Vdd of +5V, the falling Vth > 3.5V. o For Vdd of +15V, the rising Vth < 14V. o For Vdd of +18V, the rising Vth < 15.4V. o Hysteresis is approximately as shown in Figure 4. o The input thresholds vary with Vdd supply voltages and can be approximated as follows: For Vdd = 5V to 18V * Vlh_max = 0.98*Vdd - 0.65V * Vhl_min = 0.95*Vdd - 0.8V The comparator includes an RC filter to provide noise rejection of transient pulses of up to several uS. Thus there is a relatively large DINx setup time of several uS (Refer to timing parameter tsu2). The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during transient events. (c)2006 Device Engineering Inc Page 3 of 11 DS-MW-01066-01 Rev E 08/25/2006 Serial Interface and Shift Register The DEI1066 digital interface is an 8-Bit Serial or Parallel-Input / Serial-Output Shift Register with 3-State Output. The control inputs to the shift register are connected as shown in Figure 2 DEI1066 LOGIC DIAGRAM to implement an SPI compatible bus consisting of /CS, SCLK, DOUT, and SDIN. The Figure 5 waveform depicts a typical 8-Bit read cycle where the 8 DIN signals are read on to the serial bus. The Figure 6 waveform demonstrates a daisy-chain application where a 16-Bit read cycle includes the serial data passed through from the SDIN input. /CS SCLK DIN[8:1] SDIN X X VALID X X X X DOUT DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN inputs latched in S-Reg Figure 5 Serial Bus Read Cycle, 8 Bit /CS SCLK DIN[8:1] SDIN DOUT X X X VALID X X SI8 DIN8 SI7 DIN7 SI6 DIN6 SI5 DIN5 SI4 DIN4 SI3 DIN3 SI2 DIN2 SI1 DIN1 X SI8 SI7 SI6 SI5 SI4 SI3 SI2 SI1 Figure 6 Serial Bus Read Cycle, 16 Bit Daisy Chain (c)2006 Device Engineering Inc Page 4 of 11 DS-MW-01066-01 Rev E 08/25/2006 Lightning Protection DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3, Waveforms 3, 4, and 5A, Level 3. See waveforms below. V V/I T1 = 6.4uS T2 = 70uS Peak 25% to 75% of Largest Peak 50% t 0 50% F = 1MHZ and 10MHZ 0 T1 t T2 Figure 7 Voltage / Current Waveform 3 Figure 8 Voltage Waveform 4 V/I Peak T1=40uS T2=120uS Waveform Source Impedance characteristics: * Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms * Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms * Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm 50% 0 T1 T2 Figure 9 Current/Voltage Waveform 5A (c)2006 Device Engineering Inc Page 5 of 11 DS-MW-01066-01 Rev E 08/25/2006 t ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings MIN MAX UNITS Vcc Supply Voltage PARAMETER -0.3 +7.0 V Vdd Supply Voltage -0.3 20 V -55 -55 +85 +125 C -55 -65 +150 +150 C -5 -600 -300 -1.5 -0.5 +40 +600 +300 VCC + 1.5 VCC + 0.5 V V V V v 0.8 0.53 W W Operating Temperature Plastic Packages Ceramic Packages Storage Temperature Plastic Packages Ceramic Packages Input Voltage DIN[8:1] Continuous DO160D, Waveform 3, Level 3 DO160D, Waveform 4 and 5, Level 3 Logic Inputs DOUT Power Dissipation @ 85 C: (> 10 Sec) 16 Lead SOIC 16 Lead CSOP Junction Temperature: Tjmax, Plastic Packages Tjmax, Ceramic Packages ESD per JEDEC A114-A Human Body Model Logic and Supply pins DIN pins 145 150 C C 2000 1000 V Lead Soldering Temperature (10 sec duration) 280 C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground Table 4 Recommended Operating Conditions PARAMETER Supply Voltage Logic Inputs and Outputs Discrete Inputs Operating Temperature Plastic Ceramic (c)2006 Device Engineering Inc SYMBOL CONDITIONS VCC VDD 5.0V10%, 3.3V10% 5.0 to 18V 0 to VCC 0 to 40V DIN[8:1] -55 to +85 C -55 to +125 C Page 6 of 11 DS-MW-01066-01 Rev E 08/25/2006 Table 5 DC Electrical Characteristics SYMBOL PARAMETER TEST CONDITIONS VCC (V) LIMITS UNIT -55 to +85C -55 to +125C 2.0 2.0 2.0 0.8 0.8 0.8 2.0 2.0 2.0 0.8 0.8 0.8 50 50 mV VCC - 0.1 VCC - 0.1 V 3.2 4.5 3.0 4.3 V 3.0 4.5 5.5 4.5 5.5 0.1 0.1 0.1 0.33 0.33 0.1 0.1 0.1 0.40 0.40 5.5 5.5 5.5 1.0 750 5.0 2.0 750 10.0 uA 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 15.7 14.2 1.0 5 20 -1.6 -1.0 15.9 14.2 1.0 10 40 -1.6 -1.0 V V V uA 3.0 to 5.5 3.0 to 5.5 4.35 3.53 0.33 5 20 -0.5 -0.25 4.35 3.53 0.33 10 40 -0.5 -0.25 mA mA 6.0 200 400 uA 6.0 6.0 11 23 11 24 mA LOGIC INPUTS AND OUTPUTS VDD = +5V to +18V VIH Min hi level input voltage VIL Max lo level input voltage VIhst Min input hysteresis voltage, SCLK input (1) VOH Min hi level output voltage |IOUT| < 20uA |IOUT| < 4.5mA VOL Max low level output voltage |IOUT| < 20uA |IOUT| < 4.5mA IIN IOZ Max input leakage Logic inputs except SDIN. SDIN Max 3-state leakage current VIH VIL VIhst IIH Min HI level input voltage Max LO level input voltage Min input hysteresis voltage Max hi level input current IILmax IILmin Max lo level input current Min lo level input current VIH VIL VIhst IIH Min HI level input voltage Max LO level input voltage Min input hysteresis voltage Max hi level input current IILmax IILmin Max lo level input current Min lo level input current ICC Max quiescent logic supply current Max quiescent analog supply current IDD (c)2006 Device Engineering Inc 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 4.5 5.5 V V V V Vin = Vcc or GND Output in Hi Impedance state. DISCRETE INPUTS VDD = +18V Vin = 18V Vin = 40V Vin = 0V Vin = 0V DISCRETE INPUTS VDD = +5V Vin = 18V Vin = 40V Vin = 0V Vin = 0V SUPPLY VOLTAGES VDD = +15V Vin(logic) = Vcc or GND VIN[8:1] = open Vin(logic) = Vcc or GND VIN[8:1] = Open VIN[8:1] = GND Page 7 of 11 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 uA mA mA V V V uA DS-MW-01066-01 Rev E 08/25/2006 Table 6 AC Electrical Characteristics LIMITS PARAMETER (4,6 & 7) SYMBOL fMAX VCC (V) Maximum SCLK frequency. (50% duty cycle) (5) Maximum usable SCLK frequency = 1/(tp2 + tsu3) tW Minimum SCLK pulse width. (50% duty cycle) tsu1 Minimum setup time, SCLK low to /CS. th1 Minimum hold time, /CS to SCLK. tsu2 th2 tsu3 Setup time, DIN valid to /CS. (8) Hold time, /CS to DIN not valid. (8) Minimum setup time, SDIN valid to SCLK. th3 Minimum hold time, SCLK to SDIN not valid. tp1 Maximum propagation delay, /CS to DOUT valid. (1) tp2 Maximum propagation delay, SCLK to DOUT valid. (1) tp3 Maximum propagation delay, /CS to DOUT HI-Z. (1) (2) (3) tp4 Minimum time between /CS active. Cin Cout 1. 2. 3. 4. 5. 6. 7. 8. 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 5.0 5.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -55 to +85C -55 to +125C 4.8 24 28 2.8 10.7 14.6 100 20 17 100 50 40 20 20 20 35 -1.5 75 20 15 5 5 5 220 55 47 295 90 70 320 80 59 50 25 25 10 15 4.0 20 24 2.2 8.2 11.2 120 24 20 100 50 40 20 20 20 35 -1.5 80 25 15 5 5 5 265 72 52 380 102 75 380 103 77 50 25 25 10 15 UNIT MHz nS nS nS uS uS nS nS nS nS nS nS Maximum logic input pin Capacitance. (5) pF Maximum DOUT pin capacitance, output in HI-Z state. (5) pF DOUT loaded with 50pF to GND. DOUT loaded with 1K Ohms to GND for Hi output, 1K Ohms to VCC for Low output. Timing measured at 25%VCC for "0" to Hi-Z, 75%VCC for "1" to Hi-Z. Sample tested on lot basis. Not tested Unless otherwise noted, VDD=+15V, VIL = 0V, VIH = VCC Measurements made at 50%VCC. Vdd = 6V. tsu2 represents the maximum possible propagation delay through the input comparator. th2 represents the minimum possible propagation delay through the input comparator. The negative hold time denotes that DIN may change prior to /CS and still be valid data at the S-Register. (c)2006 Device Engineering Inc Page 8 of 11 DS-MW-01066-01 Rev E 08/25/2006 /CS tsu1 th1 tsu2 th2 tp4 tW SCLK DIN[8:1] X 1/fmax valid X tsu3 th3 SDIN X valid tp2 tp1 DOUT X DIN8 tp3 DIN7 Figure 10 Switching Waveforms (c)2006 Device Engineering Inc Page 9 of 11 DS-MW-01066-01 Rev E 08/25/2006 PACKAGE DESCRIPTIONS 16 Lead Narrow Body SOIC Moisture Sensitivity: ja: jc: Level 2 per JEDEC J-STD-020A (1yr floor life) 73.6C/W (Mounted on 4 layer PCB) 29.8C/W 7 C L C L PIN NO 1 DETAIL-A h X 45 DETAIL-A a A1 SOIC-16LD SOIC-16LD MILLIMETERS MIN MAX SYMBOL SYMBOL C .0040 .0098 A1 0.10 0.25 INCHES MIN MAX B .014 .018 B C .0075 .0098 C D .386 .393 D 9.80 9.98 E .150 .157 E 3.81 3.99 e .050 BSC e 1.27 BSC H .2284 .2440 H 5.80 6.20 h .0099 .0196 h 0.25 0.50 L .016 .050 L 0.41 1.27 A .060 .068 A 1.52 1.72 a 8 0 a ZD .020 REF ZD A2 .054 .062 A2 0.36 0.46 0.19 0.25 0 8 0.51 REF 1.37 1.57 Figure 11 16 Lead Narrow Body SOIC Outline Drawing (c)2006 Device Engineering Inc Page 10 of 11 DS-MW-01066-01 Rev E 08/25/2006 16 Lead Ceramic Small Outline Package (CSOP) Theta ja: Theta jc: Moisture Sensitivity Level: 122 C/W Device mounted on 2 layer PCB 5 C/W Hermetic Figure 12 16 Lead CSOP Outline Drawing ORDERING INFORMATION Table 7 Part Number DEI1066-SES DEI1066-SMS DEI1066-SMB DEI1066-WMS DEI1066-WMB Marking DEI1066-SES DEI1066-SMS DEI1066-SMB DEI1066-WMS DEI1066-WMB Package 16 SOIC 16 SOIC 16 SOIC 16 CSOP 16 CSOP Burn In No No 96hr / +125 C No 96hr / +125 C Temperature -55 / +85 C -55 / +125 C -55 / +125 C -55 / +125 C -55 / +125 C DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. (c)2006 Device Engineering Inc Page 11 of 11 DS-MW-01066-01 Rev E 08/25/2006