SPECIFICATION
SPEC. No.
Customer DATE：
CUSTOMER’S PRODUCT NAME
TDK PRODUCT NAME
MULTILAYER CERAMIC CHIP CAPACITORS
CKD710JB, CKD610JB, CKD510JB, CKD110JB,
CKD310JB T ype(Low ESL Feed Trough)
Please sign retu rn this specificat ion to TDK representatives. If orders are placed without
this returned docume ntation, we must consider you found the specificati on acceptable.
THIS SPECIFICATION IS RECEIVED
DATE: YEAR MONTH DAY
ENGINEERING
ISSUED CHECKED APPROVED
DATE DATE DATE
PRODUCT CLASSIFICATION
CODE 040320
REV 0.3 / 201012
Sales Office
Sales Tel. （ ）
TDK-EPC Corporation
1-13-1, Nihonbashi, Chuo-ku, Tokyo
103-0027 , Japan
1 of 27
1. SCOPE
This specification is applicable to chip type multilayer ceramic capacitors with a priority over other
relevant specifications. Production places defined in this specification shall be TDK-EPC
Corporation Japan, TDK-EPC HONG KONG LIMITED, TDK (Suzhou) Co., Ltd, TDK (Malaysia) Sdn.
Bhd and TDK Components U.S.A. Inc.
EXPLANATORY NOTE:
This specification warrants the quality of the TDK ceramic chip capacitor. The product should
be evaluated and confirmed in your product before use. If the use of the product exceeds the
bounds of the specification, we can not guarantee its quality and/or reliability.
2. CODE CO NST RUCTI ON
CKD610JB 0J 225 S T
(Example)
(1) (2) (3) (4) (5)
1. Type
Please refer to product list for the dimension of each product. See Section 8 for inside structure and
material.
T
Internal electrode Ceramic dielectric
W
L
Terminal electrode
B
B
C
2 of 27
Symbol Rated Voltage
1 H 50 V DC
1 E 25 V DC
1 C 16 V DC
1 A 10 V DC
0 J 6.3 V DC
2. Rated Voltage
3. Rated Capacitance
Stated in three digits and in units of pico farads (pF).The first and second digits identify the
first and second significant figure of the capacitance, the third digit identifies the multiplier.
R is designated for a decimal point.
Example 225 → 2,200,000pF
4. Capacitance tolerance Symbol Tolerance
S + 50, -20 %
See the cap range chart In the TDK Product Guide for this
series to obtain item specific parameters.
M ±20 %
Symbol Packaging
B Bulk
T Taping
5. Packaging
3. RATED CURRENT
DC2A
DC1A
DC500mA
DC400mA
DC200mA
See the cap range chart In the TDK Product Guide for this series to obtain item specific
parameters.
4. OPERATING TEMPERATURE RANGE
-25 ～ 85°C
-55 ～ 85°C
-55 ～ 125°C
See the cap range chart In the TDK Product Guide for this series to obtain item specific
parameters
5. STORING CONDITION AND TERM
5 to 40°C at 20 to 70%RH
6 months Max.
6. INDUSTRIAL WASTE DISPOSAL
Dispose this product as industrial waste in accordance with the local Industrial Waste Laws.
3 of 27
7. PERFORMANCE
No. Item Performance Test or inspection method
1 External Appearance No defects which may affect
performance.
Inspect with magnifying glass (3X)
2 Insulation Resistance 10,000MΩ or 500MΩ·μF min.
whichever smaller (As for the
capacitors of rated voltage 16, 10,
6.3V DC, 100MΩ·μF min.).
Apply rated voltage for 60s.
3 Direct Current
Resistance
Rdc (1-2)
Rdc is between 5MΩ - 600 MΩ
depending on item. See the cap
range chart in the TDK Product
Guide for this series to obtain item
specific parameters.
Measuring current should be 100mA max.
4 Voltage Proof Withstand test voltage without
insulation breakdown or other
damage.
2.5 times of rated voltage.
Above DC voltage shall be applied for
1 to 5s.
Charge / discharge current shall not
exceed 50mA.
Measuring
frequency Measuring voltage
0.5±0.2Vrms.
1kHz±10% 1.0±0.2Vrms.
5 Capacitance Within the specified capacitance
tolerance.
6 Dissipation Factor
(DF)
Max. DF= 0.10
See No.5 in this table for measuring
condition.
Ω
12
4
3
4 of 27
(7. Performance, continued)
No. Item Performance Test or inspection method
7 Bending No mechanical damage.
Reflow solder the capacitor on P.C. board
(shown in Appendix 2, Appendix 4 or
Appendix 6) and bend 1mm.
(Unit: mm)
8 Solderability New solder to cover over 75% of
termination.
25% may have pin holes or rough
spots but not concentrated in one
spot.
Ceramic surface of “A sections”
shall not be exposed due to
melting or shifting of termination
material.
Completely soak both terminations in
solder at 235±5°C for 2±0.5s.
Solder: H63A (JIS Z 3282)
Flux: Isopropyl alcohol (JIS K 8839)
Rosin(JIS K 5902) 25% solid
solution.
External
appearance No mechanical damage.
Change from the value before test
± 7.5 %
Capacitance
D.F.
Meet the initial spec.
Insulation
Resistance Meet the initial spec.
Voltage
proof No insulation breakdown or
other damage.
9 Resistance
to solder
heat
Resistance
for DC
Rdc
1.0 Ω max.
Completely soak both terminations in
solder at 260±5°C for 5±1s.
Preheating condition
Temp.: 150±10°C
Time: 1 to 2min.
Flux: Isopropyl alcohol (JIS K 8839)
Rosin (JIS K 5902) 25% solid
solution.
Solder: H63A (JIS Z 3282)
Leave the capacitor in ambient conditions
for 24±2h before measurement.
1
20
50 F
R230
45 45
A section
5 of 27
(7. Performance, continued)
No. Item Performance Test or inspection method
External
appearance No mechanical damage.
Change from the value before test
± 7.5 %
Capacitance
D.F. Meet the initial spec.
Insulation
Resistance Meet the initial spec.
10 Temperature
cycle
Resistance
for DC
Rdc
1.0Ω max.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1 or
Appendix 3) before testing.
Expose the capacitor in the conditions
step1 through step 4 and repeat 5 times
consecutively.
Leave the capacitor in ambient
conditions for 24±2h before
measurement.
External
appearance No mechanical damage.
Change from the value before test
± 12.5 %
Capacitance
D.F.
Characteristics
200% of initial spec. max.
Insulation
Resistance
1,000MΩ or 50MΩ·μF min.
whichever smaller. (As for the
capacitors of rated voltage 16, 10,
6.3V DC, 10MΩ·μF min.,)
11 Moisture
Resistance
(Steady
State)
Resistance
for DC
Rdc
1.0 Ω max.
Reflow solder the capacitors on P.C.
board (shown in Appendix 1 or
Appendix 3) before testing.
Leave at temperature 40±2°C, 90 to
95%RH for 500 +24,0h.
Leave the capacitor in ambient
conditions for 24±2h before
measurement.
Step Temperature(°C) Time (min.)
1 Min. operating
temp. ± 3 30 ± 3
2 20 ± 2 2 - 5
3 Max. operating
temp. ± 2 30 ± 2
4 20 ± 2 2 - 5
6 of 27
(7. Performed, continued)
No. Item Performance Test or inspection method
External
appearance
No mechanical damage.
Change from the value before test
± 15 %
Capacitance
D.F. Characteristics
200% of initial spec. max.
Insulation
Resistance
1,000MΩ or 50MΩ·μF min.
whichever smaller. (As for the
capacitors of rated voltage 16,
10, 6.3V DC, 10MΩ·μF min.,)
12 Life
Resistance
for DC
Rdc
1.0 Ω max.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1, Appendix
3 or Appendix 5) before testing.
Below the voltage shall be applied at
maximum operating temperature ±2°C
for 1,000 +48, 0h.
Applied voltage is 1xRV; however some
items may be tested at higher voltage
(1.2x, 1.5x or 2xRV). Contact TDK for
details.
Charge/discharge current shall not
exceed 50mA.
Leave the capacitor in ambient
conditions for 24±2h before
measurement.
Voltage conditioning:
Voltage treats the capacitor under
testing temperature and voltage for 1
hour.
Leave the capacitor in ambient
conditions for 24±2h before measurement.
Use this measurement for initial value.
*As for the initial measurement of capacitors on number 9, 10 and 11, leave capacitors at 150 –10, 0°C for
1 hour and measure the value after leaving capacitors for 24±2h in ambient condition.
7 of 27
Appendix - 1
P.C. Board for reliability test
Appendix - 2
P.C. Board for bending test
Dimensions (mm)
TDK (EIA style) a b c d e f
CKD710JB 0.7 0.3 0.19 0.6 0.25 0.25
1. Material: Glass Epoxy (As per JIS C6484 GE4)
2.Thickness：1.6mm Copper(Thickness 0.035mm)
Solder resist
a
b b
f
f
e
c
d
40
100
Solder resist Copper
4
100
Solder resist Copper
(Unit: mm) (Unit: mm)
8 of 27
Appendix - 3
P.C. Board for reliability test
Appendix - 4
P.C. Board for bending test
Appendix - 3 Dimensions (mm)
TDK (EIA style) a b c d e f
CKD610JB 1.0 0.6 0.4 0.6 0.4 0.4
Appendix - 4 Dimensions (mm)
TDK (EIA style) a b c d
CKD610JB 0.4 0.5 0.4 2.0
1. Material: Glass Epoxy (As per JIS C6484 GE4)
2.Thickness：1.6mm Copper(Thickness 0.035mm)
Solder resist
40
100
a
b b
c
d
c
a
b b
f
f
e
c
d
40
100
Solder resist Copper
(Unit: mm) (Unit: mm)
9 of 27
Appendix - 5
P.C. Board for reliability test
Appendix - 6
P.C. Board for bending test
Dimensions (mm)
TDK (EIA style) a b c d e f
CKD510JB 1.4 0.6 0.5 0.8 0.6 0.65
CKD110JB 2.5 0.7 1.4 1.0 0.6 0.7
CKD310JB 2.5 1.2 1.4 1.3 0.8 0.9
1. Material: Glass Epoxy (As per JIS C6484 GE4)
2.Thickness：1.6mm Copper(Thickness 0.035mm)
Solder resist
a
b b
f
f
e
c
d
40
100
40
100
Solder resist Copper
(Unit: mm) (Unit: mm)
10 of 27
8. INSIDE STRUCTURE AND MATERIAL
〈A-A’〉 〈B-B’〉
No. NAME MATERIAL
1 Dielectric CaZrO3 or BaTiO3
2 Electrode Nickel (Ni)
3 Copper (Cu)
4 Nickel (Ni)
5
Terminat ion
Ti n (S n )
34 5
1 2
34
5
A
B’
B A’
11 of 27
9. Caution
No. Process Condition
1.1 Storage
1.
2.
3.
4.
5.
The capacitor must be stored in an ambient temperature of 5 to 40°C with a relative
humidity of 20 to 70%RH. The product should be used within 6 months upon
receipt.
The capacitors must be operated and stored in an environment free of
condensation and corrosive gases such as hydrogen sulphide, hydrogen sulphate,
chlorine, ammonia and sulfur.
Avoid storing in sun light and falling of dew.
Do not use capacitor under high humidity and high/low atmospheric pressure
which may compromise product reliability.
Capacitors should be tested for the solderability when they are stored for long
periods of time.
1.2 Handling in transportation
1 Operating
Condition
(Storage,
Transportation)
In case of the transportation the performance of the capacitor may be deteriorated
depending on the transportation condition. (Refer to JEITA RCR-2335B 9.2
“Handling in Transportation”)
2.1 Operating temperature
Operating temperature should be followed strictly within this specification,
especially be careful with maximum temperature.
1.
2.
3.
Do not use capacitors above the maximum allowable operating temperature.
Surface temperature including self heating should be below maximum operating
temperature.
(Due to dielectric loss, capacitors will heat itself when AC is applied. Especially at
high frequencies around its SRF, the heat might be so extreme that it may damage
itself or the product its mounted on. Please design the circuit so that the maximum
temperature of the capacitors (including the self heating) will be below the
maximum allowable operating temperature. Temperature rise at capacitor surface
shall be below 20°C)
The electrical characteristics of the capacitors will vary depending on the
temperature. The capacitors should be selected and designed after taking the
temperature into consideration.
2.2 Operating voltage
1. Operating voltage across the terminals should be below the rated voltage.
When AC and DC are super imposed, V0-P must be below the rated voltage.
Reference figures 1 and 2 below.
AC or pulse with overshooting, VP-P must be below the rated voltage. Reference:
figures 3, 4, and 5 below.
When the voltage is started/ stopped to apply to the circuit an irregular voltage
may be generated for a transit period because of resonance or switching. Be sure
to use the capacitor within its rated voltage during these Irregular voltage periods.
Voltage (1) DC voltage (2) DC+AC voltage (3) AC voltage
Positional
Measurement
(Rated voltage)
V0-P
0
V0-P
0
VP-P
Voltage (4) Pulse voltage (A) (5) Pulse voltage (B)
2 Circuit design
Positional
Measurement
(Rated voltage)
VP-P
VP-P
0
0
0
12 of 27
(9. Caution, continued)
No. Process Condition
2.2
2.
3.
Operating Voltage (continued)
Even below the rated voltage, if repetitive high AC frequency or pulsed voltage is
applied, the reliability of the capacitors may be reduced.
The effective capacitance will vary depending on applied DC and AC voltages.
The capacitors should be selected after considering the voltage affect.
2.3 Frequency
2 Circuit design
When Class 2 capacitors are used in AC and/or pulse voltages, the capacitors may
self vibrate and generate audible sound (piezoelectric affect).
The amount of solder at the terminations directly impacts the reliability of the capacitor.
1.
2.
3.
The greater the amount of solder, the higher the stress on the chip capacitor, and the
more likely that it will break. When designing a P.C. board, determine the shape and
size of the solder lands to ensure the proper amount of solder is applied to the
terminations.
Avoid using common solder land for multiple terminations and provide individual
solder land for each termination instead.
Size and recommended land dimensions provided below:
<CKD710JB>
Chip mounted size Back side:
Back side shall be connected to the
ground pattern of the chip mounted
side. Please design the back side
ground as large as possible.
*If thorough hole is too large, solder
paste may come into the hole and
make bad connection with the
ground pattern.
Resist Cu pattern No pattern
(mm)
Type
Symbol a b c d e
CKD710JB 0.19 0.7 1.3 0.6 0.75
3 Designing
P.C. Board
Throu
g
h hole
φ
0.4～0.6
b
a
d e
c
Connect to the ground pattern of the
chip mounted side.
Ground pattern
13 of 27
(9. Caution, continued)
No. Process Condition
<CKD610JB>
Chip mounted size Connect to the ground pattern
of the chip mounted side.
”Through hole” should be
designed as close to GND
terminal as possible.
Resist Cu pattern No pattern
(mm)
Type
Symbol a b c d e
CKD610JB 0.4 1.2 2.2 0.7 1.4
3 Designing
P. C . B o a r d
<CKD510JB, CKD110JB, CKD310JB>
Chip mounted size
Resist Cu pattern No pattern
Back side:
Back side shall be connected to the
ground pattern of the chip mounted side.
Please design the back side ground as
large as possible.
*If through hole is too big, solder paste
may come into the hole and make bad
connection with the ground pattern.
(mm)
Type
Symbol a b c d e
CKD510JB 0.5 1.5 2.6 1.0 2.0
CKD110JB 1.4 2.5 4.5 1.0 2.0
CKD310JB 1.4 2.5 4.5 1.2 2.4
a
Throu
g
h hole
Ø0.4-0.6
d e
b
c
a
Throu
g
h hole
Ø0.4-0.6
d e
b
c
Connect to the ground pattern of the
chip mounted side.
Ground pattern
14 of 27
(9. Caution, continued)
No. Process Condition
4. Recommended chip capacitor layout is provided below:
Disadvantage against
bending stress
Advantage against
bending stress
Mounting
face
Perforation or slit
Break P.C. board with
mounted side up.
Perforation or slit
Break P.C. board with
mounted side down.
Chip
arrangement
(Direction)
Mount perpendicularly to
perforation or slit
Perforation or slit
Mount in parallel with
perforation or slit
Perforation or slit
Distance from
slit
Closer to slit is higher stress
ℓ 1
(ℓ 1 < ℓ2 )
Away from slit is less stress
ℓ 2
(ℓ 1 < ℓ 2
)
Designing
P.C. Board
(continued)
15 of 27
(9. Caution, continued)
No. Process Condition
3 Designing
P. C . B o a r d
(continued)
5. Mechanical stress varies according to location of chip capacitor on the P.C. board.
Perforation
The relative stress applied to these capacitors during depaneling is in the following
order:
A > B = C > D > E
4 4.1 Stress from mounting head
If the mounting head is adjusted too low, it may induce excessive stress on the chip
capacitor and to result in cracking. Please take following precautions.
1.
2.
3.
Adjust the bottom dead center of the mounting head to reach the P.C. board surface but
do not contact it.
Adjust the mounting head pressure to be 1 to 3N of static weight.
To minimize the impact energy from mounting head, it is important to provide support
from the bottom side of the P.C. board. See following examples.
Not recommended Recommended
Single sided
mounting
Double-sides
mounting
Mounting
When the centering jaw is worn, mechanical impact on the capacitor may occur and
damage the product. Please control the closing dimension of the centering jaw and
provide sufficient preventive maintenance and/or replacement if necessary.
A
C
D
B
E
Slit
Crac
k
Su
pp
or
t
Su
pp
or
t
Solder
peeling Crack
16 of 27
(9. Caution, continued)
No. Process Condition
5.1 Flux selection
Although highly-activated flux gives better solderability, substances which increase
activity may also degrade the insulation of the chip capacitor. To avoid such
degradation, the following is recommended.
1.
2.
3.
Use a mildly activated rosin flux (less than 0.1wt% chlorine).
Excessive flux must be avoided. Please provide proper amount of flux.
When water-soluble flux is used, sufficient washing is necessary.
5.2 Recommended soldering profile by various methods
5.3 Recommended soldering peak temp and duration
Reflow soldering
Temp./Duration
Solder Peak temp(°C) Duration(sec.)
Sn-Pb Solder 230 max. 20 max.
Lead Free Solder 260 max. 10 max.
5 Soldering
Recommended solder compositions
Sn-37Pb (Sn-Pb solder)
Sn-3.0Ag-0.5Cu (Lead Free Solder)
∆T
Preheatin
g
3sec. (As short as possible)
0
Te m p .. (°C)
300
Manual soldering
(Solder iron)
0
∆T
Over 60 sec.
Natural cooling
Preheating
Soldering
Reflow soldering
P
ea
k
Temp
Te m p .. (°C)
Peak Temp time
17 of 27
(9. Caution, continued)
No. Process Condition
5.4 Avoiding thermal shock
Preheating condition
Soldering Temp. (°C)
Reflow soldering ∆T ≤ 150
1.
Manual soldering ∆T ≤ 150
2.
Cooling condition
Natural cooling using air is recommended. If the chips are dipped into a solvent
for cleaning, the temperature difference (∆T) must be less than 100°C.
5.5 Amount of solder
Excessive solder will induce higher tensile force on the chip capacitor during
temperature changes and may result in chip cracking. Insufficient solder may
detach the capacitor from the P.C. board.
Excessive
solder
Higher tensile force on
the chip capacitor may
cause cracking.
Adequate
Insufficient
solder
Small solder fillet may
cause contact failure or
not hold the chip
capacitor to the P.C.
board.
5.6 Solder repair by solder iron
1. Selection of the soldering iron tip
Tip temperatures of solder iron vary by its type, P.C. board material and solder
land size. Higher temperatures may provide quicker operation; however, heat
shock may cause a crack in the chip capacitor. Please make sure the tip
temperature before soldering and keep the peak temperature and time in
accordance with following recommended condition. (Please preheat the chip
capacitors with the condition in 5.4 to avoid the thermal shock.)
Recommended solder iron condition (Sn-Pb Solder and Lead Free Solder)
Temp. (°C) Duration (sec.) Wattage (W) Shape (mm)
300 max. 3 max. 20 max. Ø 3.0 max.
5 Soldering
(continued)
Maximum amount
Minimum amoun
t
18 of 27
(9. Caution, continued)
No. Process Condition
2.
Direct contact of the soldering iron with ceramic dielectric of the chip capacitor
may cause cracking. Do not touch the ceramic dielectric and the terminations
by solder iron.
5 Soldering
(continued)
5.7 Sn-Zn solder
Sn-Zn solder affects product reliability.
Please contact TDK in advance when utilize Sn-Zn solder.
5.8 Countermeasure for tombstone
The misalignment between the mounted positions of the capacitors and the land
patterns should be minimized. The tombstone phenomenon may occur especially
when the capacitors are mounted (in longitudinal direction) in the same direction of
the reflow soldering. (Refer to JEITA RCR-2335B Annex 1 “Recommendations to
prevent the tombstone phenomenon”.)
1.
2.
If an unsuitable cleaning fluid is used, flux residue or some foreign articles may
stick to the chip capacitor surface and to deteriorate insulation resistance.
If cleaning condition is not suitable, it may deteriorate the chip capacitor.
2.1 Insufficient washing
1.
2.
3.
Terminal electrodes may be corroded by Halogen in the flux.
Halogen in the flux may adhere on the surface of capacitor, and lower the
insulation resistance.
Water soluble flux has higher tendency to have above mentioned
problems (1) and (2).
2.2 Excessive washing
When ultrasonic cleaning is used, excessively high energy output can affect
the connection between the ceramic chip capacitor's body and the terminal
electrode. To avoid this, the following is recommended.
Power: 20 W/ ℓ max.
Frequency: 40 kHz max.
Washing time: 5 minutes max.
6 Cleaning
2.3 If the cleaning fluid is contaminated, concentration of Halogen can increase, and it
may bring the same result as insufficient cleaning.
19 of 27
(9. Caution, continued)
No. Process Condition
7 Coating and
molding of the
P. C . B o a r d
1.
2.
3.
When the P.C. board is coated, please verify the impact on the capacitor.
Please carefully verify that there is no harmful decomposing or reaction gas
emission during curing which may damage the chip capacitor.
Please verify the curing temperature.
1.
Please pay attention not to bend or distort the P.C. board after soldering otherwise
the chip capacitor may crack.
Bend Twist
2. When functional check of the P.C. board is performed, high pin pressure tends
to be used to avoid poor contact. But if the pressure is excessive and bends the
P.C. board, it may crack the chip capacitor or peel the termination. Please
adjust the check pins accordingly to ensure the P.C. board is not flexed.
Item Not recommended Recommended
Board
bending
8 Handling after
chip mounted
Check pin
Termination
peeling
Support pin
Check pin
20 of 27
(9. Caution, continued)
No. Process Condition
9 Handling of loose
chip capacitors
1. The chip capacitor may crack if dropped, especially large case sizes. Please
handle with care and do not use if dropped.
2. When stacking the P.C. board for storage or handling after soldering, the corner of
the P.C. board may hit the chip capacitor of a neighboring board to cause a crack.
10 Capacitance aging
Class 2 capacitors have an aging characteristic, which is a decrease in capacitance
over time due to crystalline changes that occur I ferroelectric ceramics. Careful
consideration should be done in case of the time constant circuit.
11 Estimated life and
estimated failure
rate of capacitors
The estimated life and (failure rate) depend on the temperature and voltage applied.
This can be calculated by the equation described in JEITA RCR-2335B Annex
6 ”Calculation of the estimated lifetime and the failure rate.” The risk can be
decreased by reducing the temperature and the voltage but the failure rate can not be
guaranteed.
12 Others
The products listed on this specification sheet are intended for use in general
electronic equipment (AV equipment, telecommunications equipment, home
appliances, amusement equipment, computer equipment, personal equipment, office
equipment, measurement equipment, industrial robots) under a normal operation and
use condition.
The products are not designed or warranted to meet the requirements of the
applications listed below, whose performance and/or quality require a more stringent
level of safety or reliability, or whose failure, malfunction or trouble could cause
serious damage to society, person or property. Please understand that TDK is not
responsible for any damage or liability caused by use of this product in any of the
applications below or for any other use exceeding the range or conditions set forth in
this specification sheet:
Aerospace/Aviation equipment. Transportation equipment (cars, electric trains, ships,
etc.) Medical equipment. Power-generation control equipment. Atomic energy-related
equipment. Seabed equipment. Transportation control equipment.
Public information-processing equipment. Military equipment. Electric heating
apparatus, burning equipment. Disaster prevention/crime prevention equipment.
Safety equipment. Other applications that are not considered general-purpose
applications.
When using this product in general-purpose applications, you are kindly requested to
take into consideration securing protection circuit/equipment or providing backup
circuits, etc., to ensure higher safety.
Crack
Floor
P. C . B o a r d
Crack
21 of 27
10. Packaging label
Packaging shall be done to protect the components from the damage during
transportation and storing, and a label which has the following information shall be
attached.
1) Inspection No.
2) TDK P/N
3) Customer's P/N
4) Quantity
*Composition of Inspection No.
Example M 0 A – ΟΟ – ΟΟΟ
(a) (b) (c) (d) (e)
a) Line code
b) Last digit of the year
c) Month and A for January and B for February and so on. (Skip I)
d) Inspection Date of the month.
e) Serial No. of the day
11. Bulk packaging quantity
Total number of components in a plastic bag for bulk packaging: 1,000pcs.
22 of 27
12. TAPE PACKAGING SPECIFICATION
1. CONSTRUCTION AND DIMENSION OF TAPING
1. Dimensions of carrier tape
Dimensions of paper tape shall be according to Appendix 7, 8.
Dimensions of plastic tape shall be according to Appendix 9
2. Bulk part and leader of taping
3. Dimensions of reel
Dimensions of Ø178 reel shall be according to Appendix 10
Dimensions of Ø330 reel shall be according to Appendix 11.
4. Structure of taping
2. CHIP QUANTITY
Chip quantity (pcs.)
Type Thickness
of chip
Taping
Material φ178mm reel φ330mm reel
CKD710JB 0.30 mm Paper 10,000 50,000
CKD610JB 0.80 mm Paper 4,000 10,000
CKD510JB 0.85 mm Paper 4,000 10,000
CKD110JB 0.85 mm Paper 4,000 10,000
CKD310JB 1.60mm MAX. Plastic 2,000 10,000
Drawing direction Leader
400mm min.
Bulk
160mm min.
Chi
p
sBulk
160mm min.
Paper carrier tape
To
p
cover ta
p
e
Pitch hole
Pa
p
er carrier ta
p
e
Pitch hole
To
p
cover ta
p
e
Bottom cover tape
23 of 27
3. PERFORMANCE SPECIFICATIONS
3-1. Peel back cover (top tape)
0.05-0.7N. (See the following figure.)
3-2. Carrier tape shall be flexible enough to be wound around a minimum radius
of 30mm with components in tape.
3-3. The missing of components shall be less than 0.1%
3-4. Components shall not stick to the cover tape.
3-5. The cover tapes shall not protrude beyond the edges of the carrier tape
not shall cover the sprocket holes.
0~15°
Carrier tape
Top cover tape
Direction of pulling
Direction of cover tape pulling
24 of 27
Appendix 7
Paper Tape
（Unit：mm）
Symbol
Type A B C D E F
CKD710JB (0.65) (1.15) 8.00±0.30 3.50±0.05 1.75±0.10 2.00±0.05
Symbol
Type G H J T
CKD710JB 2.00±0.05 4.00±0.10 Ø 1.5 +0.10
0 0.60±0.05
* The values in the parentheses ( ) are for reference.
Appendix 8
Paper Tape
(Unit: mm)
Symbol
Type A B C D E F
CKD610JB ( 1.10 ) ( 1.90 )
CKD510JB ( 1.50 ) ( 2.30 )
CKD110JB ( 1.65 ) ( 3.50 )
8.00 ± 0.30 3.50 ± 0.05 1.75 ± 0.10 4.00 ± 0.10
Symbol
Type G H J T
CKD610JB
CKD510JB
CKD110JB
2.00 ± 0.05 4.00 ± 0.10 Ø 1.5 +0.10
0 1.10 max.
.
* The values in the parentheses ( ) are for reference.
A
J
Pitch hole
HGF
E
D C
B
T
A
J
Pitch hole
HGF
B
E
D C
T
25 of 27
Appendix 9
Plastic Tape
(Unit: mm)
Symbol
Type A B C D E F
CKD310JB ( 1.90 ) ( 3.50 ) 8.00 ± 0.30 3.50 ± 0.05 1.75 ± 0.10 4.00 ± 0.10
Symbol
Type G H J K t Q
CKD310JB 2.00 ± 0.05 4.00 ± 0.10 Ø 1.5 +0.10
0 2.50 max. 0.30 max. Ø 0.50 min.
* The values in the parentheses ( ) are for reference.
t
K
HGF
A
C
E
D
Pitch hole J
B
Q
26 of 27
Appendix 10
(Material: Polystyrene)
(Unit: mm)
Symbol A B C D E W1
Dimension Ø178 ± 2.0 Ø60 ± 2.0 Ø13 ± 0.5 Ø21 ± 0.8 2.0 ± 0.5 9.0 ± 0.3
Symbol W2 r
Dimension 13.0 ± 1.4 1.0
Appendix 11
(Material: Polystyrene)
(Unit: mm)
Symbol A B C D E W
Dimension
Ø382 max.
(Nominal
Ø330)
Ø50 min. Ø13 ± 0.5 Ø21 ± 0.8 2.0 ± 0.5 10.0 ± 1.5
Symbol t r
Dimension 2.0 ± 0.5 1.0
B
W1
A
E
C
D
r
W2
B
W
A
EC
D
r
t
27 of 27
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