SPECIFICATION SPEC. No. DATE Customer CUSTOMER'S PRODUCT NAME TDK PRODUCT NAME MULTILAYER CERAMIC CHIP CAPACITORS CKD710JB, CKD610JB, CKD510JB, CKD110JB, CKD310JB Type(Low ESL Feed Trough) Please sign return this specification to TDK representatives. If orders are placed without this returned documentation, we must consider you found the specification acceptable. THIS SPECIFICATION IS RECEIVED DATE: YEAR MONTH DAY TDK-EPC Corporation 1-13-1, Nihonbashi, Chuo-ku, Tokyo 103-0027, Japan ENGINEERING ISSUED CHECKED APPROVED DATE DATE DATE Sales Office Sales Tel. PRODUCT CLASSIFICATION CODE 040320 REV 0.3 / 201012 1. SCOPE This specification is applicable to chip type multilayer ceramic capacitors with a priority over other relevant specifications. Production places defined in this specification shall be TDK-EPC Corporation Japan, TDK-EPC HONG KONG LIMITED, TDK (Suzhou) Co., Ltd, TDK (Malaysia) Sdn. Bhd and TDK Components U.S.A. Inc. EXPLANATORY NOTE: This specification warrants the quality of the TDK ceramic chip capacitor. The product should be evaluated and confirmed in your product before use. If the use of the product exceeds the bounds of the specification, we can not guarantee its quality and/or reliability. 2. CODE CONSTRUCTION (Example) CKD610JB (1) 0J (2) 225 (3) L B S (4) T (5) 1. Type Terminal electrode W C B T Internal electrode Ceramic dielectric Please refer to product list for the dimension of each product. material. See Section 8 for inside structure and 1 of 27 2. Rated Voltage Symbol Rated Voltage 1H 50 V DC 1E 25 V DC 1C 16 V DC 1A 10 V DC 0J 6.3 V DC 3. Rated Capacitance Stated in three digits and in units of pico farads (pF).The first and second digits identify the first and second significant figure of the capacitance, the third digit identifies the multiplier. R is designated for a decimal point. Example 225 2,200,000pF 4. Capacitance tolerance See the cap range chart In the TDK Product Guide for this series to obtain item specific parameters. 5. Packaging Symbol Tolerance S + 50, -20 % M 20 % Symbol Packaging B Bulk T Taping 3. RATED CURRENT DC2A DC1A DC500mA DC400mA DC200mA See the cap range chart In the TDK Product Guide for this series to obtain item specific parameters. 4. OPERATING TEMPERATURE RANGE -25 85C -55 85C -55 125C See the cap range chart In the TDK Product Guide for this series to obtain item specific parameters 5. STORING CONDITION AND TERM 5 to 40C at 20 to 70%RH 6 months Max. 6. INDUSTRIAL WASTE DISPOSAL Dispose this product as industrial waste in accordance with the local Industrial Waste Laws. 2 of 27 7. PERFORMANCE No. Item 1 External Appearance No defects which may affect performance. Performance Inspect with magnifying glass (3X) Test or inspection method 2 Insulation Resistance 10,000M or 500M*F min. whichever smaller (As for the capacitors of rated voltage 16, 10, 6.3V DC, 100M*F min.). Apply rated voltage for 60s. 3 Direct Current Resistance Rdc (1-2) Measuring current should be 100mA max. Rdc is between 5M - 600 M depending on item. See the cap range chart in the TDK Product Guide for this series to obtain item specific parameters. 3 1 2 4 4 Voltage Proof Withstand test voltage without insulation breakdown or other damage. 5 Capacitance Within the specified capacitance tolerance. 2.5 times of rated voltage. Above DC voltage shall be applied for 1 to 5s. Charge / discharge current shall not exceed 50mA. Measuring frequency 1kHz10% 6 Dissipation Factor (DF) Max. DF= 0.10 Measuring voltage 0.50.2Vrms. 1.00.2Vrms. See No.5 in this table for measuring condition. 3 of 27 (7. Performance, continued) No. 7 Item Performance No mechanical damage. Bending Test or inspection method Reflow solder the capacitor on P.C. board (shown in Appendix 2, Appendix 4 or Appendix 6) and bend 1mm. 20 50 F R230 45 1 45 (Unit: mm) 8 Solderability New solder to cover over 75% of termination. 25% may have pin holes or rough spots but not concentrated in one spot. Ceramic surface of "A sections" shall not be exposed due to melting or shifting of termination material. Completely soak both terminations in solder at 2355C for 20.5s. Solder: H63A (JIS Z 3282) Flux: Isopropyl alcohol (JIS K 8839) Rosin(JIS K 5902) 25% solid solution. A section 9 Resistance to solder heat External appearance No mechanical damage. Capacitance Change from the value before test 7.5 % Preheating condition Temp.: 15010C Time: 1 to 2min. Flux: Isopropyl alcohol (JIS K 8839) Rosin (JIS K 5902) 25% solid solution. Solder: H63A (JIS Z 3282) D.F. Meet the initial spec. Insulation Resistance Meet the initial spec. Voltage proof No insulation breakdown or other damage. Resistance for DC Rdc Completely soak both terminations in solder at 2605C for 51s. Leave the capacitor in ambient conditions for 242h before measurement. 1.0 max. 4 of 27 (7. Performance, continued) No. Item 10 Temperature External cycle appearance Performance No mechanical damage. Capacitance Change from the value before test 7.5 % D.F. Meet the initial spec. Insulation 11 Moisture Resistance Meet the initial spec. Resistance for DC Rdc 1.0 max. External Resistance appearance (Steady Capacitance State) No mechanical damage. Test or inspection method Reflow solder the capacitor on P.C. board (shown in Appendix 1 or Appendix 3) before testing. Expose the capacitor in the conditions step1 through step 4 and repeat 5 times consecutively. Leave the capacitor in ambient conditions for 242h before measurement. Step Temperature(C) Time (min.) 1 Min. operating temp. 3 30 3 2 20 2 2-5 3 Max. operating temp. 2 30 2 4 20 2 2-5 Reflow solder the capacitors on P.C. board (shown in Appendix 1 or Appendix 3) before testing. Change from the value before test 12.5 % D.F. Characteristics 200% of initial spec. max. Insulation Resistance 1,000M or 50M*F min. whichever smaller. (As for the capacitors of rated voltage 16, 10, 6.3V DC, 10M*F min.,) Resistance for DC Rdc 1.0 max. Leave at temperature 402C, 90 to 95%RH for 500 +24,0h. Leave the capacitor in ambient conditions for 242h before measurement. 5 of 27 (7. Performed, continued) No. 12 Item Life External appearance Performance No mechanical damage. Capacitance Test or inspection method Reflow solder the capacitor on P.C. board (shown in Appendix 1, Appendix 3 or Appendix 5) before testing. Change from the value before test 15 % D.F. Characteristics 200% of initial spec. max. Insulation 1,000M or 50M*F min. Resistance whichever smaller. (As for the capacitors of rated voltage 16, 10, 6.3V DC, 10M*F min.,) Resistance for DC Rdc 1.0 max. Below the voltage shall be applied at maximum operating temperature 2C for 1,000 +48, 0h. Applied voltage is 1xRV; however some items may be tested at higher voltage (1.2x, 1.5x or 2xRV). Contact TDK for details. Charge/discharge current shall not exceed 50mA. Leave the capacitor in ambient conditions for 242h before measurement. Voltage conditioning: Voltage treats the capacitor under testing temperature and voltage for 1 hour. Leave the capacitor in ambient conditions for 242h before measurement. Use this measurement for initial value. *As for the initial measurement of capacitors on number 9, 10 and 11, leave capacitors at 150 -10, 0C for 1 hour and measure the value after leaving capacitors for 242h in ambient condition. 6 of 27 Appendix - 1 Appendix - 2 P.C. Board for reliability test P.C. Board for bending test 100 4 40 100 Solder resist Copper Copper Solder resist (Unit: mm) (Unit: mm) c f d e f b a b Dimensions (mm) TDK (EIA style) CKD710JB a b c d e f 0.7 0.3 0.19 0.6 0.25 0.25 1. Material: Glass Epoxy (As per JIS C6484 GE4) 2.Thickness1.6mm Copper(Thickness 0.035mm) Solder resist 7 of 27 Appendix - 3 Appendix - 4 P.C. Board for reliability test P.C. Board for bending test 100 40 40 100 Copper Solder resist (Unit: mm) (Unit: mm) c c c f d d b a e f b b a b Appendix - 3 Dimensions (mm) TDK (EIA style) CKD610JB a b c d e f 1.0 0.6 0.4 0.6 0.4 0.4 Appendix - 4 Dimensions (mm) TDK (EIA style) CKD610JB a b c d 0.4 0.5 0.4 2.0 1. Material: Glass Epoxy (As per JIS C6484 GE4) 2.Thickness1.6mm Copper(Thickness 0.035mm) Solder resist 8 of 27 Appendix - 5 Appendix - 6 P.C. Board for reliability test P.C. Board for bending test 100 40 40 100 Copper Solder resist (Unit: mm) (Unit: mm) c f e d f b a b Dimensions (mm) TDK (EIA style) a b c d e f CKD510JB 1.4 0.6 0.5 0.8 0.6 0.65 CKD110JB 2.5 0.7 1.4 1.0 0.6 0.7 CKD310JB 2.5 1.2 1.4 1.3 0.8 0.9 1. Material: Glass Epoxy (As per JIS C6484 GE4) 2.Thickness1.6mm Copper(Thickness 0.035mm) Solder resist 9 of 27 8. INSIDE STRUCTURE AND MATERIAL B' A A' B A-A' B-B' 3 3 4 4 5 1 2 No. NAME MATERIAL 1 Dielectric CaZrO 3 or BaTiO 3 2 Electrode Nickel (Ni) 3 4 5 5 Copper (Cu) Termination Nickel (Ni) Tin (Sn) 10 of 27 9. Caution No. 1 Process Operating Condition (Storage, Transportation) Condition 1.1 Storage 1. The capacitor must be stored in an ambient temperature of 5 to 40C with a relative humidity of 20 to 70%RH. The product should be used within 6 months upon receipt. 2. The capacitors must be operated and stored in an environment free of condensation and corrosive gases such as hydrogen sulphide, hydrogen sulphate, chlorine, ammonia and sulfur. 3. Avoid storing in sun light and falling of dew. 4. Do not use capacitor under high humidity and high/low atmospheric pressure which may compromise product reliability. 2 Circuit design 5. Capacitors should be tested for the solderability when they are stored for long periods of time. 1.2 Handling in transportation In case of the transportation the performance of the capacitor may be deteriorated depending on the transportation condition. (Refer to JEITA RCR-2335B 9.2 "Handling in Transportation") 2.1 Operating temperature Operating temperature should be followed strictly within this specification, especially be careful with maximum temperature. 1. Do not use capacitors above the maximum allowable operating temperature. 2. Surface temperature including self heating should be below maximum operating temperature. (Due to dielectric loss, capacitors will heat itself when AC is applied. Especially at high frequencies around its SRF, the heat might be so extreme that it may damage itself or the product its mounted on. Please design the circuit so that the maximum temperature of the capacitors (including the self heating) will be below the maximum allowable operating temperature. Temperature rise at capacitor surface shall be below 20C) 3. The electrical characteristics of the capacitors will vary depending on the temperature. The capacitors should be selected and designed after taking the temperature into consideration. 2.2 Operating voltage 1. Operating voltage across the terminals should be below the rated voltage. When AC and DC are super imposed, V0-P must be below the rated voltage. Reference figures 1 and 2 below. AC or pulse with overshooting, VP-P must be below the rated voltage. Reference: figures 3, 4, and 5 below. When the voltage is started/ stopped to apply to the circuit an irregular voltage may be generated for a transit period because of resonance or switching. Be sure to use the capacitor within its rated voltage during these Irregular voltage periods. Voltage (1) DC voltage (2) DC+AC voltage (3) AC voltage Positional Measurement V0-P (Rated voltage) 0 Voltage V0-P VP-P 0 0 (4) Pulse voltage (A) (5) Pulse voltage (B) Positional Measurement VP-P (Rated voltage) 0 VP-P 0 11 of 27 (9. Caution, continued) No. 2 Process Circuit design Condition 2.2 Operating Voltage (continued) 2. Even below the rated voltage, if repetitive high AC frequency or pulsed voltage is applied, the reliability of the capacitors may be reduced. 3. The effective capacitance will vary depending on applied DC and AC voltages. The capacitors should be selected after considering the voltage affect. 2.3 Frequency When Class 2 capacitors are used in AC and/or pulse voltages, the capacitors may self vibrate and generate audible sound (piezoelectric affect). 3 Designing P.C. Board The amount of solder at the terminations directly impacts the reliability of the capacitor. 1. The greater the amount of solder, the higher the stress on the chip capacitor, and the more likely that it will break. When designing a P.C. board, determine the shape and size of the solder lands to ensure the proper amount of solder is applied to the terminations. 2. Avoid using common solder land for multiple terminations and provide individual solder land for each termination instead. 3. Size and recommended land dimensions provided below: <CKD710JB> Chip mounted size Back side: Back side shall be connected to the Through hole ground pattern of the chip mounted 0.40.6 side. Please design the back side ground as large as possible. Connect to the ground pattern of the chip mounted side. d e Ground pattern *If thorough hole is too large, solder paste may come into the hole and make bad connection with the ground pattern. a b c Resist Cu pattern No pattern (mm) Type Symbol CKD710JB a b c d e 0.19 0.7 1.3 0.6 0.75 12 of 27 (9. Caution, continued) No. Process 3 Designing P.C. Board Condition <CKD610JB> Chip mounted size Through hole O0.4-0.6 Connect to the ground pattern of the chip mounted side. "Through hole" should be designed as close to GND terminal as possible. d e a b c Resist Cu pattern No pattern (mm) Type Symbol CKD610JB a b c d e 0.4 1.2 2. 2 0.7 1.4 <CKD510JB, CKD110JB, CKD310JB> Chip mounted size Back side: Back side shall be connected to the ground pattern of the chip mounted side. Please design the back side ground as large as possible. Through hole O0.4-0.6 Connect to the ground pattern of the chip mounted side. d e Ground pattern a b c Resist *If through hole is too big, solder paste may come into the hole and make bad connection with the ground pattern. Cu pattern No pattern (mm) Type a b c d e CKD510JB 0.5 1. 5 2.6 1.0 2.0 CKD110JB 1.4 2. 5 4.5 1.0 2.0 CKD310JB 1.4 2. 5 4.5 1.2 2.4 Symbol 13 of 27 (9. Caution, continued) No. Process Designing Condition 4. Recommended chip capacitor layout is provided below: P.C. Board (continued) Disadvantage against bending stress Perforation or slit Advantage against bending stress Perforation or slit Mounting face Break P.C. board with mounted side up. Break P.C. board with mounted side down. Mount perpendicularly to perforation or slit Mount in parallel with perforation or slit Perforation or slit Perforation or slit Chip arrangement (Direction) Closer to slit is higher stress Away from slit is less stress 2 1 Distance from slit ( 1 < 2 ) ( 1 < 2 ) 14 of 27 (9. Caution, continued) No. 3 Process Designing P.C. Board (continued) Condition 5. Mechanical stress varies according to location of chip capacitor on the P.C. board. E Perforation D C B A Slit The relative stress applied to these capacitors during depaneling is in the following order: A>B=C>D>E 4 Mounting 4.1 Stress from mounting head If the mounting head is adjusted too low, it may induce excessive stress on the chip capacitor and to result in cracking. Please take following precautions. 1. Adjust the bottom dead center of the mounting head to reach the P.C. board surface but do not contact it. 2. Adjust the mounting head pressure to be 1 to 3N of static weight. 3. To minimize the impact energy from mounting head, it is important to provide support from the bottom side of the P.C. board. See following examples. Not recommended Single sided mounting Recommended Crack Support Double-sides mounting Solder peeling Crack Support When the centering jaw is worn, mechanical impact on the capacitor may occur and damage the product. Please control the closing dimension of the centering jaw and provide sufficient preventive maintenance and/or replacement if necessary. 15 of 27 (9. Caution, continued) Soldering Condition 5.1 Flux selection Although highly-activated flux gives better solderability, substances which increase activity may also degrade the insulation of the chip capacitor. To avoid such degradation, the following is recommended. 1. Use a mildly activated rosin flux (less than 0.1wt% chlorine). 2. Excessive flux must be avoided. Please provide proper amount of flux. 3. When water-soluble flux is used, sufficient washing is necessary. 5.2 Recommended soldering profile by various methods Reflow soldering Soldering Natural cooling Preheating Peak Temp Temp.. (C) 5 Process T 0 Over 60 sec. Peak Temp time Manual soldering (Solder iron) 300 Temp.. (C) No. T Preheating 0 3sec. (As short as possible) 5.3 Recommended soldering peak temp and duration Temp./Duration Solder Reflow soldering Peak temp(C) Duration(sec.) Sn-Pb Solder 230 max. 20 max. Lead Free Solder 260 max. 10 max. Recommended solder compositions Sn-37Pb (Sn-Pb solder) Sn-3.0Ag-0.5Cu (Lead Free Solder) 16 of 27 (9. Caution, continued) No. 5 Process Soldering (continued) Condition 5.4 Avoiding thermal shock 1. Preheating condition 2. Soldering Temp. (C) Reflow soldering T 150 Manual soldering T 150 Cooling condition Natural cooling using air is recommended. If the chips are dipped into a solvent for cleaning, the temperature difference (T) must be less than 100C. 5.5 Amount of solder Excessive solder will induce higher tensile force on the chip capacitor during temperature changes and may result in chip cracking. Insufficient solder may detach the capacitor from the P.C. board. Higher tensile force on the chip capacitor may cause cracking. Excessive solder Maximum amount Minimum amount Adequate Small solder fillet may cause contact failure or not hold the chip capacitor to the P.C. board. Insufficient solder 5.6 Solder repair by solder iron 1. Selection of the soldering iron tip Tip temperatures of solder iron vary by its type, P.C. board material and solder land size. Higher temperatures may provide quicker operation; however, heat shock may cause a crack in the chip capacitor. Please make sure the tip temperature before soldering and keep the peak temperature and time in accordance with following recommended condition. (Please preheat the chip capacitors with the condition in 5.4 to avoid the thermal shock.) Recommended solder iron condition (Sn-Pb Solder and Lead Free Solder) Temp. (C) Duration (sec.) Wattage (W) Shape (mm) 300 max. 3 max. 20 max. O 3.0 max. 17 of 27 (9. Caution, continued) No. 5 Process Soldering (continued) Condition 2. Direct contact of the soldering iron with ceramic dielectric of the chip capacitor may cause cracking. Do not touch the ceramic dielectric and the terminations by solder iron. 5.7 Sn-Zn solder Sn-Zn solder affects product reliability. Please contact TDK in advance when utilize Sn-Zn solder. 5.8 Countermeasure for tombstone The misalignment between the mounted positions of the capacitors and the land patterns should be minimized. The tombstone phenomenon may occur especially when the capacitors are mounted (in longitudinal direction) in the same direction of the reflow soldering. (Refer to JEITA RCR-2335B Annex 1 "Recommendations to prevent the tombstone phenomenon".) 6 Cleaning 1. If an unsuitable cleaning fluid is used, flux residue or some foreign articles may stick to the chip capacitor surface and to deteriorate insulation resistance. 2. If cleaning condition is not suitable, it may deteriorate the chip capacitor. 2.1 Insufficient washing 1. Terminal electrodes may be corroded by Halogen in the flux. 2. Halogen in the flux may adhere on the surface of capacitor, and lower the insulation resistance. 3. Water soluble flux has higher tendency to have above mentioned problems (1) and (2). 2.2 Excessive washing When ultrasonic cleaning is used, excessively high energy output can affect the connection between the ceramic chip capacitor's body and the terminal electrode. To avoid this, the following is recommended. Power: 20 W/ max. Frequency: 40 kHz max. Washing time: 5 minutes max. 2.3 If the cleaning fluid is contaminated, concentration of Halogen can increase, and it may bring the same result as insufficient cleaning. 18 of 27 (9. Caution, continued) No. Process 7 Coating and molding of the P.C. Board 8 Handling after chip mounted Condition 1. When the P.C. board is coated, please verify the impact on the capacitor. 2. Please carefully verify that there is no harmful decomposing or reaction gas emission during curing which may damage the chip capacitor. 3. Please verify the curing temperature. 1. Please pay attention not to bend or distort the P.C. board after soldering otherwise the chip capacitor may crack. Bend Twist 2. When functional check of the P.C. board is performed, high pin pressure tends to be used to avoid poor contact. But if the pressure is excessive and bends the P.C. board, it may crack the chip capacitor or peel the termination. Please adjust the check pins accordingly to ensure the P.C. board is not flexed. Item Board bending Not recommended Termination peeling Check pin Recommended Support pin Check pin 19 of 27 (9. Caution, continued) No. 9 Process Handling of loose chip capacitors Condition 1. The chip capacitor may crack if dropped, especially large case sizes. Please handle with care and do not use if dropped. Crack Floor 2. When stacking the P.C. board for storage or handling after soldering, the corner of the P.C. board may hit the chip capacitor of a neighboring board to cause a crack. P.C. Board Crack 10 Capacitance aging Class 2 capacitors have an aging characteristic, which is a decrease in capacitance over time due to crystalline changes that occur I ferroelectric ceramics. Careful consideration should be done in case of the time constant circuit. 11 Estimated life and estimated failure rate of capacitors 12 Others The estimated life and (failure rate) depend on the temperature and voltage applied. This can be calculated by the equation described in JEITA RCR-2335B Annex 6 "Calculation of the estimated lifetime and the failure rate." The risk can be decreased by reducing the temperature and the voltage but the failure rate can not be guaranteed. The products listed on this specification sheet are intended for use in general electronic equipment (AV equipment, telecommunications equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement equipment, industrial robots) under a normal operation and use condition. The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to society, person or property. Please understand that TDK is not responsible for any damage or liability caused by use of this product in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet: Aerospace/Aviation equipment. Transportation equipment (cars, electric trains, ships, etc.) Medical equipment. Power-generation control equipment. Atomic energy-related equipment. Seabed equipment. Transportation control equipment. Public information-processing equipment. Military equipment. Electric heating apparatus, burning equipment. Disaster prevention/crime prevention equipment. Safety equipment. Other applications that are not considered general-purpose applications. When using this product in general-purpose applications, you are kindly requested to take into consideration securing protection circuit/equipment or providing backup circuits, etc., to ensure higher safety. 20 of 27 10. Packaging label Packaging shall be done to protect the components from the damage during transportation and storing, and a label which has the following information shall be attached. 1) Inspection No. 2) TDK P/N 3) Customer's P/N 4) Quantity *Composition of Inspection No. Example M 0 A (a) (b) (c) - - (d) (e) a) Line code b) Last digit of the year c) Month and A for January and B for February and so on. (Skip I) d) Inspection Date of the month. e) Serial No. of the day 11. Bulk packaging quantity Total number of components in a plastic bag for bulk packaging: 1,000pcs. 21 of 27 12. TAPE PACKAGING SPECIFICATION 1. CONSTRUCTION AND DIMENSION OF TAPING 1. Dimensions of carrier tape Dimensions of paper tape shall be according to Appendix 7, 8. Dimensions of plastic tape shall be according to Appendix 9 2. Bulk part and leader of taping Bulk Bulk Chips 160mm min. 160mm min. Leader Drawing direction 400mm min. 3. Dimensions of reel Dimensions of O178 reel shall be according to Appendix 10 Dimensions of O330 reel shall be according to Appendix 11. 4. Structure of taping Top cover tape Top cover tape Pitch hole Pitch hole Bottom cover tape Paper carrier tape Paper carrier tape 2. CHIP QUANTITY Thickness of chip Taping Material CKD710JB 0.30 mm CKD610JB Type Chip quantity (pcs.) 178mm reel 330mm reel Paper 10,000 50,000 0.80 mm Paper 4,000 10,000 CKD510JB 0.85 mm Paper 4,000 10,000 CKD110JB 0.85 mm Paper 4,000 10,000 CKD310JB 1.60mm MAX. Plastic 2,000 10,000 22 of 27 3. PERFORMANCE SPECIFICATIONS 3-1. Peel back cover (top tape) 0.05-0.7N. (See the following figure.) Direction of cover tape pulling Carrier tape Top cover tape 0~15 Direction of pulling 3-2. Carrier tape shall be flexible enough to be wound around a minimum radius of 30mm with components in tape. 3-3. The missing of components shall be less than 0.1% 3-4. Components shall not stick to the cover tape. 3-5. The cover tapes shall not protrude beyond the edges of the carrier tape not shall cover the sprocket holes. 23 of 27 Appendix 7 Paper Tape Pitch hole J E A D C B H T G F Unitmm Symbol Type A B C D E F CKD710JB (0.65) (1.15) 8.000.30 3.500.05 1.750.10 2.000.05 Symbol Type G H J T CKD710JB 2.000.05 4.000.10 O 1.5 +0.10 0 0.600.05 * The values in the parentheses ( ) are for reference. Appendix 8 Paper Tape Pitch hole J E A D B H T G C F (Unit: mm) Symbol Type CKD610JB CKD510JB CKD110JB Symbol Type CKD610JB CKD510JB CKD110JB A B C D E F ( 1.10 ) ( 1.50 ) ( 1.65 ) ( 1.90 ) ( 2.30 ) ( 3.50 ) 8.00 0.30 3.50 0.05 1.75 0.10 4.00 0.10 G H J T 4.00 0.10 +0.10 O 1.5 0 2.00 0.05 . 1.10 max. * The values in the parentheses ( ) are for reference. 24 of 27 Appendix 9 Plastic Tape Pitch hole J E A D B t H K Q F G C (Unit: mm) Symbol Type A B C D E F CKD310JB ( 1.90 ) ( 3.50 ) 8.00 0.30 3.50 0.05 1.75 0.10 4.00 0.10 Symbol Type G H J K t Q CKD310JB 2.00 0.05 4.00 0.10 2.50 max. 0.30 max. O 0.50 min. O 1.5 +0.10 0 * The values in the parentheses ( ) are for reference. 25 of 27 Appendix 10 (Material: Polystyrene) E W2 C B D r W1 A (Unit: mm) Symbol A B C D E W1 Dimension O178 2.0 O60 2.0 O13 0.5 O21 0.8 2.0 0.5 9.0 0.3 Symbol W2 r Dimension 13.0 1.4 1.0 Appendix 11 (Material: Polystyrene) E C B D r t W A (Unit: mm) Symbol A B C D E W Dimension O382 max. (Nominal O330) O50 min. O13 0.5 O21 0.8 2.0 0.5 10.0 1.5 Symbol t r Dimension 2.0 0.5 1.0 26 of 27 END PAGE 27 of 27