EFR32BG1 Blue Gecko Bluetooth® Smart

SoC CSP Family Data Sheet

The Blue Gecko Bluetooth Smart family of SoCs is part of the

Wireless Gecko portfolio. Blue Gecko SoCs are ideal for enabling

energy-friendly Bluetooth Smart networking for IoT devices.

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-

options available in footprint-compatible

CSP packaging

• 12-channel Peripheral Reflex System

enabling autonomous interaction of MCU

• Autonomous Hardware Crypto Accelerator

and Random Number Generator

• Integrated 2.4 GHz balun and PA with up

to 19.5 dBm transmit power

• Integrated DC-DC with RF noise mitigation

• Human Interface Devices

• Commercial and Retail Lighting and Sensing

Timers and Triggers

Serial

I/O Ports Analog I/F

Clock Management

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon

Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).

The EFR32BG1 highlighted features are listed below.

RTCC running from LFXO)

pattern detection, frame detection and timeout

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

• 8 Channel DMA Controller

• 12 Channel Peripheral Reflex System (PRS)

• 2×16-bit Timer/Counter

• 3 + 4 Compare/Capture/PWM channels

• 32-bit Real Time Counter and Calendar

• 16-bit Low Energy Timer for waveform generation

• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up

• 16-bit Pulse Counter with asynchronous operation

• Watchdog Timer with dedicated RC oscillator @ 50nA

VSS

Networks section.

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

The EFR32BG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is

used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly

generate the modulated RF carrier.

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with

low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to

optimize system energy consumption.

tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received

frame and the dynamic RSSI measurement can be monitored throughout reception.

The EFR32BG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-

ing a subsystem of the EFR32BG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.

The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing

true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.

RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-

sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by

enabling normal RF reception.

Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

EFR32BG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-

• Multiple CRC values can be embedded in a single frame

• 8, 16, 24 or 32-bit CRC value

• Configurable CRC bit and byte ordering

• Selectable bit-ordering (least significant or most significant bit first)

• Optional data whitening

• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding

• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing

• Optional symbol interleaving, typically used in combination with FEC

• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware

• UART encoding over air, with start and stop bit insertion / removal

• Data observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable data output bitrate / baudrate

• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

The EFR32BG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG1. It performs the following tasks:

• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry

• Run-time calibration of receiver, transmitter and frequency synthesizer

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

The EFR32BG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a

single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can

be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.

AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB

components, supplying up to a total of 200 mA.

blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple

supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen

below a chosen threshold.

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation

of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,

short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

grouped by X/Y pairs.

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet

Test conditions: LDCDC=4.7 µH (Murata LQH3NPN4R7MM0L), CDCDC=1.0 µF (Murata GRM188R71A105KA61D), VDCDC_I=3.3 V,

Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50

Low noise (LN) mode, 1.8 V out-

put, IDCDC_LOAD = 100 mA, or

Low power (LP) mode, 1.8 V out-

put, IDCDC_LOAD = 10 mA

Low noise (LN) mode, 1.8 V out-

put, IDCDC_LOAD = 200 mA

output, IDCDC_LOAD ≤ 75 μA

Low power (LP) mode,

output, IDCDC_LOAD ≤ 10 mA

Steady-state output ripple VRRadio disabled. — 3 — mVpp

Output voltage under/over-

1), Load changes between 0 mA

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC

output. TOP = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process

Active mode with all periph-

erals disabled, DCDC in Low

Noise CCM mode3.

while loop from flash2

38 MHz HFRCO, CPU running

Prime from flash

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

38 MHz HFRCO — 32 — μA/MHz

26 MHz HFRCO — 38 — μA/MHz

Current consumption in EM1

Sleep mode with all peripher-

als disabled, DCDC in Low

Noise CCM mode3.

38.4 MHz crystal2— 61 — μA/MHz

38 MHz HFRCO — 45 — μA/MHz

26 MHz HFRCO — 58 — μA/MHz

Current consumption in EM2

Current consumption in

EM4H Hibernate mode

running from LFXO

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

128 byte RAM retention, no RTCC — 0.58 — μA

EM4S Shutoff mode

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. TOP = 25 °C.

while loop from flash

26 MHz HFRCO — 37 — μA/MHz

1 MHz HFRCO — 154 — μA/MHz

Current consumption in EM2

Deep Sleep mode

running from LFXO

4 kB RAM retention and RTCC

running from LFRCO

Current consumption in EM3

Stop mode

TIMER running from ULFRCO

Current consumption in

EM4H Hibernate mode

running from LFXO

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. TOP = 25 °C.

See Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 or

38.4 MHz, peripheral clocks

Current consumption in

transmit mode (MCU in EM1

@ 38.4 MHz, peripheral

clocks disabled)

power, Radio clock prescaled by 3

F = 2.4 GHz, CW, 3 dBm output

put power, PAVDD connected di-

rectly to external 3.3V supply

F = 2.4 GHz, CW, 19.5 dBm out-

put power, PAVDD connected di-

rectly to external 3.3V supply

RFSENSE current consump-

Wake up from EM2 Deep

Wake up from EM3 Stop tEM3_WU Executing from flash — 10.7 — μs

Executing from RAM — 3 — μs

Wake up from EM4H Hiber-

Wake up from EM4S Shut-

AVDD BOD threshold VAVDDBOD AVDD rising — — 1.85 V

AVDD falling 1.62 — — V

AVDD BOD hysteresis VAVDDBOD_HYST — 21 — mV

AVDD response time tAVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs

EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V

AVDD falling 1.45 — — V

EM4 BOD hysteresis VEM4BOD_HYST — 46 — mV

EM4 response time tEM4BOD_DELAY Supply drops at 0.1V/μs rate — 300 — μs

RF Synthesizer Frequency

LO tuning frequency resolu-

tion with 38.4 MHz crystal

ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.

Maximum TX power1POUTMAX 19.5 dBm-rated part numbers.

PAVDD connected directly to ex-

ternal 3.3V supply2

10.5 dBm-rated part numbers — 10.5 — dBm

0 dBm-rated part numbers — 0 — dBm

Minimum active TX Power POUTMIN CW -30 — dBm

ternal supply, for output power >

10.5 dBm.

1.85 V < VVREGVDD < 3.3 V,

PAVDD connected directly to ex-

ternal supply, for output power =

10.5 dBm.

1.85 V < VVREGVDD < 3.3 V using

DC-DC converter

Output power variation vs

temperature at POUTMAX

nected to DC-DC output

band in restricted bands

supply, Test Frequency =

2450 MHz

GHz; continuous transmission of

modulated carrier4

Spurious emissions out-of-

band in restricted bands

(88-216 MHz), per FCC part

15.205/15.209, Emissions

taken at Pout_Max power

level of 19.5 dBm, PAVDD

part 15.205/15.209, Emis-

sions taken at Pout_Max

power level of 19.5 dBm,

PAVDD connected to exter-

nal 3.3 V supply, Test Fre-

quency = 2450 MHz

Spurious emissions out-of-

band in restricted bands

(>960 MHz), per FCC part

15.205/15.209, Emissions

band in non-restricted bands

per FCC Part 15.247, Emis-

sions taken at Pout_Max

power level of 19.5 dBm,

PAVDD connected to exter-

nal 3.3 V supply, Test Fre-

quency = 2450 MHz

GHz; continuous transmission of

modulated carrier

Spurious emissions out-of-

band; per ETSI 300.3285

174-230 MHz, 470-862 MHz

25-1000 MHz, excluding above

Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD

and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to Figure

5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure

5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.

Max usable receiver input

length is 20 octets.

Co-channel interferer rejec-

tion, 1% PER

tivity limit

High-side adjacent channel

rejection, 1% PER. Desired

is reference signal at 3dB

above reference sensitivity

Interferer is filtered reference sig-

Interferer is CW at +1 channel-

Interferer is filtered reference sig-

Interferer is CW at -1 channel-

Alternate channel rejection,

1% PER. Desired is refer-

ence signal at 3dB above

reference sensitivity level3

Interferer is filtered reference sig-

range over which RSSI reso-

Lower limit of input power

range over which RSSI reso-

RSSI resolution RSSIRES over RSSIMIN to RSSIMAX — 0.25 — dB

Crystal Frequency fHFXO 38 38.4 40 MHz

Frequency Accuracy fHFRCO_ACC Any frequency band, across sup-

Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns

Step size SSHFRCO Coarse (% of period) — 0.8 — %

Fine (% of period) — 0.1 — %

Period Jitter PJHFRCO — 0.2 — % RMS

Flash erase cycles before

Flash data retention RETFLASH 10 — — years

Word (32-bit) programming

Page erase time tPERASE 20 27 40 ms

Mass erase time tMERASE 20 27 40 ms

Device erase time2tDERASE — 60 74 ms

Page erase current3IERASE — — 3 mA

Mass or Device erase cur-

Input low voltage VIOIL — — IOVDD*0.3 V

Output high voltage relative

to IOVDD

Sourcing 1.2 mA, IOVDD ≥ 1.62

Sourcing 20 mA, IOVDD ≥ 3 V,

Sinking 20 mA, IOVDD ≥ 3 V,

Sinking 8 mA, IOVDD ≥ 1.62 V,

Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO

≤ IOVDD

LFXO Pins, GPIO ≤ IOVDD — 0.1 50 nA

Input leakage current on

5VTOL pads above IOVDD

to 30% of VIO

to 70% of VIO

SLEWRATE = 0x61

VMON Supply Current IVMON In EM0 or EM1, 1 supply moni-

In EM0 or EM1, 4 supplies moni-

In EM2, EM3 or EM4, 1 supply

In EM2, EM3 or EM4, 4 supplies

VMON Loading of Monitored