Products and specifications discussed herein are subject to change by Aptina without notice.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Features
PDF: 0185865399/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev.J 5/10 EN 1©2004 Aptina Imaging Corporation All rights reserved.
1/2-Inch Megapixel CMOS Digital Image Sensor
MT9M001C12STM (Monochrome)
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
Features
•Aptina
® DigitalClarity™ CMOS imaging technology
• Array Format (5:4): 1,280H x 1,024V (1,310,720 active
pixels). Total (incl. dark pixels): 1,312H x 1,048V
(1,374,976 pixels)
• Frame Rate: 30 fps progressive scan; programmable
• Shutter: Electronic Rolling Shutter (ERS)
• Window Size: SXGA; programmable to any smaller
format (VGA, QVGA, CIF, QCIF, etc.)
• Programmable Controls: Gain, frame rate, frame size
Applications
• Digital still cameras
• Digital video cameras
•PC cameras
General Description
The Aptina® Imaging MT9M001 is an SXGA-format
with a 1/2-inch CMOS active-pixel digital image sen-
sor. The active imaging pixel array of 1,280H x 1,024V. It
incorporates sophisticated camera functions on-chip
such as windowing, column and row skip mode, and
snapshot mode. It is programmable through a simple
two-wire serial interface.
This megapixel CMOS image sensor features Digital-
Clarity—Aptina’s breakthrough low-noise CMOS imag-
ing technology that achieves CCD image quality
(based on signal-to-noise ratio and low-light sensitiv-
ity) while maintaining the inherent size, cost, and inte-
gration advantages of CMOS.
Table 1: Key Performance Parameters
The sensor can be operated in its default mode or pro-
grammed by the user for frame size, exposure, gain set-
ting, and other parameters. The default mode outputs
an SXGA-size image at 30 frames per second (fps). An
on-chip analog-to-digital converter (ADC) provides 10
bits per pixel. FRAME_VALID and LINE_VALID signals
are output on dedicated pins, along with a pixel clock
that is synchronous with valid data.
Ordering Information
Parameter Value
Optical format 1/2-inch (5:4)
Active imager size 6.66mm(H) x 5.32mm(V)
Active pixels 1,280H x 1,024V
Pixel size 5.2μm x 5.2μm
Shutter type Electronic rolling shutter (ERS)
Maximum data rate/
master clock
48 MPS/48 MHz
Frame
rate
SXGA
(1280 x 1024)
30 fps progressive scan;
programmable
ADC resolution 10-bit, on-chip
Responsivity 2.1 V/lux-sec
Dynamic range 68.2dB
SNRMAX 45dB
Supply voltage 3.0V−3.6V, 3.3V nominal
Power consumption 363mW at 3.3V (operating);
294μW (standby)
Operating temperature 0°C to +70°C
Packaging 48-pin CLCC
Table 2: Available Part Numbers
Part Number Description
MT9M001C12STM 48-pin CLCC (lead free)
PDF: 0185865399/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev.J 5/10 EN 2©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Table of Contents
Table of Contents
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Frame Timing Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Idle State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Two-Wire Serial Interface Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
16-Bit Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Programmable Gain Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Programmable Analog Offset Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Column and Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Column and Row Skip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Still Image Capture with External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
LINE_VALID Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Data Output and Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Image Center Offset and Orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PDF:0185865399/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 3©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
List of Tables
List of Tables
Table 1: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 3: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 4: Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5: Frame Time—Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6: Recommended Gain Settings at 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7: DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 9: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10: Optical Area Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PDF: 0185865399/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 4©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
List of Figures
List of Figures
Figure 1: 48-Pin CLCC Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 2: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4: Pixel Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 6: Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 8: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284. . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10: Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11: Readout of Six Columns in Normal and Column Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12: Readout of Six Rows in Normal and Row Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 13: Readout of Eight Pixels in Normal and Column Skip Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 14: Black Level Calibration Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15: General Timing for Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 16: Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 17: Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 18: Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 19: Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 20: Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 21: Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 24: Quantum Efficiency—Monochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 25: Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 26: Optical Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 27: 48-pin CLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 5©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
General Description
Figure 1: 48-Pin CLCC Package Pinout Diagram
12345648474645
44 43
19 20 21 22 23 24 25 26 27 28 29 30
7
8
9
10
11
12
13
14
15
16
17
18
42
41
40
39
38
37
36
35
34
33
32
31
STANDBY
TRIGGER
NC
RESET#
NC
NC
OE#
NC
A
GND
V
AA
A
GND
A
GND
NC
FRAME_VALID
LINE_VALID
STROBE
D
GND
V
DD
D
OUT
<9>
D
OUT
<8>
D
OUT
<7>
D
OUT
<6>
D
OUT
<5>
P
IXCLK
NC
V
AA
A
GND
V
DD
D
GND
D
OUT
<0>
D
OUT
<1>
D
OUT
<2>
D
OUT
<3>
D
OUT
<4>
CLKIN
NC
NC
D
GND
V
DD
NC
NC
VAAPIX
A
GND
A
GND
SCLK
S
DATA
NC
D
GND
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 6©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
Figure 2: Block Diagram
Clock
Two-wire serial
Input/Output
10-bit Data
Sync
Signals
Control Register
Analog Processing
Active-Pixel
Sensor (APS)
Array
SXGA
1,280H x 1,024V
Timing and Control
ADC
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 7©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
Table 3: Pin Descriptions
Pin Numbers Symbol Type Description
29 CLKIN Input Clock in. Master clock into sensor (48 MHz maximum).
13 OE# Input Output enable. OE# when HIGH places outputs DOUT<0:9>, FRAME_VALID,
LINE_VALID, PIXCLK, and STROBE into a tri-state configuration.
10 RESET# Input Reset. Activates (LOW) asynchronous reset of sensor. All registers assume
factory defaults.
46 SCLK Input Serial clock. Clock for serial interface.
7 STANDBY Input Standby. Activates (HIGH) standby mode, disables analog bias circuitry for
power saving mode.
8 TRIGGER Input Trigger. Activates (HIGH) snapshot sequence.
45 SDATA Input/Output Serial data. Serial data bus, requires 1.5KΩ resistor to 3.3V for pull-up.
24–28, 32–36 DOUT<0–9> Output Data out. Pixel data output bits 0:9, DOUT<9> (MSB), DOUT<0> (LSB).
41 FRAME_VALID Output Frame valid. Output is pulsed HIGH during frame of valid pixel data.
40 LINE_VALID Output Line valid. Output is pulsed HIGH during line of selectable valid pixel data (see
Reg0x20 for options).
31 PIXCLK Output Pixel clock. Pixel data outputs are valid during falling edge of this clock.
Frequency = (master clock).
39 STROBE Output Strobe. Output is pulsed HIGH to indicate sensor reset operation of pixel array
has completed.
15,17,18,21, 47,
48
AGND Supply Analog ground. Provide isolated ground for analog block and pixel array.
5, 23, 38, 43 DGND Supply Digital ground. Provide isolated ground for digital block.
16, 20 VAA Supply Analog power. Provide power supply for analog block, 3.3V ±0.3V.
1 VAAPIX Supply Analog pixel power. Provide power supply for pixel array, 3.3V ±0.3V (3.3V).
4, 22, 37 VDD Supply Digital power. Provide power supply for digital block, 3.3V ±0.3V.
2, 3 ,6, 9, 11,
12,14, 19, 30, 42,
44
NC — No connect. These pins must be left unconnected.
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The MT9M001 pixel array is configured as 1,312 columns by 1,048 rows (shown in
Figure 3). The first 16 columns and the first eight rows of pixels are optically black, and
can be used to monitor the black level. The last seven columns and the last seven rows of
pixels are also optically black. The black row data is used internally for the automatic
black level adjustment. However, the black rows can also be read out by setting the
sensor to raw data output mode (Reg0x20, bit 11 = 1). There are 1,289 columns by 1,033
rows of optically active pixels, which provides a four-pixel boundary around the SXGA
(1,280 x 1,024) image.
Figure 3: Pixel Array Description
Figure 4: Pixel Pattern Detail (Top Right Corner)
Note: e = even column or row
0 = odd column or row
(1311, 1047)
16 black columns
7 black rows
8 black rows (0, 0)
7 black columns
SXGA (1,280 x 1,024)
+ 4 pixel boundary
+ additional active column
+ additional active row
= 1,289 x 1,033 active pixels
Pixel
(8, 16)
black pixe
ls
column readout direction
.
.
.
...
row
readout
direction
ee
oe
ee
oe
ee
oe
eo
oo
eo
oo
eo
oo
ee
oe
ee
oe
ee
oe
eo
oo
eo
oo
eo
oo
ee
oe
ee
oe
ee
oe
eo
oo
eo
oo
eo
oo
ee
oe
ee
oe
ee
oe
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Output Data Format
The MT9M001 image data is read out in a progressive scan. Valid image data is
surrounded by horizontal blanking and vertical blanking, as shown in Figure 5. The
amount of horizontal blanking and vertical blanking is programmable through Reg0x05
and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure.
FRAME_VALID timing is described in “Output Data Timing” on page 9.
Figure 5: Spatial Illustration of Image Readout
Output Data Timing
The data output of the MT9M001 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 6: Timing Example of Pixel Data
The rising edges of the PIXCLK signal are nominally timed to occur on the rising DOUT
edges. This allows PIXCLK to be used as a clock to latch the data. DOUT data is valid on
the falling edge of PIXCLK. The PIXCLK is HIGH while master clock is HIGH and then
LOW while master clock is LOW. It is continuously enabled, even during the blanking
period. The parameters P1, A, P2, and Q in Figure 7 are defined in Table 4.
P
0,0
P
0,1
P
0,2
.....................................P
0,n-1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n-1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-1,0
P
m-1,1
.....................................P
m-1,n-1
P
m-1,n
P
m,0
P
m,1
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE HORIZONTAL
BLANKING
VERTICAL BLANKING VERTICAL/HORIZONTAL
BLANKING
LINE_VALID
PIXCLK
D
OUT
9-D
OUT
0
. . . .
. . . .
. . . .
. . . .
P0
(9:0) P1
(9:0) P2
(9:0) P3
(9:0) P4
(9:0) Pn-1
(9:0) Pn
(9:0)
Valid Image DataBlanking Blanking
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals
P1 A Q A Q AP2
. . .
. . .
. . .
N
umber of master clocks
F
RAME_VALID
LINE_VALID
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Frame Timing Formulas
Notes: 1. Row skip mode should have no effect on the integration time. Column skip mode changes the effective
value of Column Size (Reg0x04) as follows:
Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1
Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1
Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1
where the int() function truncates to the next lowest integer. Now use R4eff in the equation for row
time instead of R4
2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19.
Sensor timing is shown above in terms of pixel clock and master clock cycles (please
refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical
blank and total frame time equations assume that the number of integration rows (bits
13 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 +
1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used
instead to determine the frame time, as shown in Table 5.
Table 4: Frame Timing
Parameter Name Equation (MASTER CLOCK) Default Timing Notes
A Active Data Time (Reg0x04 + 1) 1,280 pixel clocks
= 26.7μs
1
P1Frame Start Blanking (242) 242 pixel clocks
= 5.04μs
P2Frame End Blanking (2 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
2 pixel clocks
= 0.042μs
2
Q = P1 + P2Horizontal Blanking (244 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
244 pixel clocks
= 5.08μs
2
A + Q Row Time ((Reg0x04 + 1) + (244 + Reg0x05 - 19)) 1,524 pixel clocks
= 31.75μs
V Vertical Blanking (Reg0x06 + 1) x (A + Q)
(MIN Reg0x06 value = 15)
39,624 pixel clocks
= 825.5μs
NROWS x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) 1,560,576 pixel clocks
= 32.51ms
F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 1,600,200 pixel clocks
= 33.34ms
Table 5: Frame Time—Long Integration Time
Parameter Name Equation (master clock) Default Timing
V’ Vertical Blanking (long integration time) (Reg0x09 – Reg0x03) x (A + Q) 39,624 pixel clocks
= 82.5μs
F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 1,600,200 pixel clocks
= 33.34ms
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9M001 through the two-wire serial inter-
face bus. The sensor is a two-wire serial interface slave and is controlled by the serial
clock (SCLK), which is driven by the serial interface master. Data is transferred into and
out of the MT9M001 through the serial data (SDATA) line. The SDATA line is pulled up to
3.3V off-chip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line
down—the serial interface protocol determines which device is allowed to pull the
SDATA line down at any given time.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
•a start bit
• the slave device eight-bit address
• a(an) (no) acknowledge bit
• an 8-bit message
•a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's eight-bit address. The last bit of the address
determines if the request will be a read or a write, where a “0” indicates a write and a “1”
indicates a read. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit
data for its internal registers, thus requiring two 8-bit transfers to write to one register.
After 16 bits are transferred, the register address is automatically incremented, so that
the next 16 bits are written to the next register address. The master stops writing by
sending a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data eight bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Serial Bus Description
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of seven bits of address
and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indi-
cates the write mode, and a “1” (0xBB) indicates read mode.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is trans-
ferred eight bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences
Two-Wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 8. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
will then give an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each eight-bit transfer, the image sensor will give an acknowl-
edge bit. All 16 bits must be written before the register will be updated. After 16 bits are
transferred, the register address is automatically incremented so that the next 16 bits are
written to the next register. The master stops writing by sending a start or stop bit.
Figure 8: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
16-Bit Read Sequence
A typical read sequence is shown in Figure 9. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The
register address should be incremented after every 16 bits is transferred. The data
transfer is stopped when the master sends a no-acknowledge bit.
Figure 9: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
S
DATA
START ACK
0xBA ADDR
ACK ACK ACK
STOP
Reg0x09 1000 0100
0000 0010
SCLK
S
DATA
START ACK
0xBA ADDR 0xBB ADDR 0000 0010Reg0x09
ACK ACK ACK
STOP
1000 0100
NACK
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Feature Description
Signal Path
The MT9M001 signal path consists of two stages, a programmable gain stage and a
programmable analog offset stage.
Programmable Gain Stage
A total programmable gain of 15 is available and can be calculated using the following
formula:
Gain 1 to 8: Gain = (bit[6] + 1) x (bit[5:0] x 0.125)
For gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3
LSB's bit[2:0] to set the higher gain values. The formula for obtaining gain greater than
eight is as follows:
Total gain = 8 + bit[2:0]
For example, for total gain = 12, the value to program is bit[6–0] = 1100100.
The maximum total gain = 15, i.e. bit[6:0] = 1100111.
The gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. The
minimum gain of one corresponds to the lowest setting where the pixel signal is guaran-
teed to saturate the ADC under all specified operating conditions. Any reduction of the
gain below this value may cause the sensor to saturate at ADC output values less than
the maximum, under certain conditions. It is recommended that this guideline be
followed at all times.
Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are
alternative ways of achieving certain gains. Some settings offer superior noise perfor-
mance to others, despite the same overall gain. Recommended gain settings are listed in
Table 6.
Figure 10: Signal Path
Table 6: Recommended Gain Settings at 48 MHz
Nominal Gain Increments Recommended Settings
1 to 4.000 0.125 0x08 to 0x20
4.25 to 8.00 0.25 0x51 to 0x60
9 to 15 1.0 0x61 to 0x67
X+
Pixel Output
(signal
minus reset)
Offset Correction Voltage
(Reg0x60, Reg0x61,
Reg0x63, Reg0x64)
(signed lower 9 bits) x 2mV
10-bit ADC ADC Data
(9:0)
Gain Selection
(Reg0x2B - 0x2E)
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Programmable Analog Offset Stage
The programmable analog offset stage corrects for analog offset that might be present in
the analog signal. The user would need to program register 0x62 appropriately to enable
the analog offset correction.
The lower eight bits (bit[7:0]) determines the absolute value of the analog offset to be
corrected and bit[8] determines the sign of the correction. When bit[8] is “1”, the sign of
the correction is negative and vice versa. The analog value of the correction relative to
the analog gain stage can be determined from the following formula:
Analog offset (bit[8] = 0) = bit[7:0] x 2mV
Analog offset (bit[8] = 1) = - (bit[7:0] x 2mV)
Column and Row Mirror Image
By setting bit 14 of Reg0x20, the readout order of the columns will be reversed, as shown
in Figure 11.
Figure 11: Readout of Six Columns in Normal and Column Mirror Output Mode
By setting bits 15 of Reg0x20 the readout order of the rows will be reversed, as shown in
Figure 12.
Figure 12: Readout of Six Rows in Normal and Row Mirror Output Mode
Column and Row Skip
By setting bit 3 of Reg0x20, only half of the columns set will be read out. An example is
shown in Figure 13. Only columns with bit 1 equal to “0” will be read out (xxxxxxx0x).
The row skip works in the same way and will only read out rows with bit 1 equal to “0.”
Row skip mode is enabled by setting bit 4 of Reg0x20. For both row and column skips, the
number of rows or columns read out will be half of what is set in Reg0x03 or Reg0x04,
respectively.
D
OUT
9–D
OUT
0
LINE_VALID
Normal readout Col0
(9:0) Col1
(9:0) Col2
(9:0) Col3
(9:0) Col4
(9:0) Col5
(9:0)
D
OUT
9–D
OUT
0
R
everse readout Col5
(9:0) Col4
(9:0) Col3
(9:0) Col2
(9:0) Col1
(9:0) Col0
(9:0)
D
OUT
9–D
OUT
0
FRAME_VALID
Normal readout
Row0
(9:0) Row1
(9:0) Row2
(9:0) Row3
(9:0) Row4
(9:0) Row5
(9:0)
D
OUT
9–D
OUT
0
Reverse readout
Row4
(9:0)
Row5
(9:0) Row3
(9:0) Row2
(9:0) Row1
(9:0) Row0
(9:0)
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Figure 13: Readout of Eight Pixels in Normal and Column Skip Output Mode
Black Level Calibration
The MT9M001 has automatic black level calibration on-chip which can be overridden by
the user, as described below and shown in Figure 14.
The automatic black level calibration measures the average value of 256 pixels from two
dark rows of the chip for each of the four colors. The pixels are averaged as if they were
light-sensitive and passed through the appropriate color gain. This average is then digi-
tally filtered over many frames.
For each color, the new filtered average is compared to a minimum acceptable level (to
screen for too low a black level) and a maximum acceptable level. If the average is lower
than the minimum acceptable level, the offset correction voltage for that color is
increased by one offset LSB (offset LSBs do not match ADC LSBs; typically, one offset
LSB is approximately 2mV). If it is above the maximum level, the level is decreased by 1
LSB (2mV). The upper threshold is automatically adjusted upwards whenever an
upward shift in the black level from below the minimum results in a new black level
above the maximum. This prevents black level oscillation from below the minimum to
above the maximum. The lower threshold is increased with the maximum gain setting
according to the formula described under Reg0x5F. This prevents clipping of the black
level.
Whenever the gain or any of the readout timing registers is changed (shutter width,
vertical blanking, number of rows or columns, or the shutter delay) or if the black level
recalculation bit, reset bit or restart bit is set, the running digitally filtered average is
reset to the first average of the dark pixels. The digital filtering over many frames is then
restarted. Whenever the gain or the readout timing registers are changed, the upper
threshold is restored to its default value.
After changes to the sensor configuration, large shifts in the black level calibration can
result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row
readout is performed on the first frame after certain changes to the sensor registers. Any
changes to the registers listed above will cause this recalculation. The data from this
sweep allows the sensor to choose an accurate new starting point for the running
average. This procedure can be disabled as described under Reg0x5F.
D
OUT
9–D
OUT
0
LINE_VALID
Normal readout G0
(9:0) R0
(9:0) G1
(9:0) R1
(9:0) G2
(9:0) R2
(9:0) G3
(9:0) R3
(9:0)
D
OUT
9–D
OUT
0
LINE_VALID
C
olumn skip readout G0
(9:0) R0
(9:0) G2
(9:0) R2
(9:0)
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Figure 14: Black Level Calibration Flow Chart
X+
Pixel Output
(signal minus
reset)
Offset Correction Voltage
(color-wise)
10-bit ADC ADC Dat
a
(9:0)
Gain Selection
(color-wise)
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Still Image Capture with External Synchronization
In continuous mode video image capture, the TRIGGER signal should be held LOW or
“0.” To capture a still image, the sensor must first be put into snapshot mode by
programming a “1” in register 0x1E, bit 8. In snapshot mode, the sensor waits for a
TRIGGER signal (FRAME_VALID, LINE_VALID signals are LOW, pixel clock signal
continues). When the TRIGGER signal is received (active HIGH), one frame is read out (a
TRIGGER signal can also be achieved by programming a restart—for example, program
a “1” to bit 0 of Reg0x0B). The reset, readout timing for that frame will be the same as for
a continuous frame with similar register settings; the only difference is that only one
frame is read out. General timing for the snapshot mode is shown in Figure 15.
Figure 15: General Timing for Snapshot Mode
LINE_VALID Signal
By setting bit 9 and 10 of Reg0x20 the line valid signal can get three different output
formats. The formats are shown when reading out four rows and two vertical blanking
rows (Figure 16). In the last format, the LINE_VALID signal is the XOR between the
continuously LINE_VALID signal and the FRAME_VALID signal.
Figure 16: Different LINE_VALID Formats
TRIGGER
R
eset Row 1
Reset Row
R
eset Row x
STROBE
Readout
MAX strobe length (all rows integrating)
MIN strobe length (1 row time)
Default
F
RAME_VALID
LINE_VALID
Continuously
F
RAME_VALID
LINE_VALID
XOR
F
RAME_VALID
LINE_VALID
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Electrical Specifications
Data Output and Propagation Delays
By default, the MT9M001 launches pixel data, FRAME_VALID and LINE_VALID with the
rising edge of PIXCLK. The expectation is that the user captures DOUT[7:0],
FRAME_VALID and LINE_VALID using the falling edge of PIXCLK.
Figure 17: Data Output Timing Diagram
Table 7: DC Electrical Characteristics
(DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C)
Symbol Definition Condition Min Typ Max Units
VDD Core digital voltage 3 3.3 3.6 V
VAA Analog voltage 3 3.3 3.6 V
VAAPIX Pixel supply voltage 3 3.3 3.6 V
VIH Input high voltage VPWR - 0.3 VPWR + 0.3 V
VIL Input low voltage -0.3 0.8 V
IIN Input leakage current No Pull-up Resistor; VIN = VDD or
DGND
-15 15 μA
VOH Output high voltage VPWR - 0.2 — V
VOL Output low voltage 0.2 V
IOZ Tri-state output leakage current — 15 μA
IDD Digital operating current — 20 24 mA
IAA Analog operating current — 85 110 mA
IAAPIX Pixel supply current — 5 10 mA
ISTDBYD Digital standby current STDBY = VDD, CLKIN = 0 MHz — 9 20 μA
CLKIN
PIXCLK
tRtF
tCLKIN
Data[0-7]
Frame Valid/
Line Valid
XXXXXX XXX XXX XXXXXX
Note: Frame_Valid leads Line_Valid by 242 PIXCLKs.
Note: Frame_Valid trails
Line_Valid (1+ Reg0x05-19) PIXCLKS.
tCP
tPFL
tPLL
t
FVS
tPD
tOH
P0 P1 P2 PN
t
LVS
t
OS
tPFH
tPLH
T
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
.
Note: 1Stresses greater than those listed may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
ISTDBYD
W/CLK
Digital standby current STDBY = VDD, CLKIN = 48 MHz — 55 125 μA
ISTDBYDA Analog standby current STDBY = VDD — 80 100 μA
Table 8: AC Electrical Characteristics
(AC Setup Conditions: fCLKIN= 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, Output Load = 30pF,
TA = 25°C))
Symbol Definition Condition Min Typ Max Unit
fCLKIIN Input clock frequency 1 — 48 MHz
tCLKIN Input clock period 1000 — 20.83 ns
T PIXCLK period 1000 — 20.83 ns
tR Input clock rise time 4 V/ns
tF Input clock fall time — 4 V/ns
Clock duty cycle 45 50 55 %
tCP CLKIN to PIXCLK propagation delay — 10 — ns
tPD PIXCLK to data valid — — 1 ns
tPFHPIXCLK to FV high ——7 ns
tPLH PIXCLK to LV high — — 7 ns
tPFL PIXCLK to FV low — — 13 ns
tPLL PIXCLK to LV low — — 13 ns
tOS Setup time for data before falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns
tOH Hold time for data after falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns
tFVS Setup time for FV before falling edge of PIXCLK 2 3 — ns
tLVS Setup time for LV before falling edge of PIXCLK 2 3 — ns
CLOAD Load capacitance 30 pF
Table 9: Absolute Maximum Ratings
Symbol Parameter
Rating
UnitMIN MAX
TOP Operating temperature 0 70 °C
TSTG1Storage temperature –40 125 °C
Table 7: DC Electrical Characteristics (continued)
(DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C)
Symbol Definition Condition Min Typ Max Units
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 22 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Two-wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles
between transitions. These are specified in the following diagrams in master clock
cycles.
Figure 18: Serial Host Interface Start Condition Timing
Figure 19: Serial Host Interface Stop Condition Timing
Note: All timing are in units of master clock cycle.
Figure 20: Serial Host Interface Data Timing for Write
Note: SDATA is driven by an off-chip transmitter.
Figure 21: Serial Host Interface Data Timing for Read
Note: SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
SCLK
5
S
DATA
4
SCLK
5
S
DATA
4
SCLK
4
S
DATA
4
SCLK
5
S
DATA
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 23 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
Note: After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read
sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On
the following cycle, a start or stop bit may be used.
SCLK
Sensor pulls down
S
DATA
pin
6
S
DATA
3
SCLK
Sensor tri-states S
DATA
pin
(turns off pull down)
7
S
DATA
6
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 24 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Quantum Efficiency
Figure 24: Quantum Efficiency—Monochrome
Image Center Offset and Orientation
Figure 25: Image Center Offset
0
10
20
30
40
50
60
350 450 550 650 750 850 950 1050
Quantum Efficiency (%)
Wavelength (nm)
Quantum Efficiency - Monochrome
Pad 1 Pixel (0,0)
Die Center
Image Center
7.75mm
Pixel
Array 0.015mm
0.712mm
Pixel (12, 20)
Black and
Boundary
Pixels
7.75mm
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 25 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Notes: 1. X and Y coordinates referenced to center of die.
2. Die center = package center.
3. Image center offset from package center (x = 0.015mm, y = 0.712mm).
Figure 26: Optical Orientation
Table 10: Optical Area Dimensions
Optical Area Pixel X-Dimension Y-dimension
SXGA Center of pixel (20, 12) 3,340.70μm 3,372.45μm
Center of Pixel (1299, 1035) -3,315.2μm -1,952.35μm
Chip Size, mm (including Seal Ring) 7.75mm 7.75mm
UP
Pin 1
Pixel Array
Top of board
Bottom of board
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 26 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Figure 27: 48-pin CLCC Package Outline Drawing
Notes: 1. All exposed metallized area shall be gold plated 60 micro inches min
thk. over nickel plated unless otherwise specified in purchase order.
2. Seal area and die attach area shall be without metallization.
3. Die center to package center accuracy +/- 100 um
4. Die thickness = 0.675mm(26.5mils).
5. Epoxy thickness for die attachment is 0.025~0.050mm
6. Glass transmittance >=90%.
7. Glass tilt =0.10mm max.
8. All dimensions in millimeters
Top View Side View Bottom View
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 27 ©2004 Aptina Imaging Corporation. All rights reserved.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Revision History
Revision History
Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/10
• Updated to non-confidential
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/10
• Removed registers and transfered to seperate document
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/09
• Updated Figure 27: “48-pin CLCC Package Outline Drawing” on page 30
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/09
• Updated to Aptina template
Rev E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/06
• Updated description in Table 2, “Available Part Numbers,” on page 1
• Update Figure 4: “Pixel Pattern Detail (Top Right Corner),” on page 8
• Updated "Data Output and Propagation Delays" on page 20
•Updated
tPFL and tPLL in Table 8, “AC Electrical Characteristics,” on page 21
Rev D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/06
• Updated Table 1, “Key Performance Parameters,” on page 1
• Update Table 2, “Available Part Numbers,” on page 1
• Updated Figure 4: “Pixel Pattern Detail (Top Right Corner),” on page 8
Rev C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/05
• Remove color information
• Updated Table 1, “Key Performance Parameters,” on page 1
• Updated Table 6, “Register List and Default Values,” on page 11
• Updated Table 7, “Register Description,” on page 12
• Updated Figure 12, Readout of Six Rows in Normal and Row Mirror Output Mode, on
page 16
• Deleted Figure 13, Readout of Eight Pixels in Normal and Column Skip Output Mode,
on page 17
• Updated Table 8, “AC Electrical Characteristics,” on page 21
• Updated Figure 25, Image Center Offset, on page 24
• Updated Figure 27, 48-pin CLCC Package Outline Drawing, on page 26
Rev B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05
• Page 1, remove PRELIMINARY disclaimer
• Page 1, add Key Performance Parameters table, add APPLICATIONS
• Page 2, add Table of Contents
• Page 6, update Pin Description table
• Page 11, update Serial Bus Description
• Page 12, update Timing Diagram Showing a Read from Reg0x09; Returned Value
0x0284 figure
• Page 13, update Register List and Default Values table
• Page 14, update Register Description Table (add Test Data-Reg0x32[11:2], update
Output Control-Reg0x07[6]
• Page 28, update AC and DC Electrical Characteristics table
10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com
Aptina, Aptina Imaging, DigitalClarity, and the Aptina logo are the property of Aptina Imaging Corporation
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final,
these specifications are subject to change, as further product development and data characterization sometimes occur.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Revision History
PDF:7657919000/Source: 7657919000 Aptina reserves the right to change products or specifications without notice.
MT9M001_DS - Rev. J 5/10 EN 28 ©2004 Aptina Imaging Corporation All rights reserved.
• Page 29, add Figure 17, Data Output Timing Diagram, and Absolute Maximum
Ratings, Table 11
• Page 30, update Propagation Delay for Frame_Valid and Line_Valid Signals (Data
Output and Propagation Delays
• Page 32, delete Quantum Efficiency figure (Color)
• Page 33, update Figure 27, 48-pin CLCC Package Outline Drawing
Rev A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/03
• Initial Release of document
