5411674116 Dual 4-Bit Latch with Clear 143 Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL Package Package Package Package Package Device Type Device Type Device Type Device Type Device Type . Cc} P|MICF C!|P| MICF C| P| MCF Cc; P|MICFI Cc} P|MICc T SN54116 J 0) wo i SN74116 J DING FCTATI6 7 FC93116 0) FAIRCHILD FM541167 FM93116 Dg | e@ MOTOROLA N.S.C. PHILIPS N74116 o SIGNETICS N7Q116 AD SIEMENS FUJITSU HITACHI MITSUBISHI NEC TOSHIBA Electrical Characteristics SN54!116SN74116 Pin Assignment (Top View) . . . ENABLE absolute maximum ratings over operating free-air temperature range Veg 204 204 203 203 202 202 201 20) 78x 7Gp CLEAR | Supply voltage. Voc Vv Operating free-ar | SNSA'| -- 55C to 125C Input voltage 5.5V temperature range SN74 OC to 70C Storage temperature range 65C to 150C recommended operating conditions Clean SN54116 SN74116 C Di Or be 02 BI O3 Ds Gal UNIT Tessie vw Pe MIN NOM MAX | MIN NOM MAX cura L282 101 01 12 soe ibs fos iDa 10H OND Supply voltage. Vog 4.5 5 5.5/4.75 5 .25| V ENABLE 7 ; High-ievel output current, |oH - 800 800 | uA Positive logic: see function table Low-level output current, | 6 16} mA : Enable 18 12 Function Table input Ise width, t ns , . Input pulse w w Clea 8 18 1 16(EACH LATCH) High | level 8 INPUTS Data setup time, tsetup rs ee a 4 ns. ENABLE OUTPUT ow logic level CLEAR DATA Q Clear inactive-state setup time, tgetup 8 8 as G1 G2 Data release time, high-level data, treigase 2 2 ns H bok L L Data hold time, low-level data. thoig 8 8 H bok H H Operating free-air temperature, Ta 55 125 0 7} C H x H x Qo electrical characteristics over recommended operating H HX x Q free-air temperature range L xX Xx x L PARAMETER * TEST CONDITIONS t MIN TYPt MAX | UNIT H=high level, L =low tevel, X =irrelevant Vin High-level input voltage 2 Vv Qo=the ievel of Q before these input conditions were established. Vin Low-level input voltage 0.8] Vv v Input ct alt Voo=MIN, l)=lamA 1.5] Vv . : \ put_clamp voltage oe _ ni Functional Block Diagram (esch bit latch) VoH High-level output voltage ce MEE 24 3.4 v Vj =0.8V, 1oH =800nA oben Pf VoC=MIN. ViH=2V, VOL Low-level out fe 0.2 oa} v 1%, Owrlevel output voltage ViE =0.8. loi =16mA aT ss, i Input current at maximum Voo-=MAX, Vj =5.5V b} oma input_voltage ots Gi, G2, { 1 Higtrievel input | tear Veo =MAX. Vj=2.4V 40) uA 1H current ce aes oo Any D 60 oe Gi, G2, -t.6 of clear soo Low-level 1 | Any D, UL owrtenel inp "y Voo=MAX, Vj =0.4V ~-2.4| mA current initial peak 20 Any D, -1.6 steady-state os (te SNSA116 20 57 ' Short-circutt output ot 1% IVog=MAX mA os Ircult output curren ce SNTAIIG xg =57 Voc =MAX, Condition A 60 100 l Suppl t mA ce upply curren See Note Condition B 40 70 t 30 PLH from Enable to output Any Q . 2 ns IPHL Voc =5V. Ta=25'c- 15 22 t Cy =15pF 10 1S {1G DUAL 4-BIT LATCH WITH CLEAR PLH? trom Data to output O L . ns PHL RL =4000 12 18 NOTE: with \ - : With outputs open, IgG is measured for the fotlowing conditions: fi Any {PHL from Ciear to output Any 0 15 22 ns A. Alll inputs grounded. B. All G inputs are grounded and ail other inputs are at 4.5V, + For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. FAI typical values are VoG=5. Ta =25C. @Not more than one output should be shorted at a time. *tPLH =propagation delay time, low-to-high-level output tPHL =propagation delay time, high-to-low-levet output