SLN04G72G2BK2MT-DCRT - Swissbit

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

Figure: mechanical dimensions1

4096MB DDR3L – SDRAM ECC SO-DIMM

204 Pin ECC SO-UDIMM

SLN04G72G2BK2MT-xxRT

4GByte in FBGA Technology

RoHS compliant

Environmental Requirements:

 Operating temperature (ambient)

Standard Grade 0°C to 70°C

 Operating Humidity

10% to 90% relative humidity, noncondensing

 Operating Pressure

105 to 69 kPa (up to 10000 ft.)

 Storage Temperature

-55°C to 100°C

 Storage Humidity

5% to 95% relative humidity, noncondensing

 Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency Marking

DDR3 1333 MT/s CL9 -CC

DDR3 1600 MT/s CL11 -DC

 Module density

4096MB with 18 dies and 2 ranks

 Standard Grade (TA) 0°C to 70°C

(TC) 0°C to 85°C

Features:

 204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double

Data Rate synchronous DRAM Module

 Module organization: dual rank 512M x 72

 VDD = 1.35V and 1.5V

 VDDQ = 1.35V and 1.5V

 SSTL_15 compatible

 Fly-by-bus with termination for C/A & CLK bus

 On-board I2C temperature sensor with integrated serial

presence-detect (SPD) EEPROM

 Gold-contact pad

 This module is fully pin and functional compatible to the

JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM

design spec. and JEDEC- Standard MO-268. (see

www.jedec.org)

 The pcb and all components are manufactured according

to the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]

 DDR3 - SDRAM component Micron

 MT41K256M8DA-125 DIE-Rev. K

 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package

 8-bit prefetch architecture

 Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.

 On-Die-Termination (ODT) and Dynamic ODT for

improved signal integrity.

 Refresh, Self Refresh and Power Down Modes.

 ZQ Calibration for output driver and ODT.

 System Level Timing Calibration Support via Write

Leveling and Multi Purpose Register (MPR) Read Pattern.

1if no tolerances specified ± 0.15mm

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line

Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses

internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to

achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ

and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. The burst length is either four or

eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated

at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent

operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-

down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are

utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR3 SDRAMs used

Row

Addr.

Device Bank

Addr.

Column

Addr.

Refresh

Module

Bank Select

512M x 72bit

18 x 256M x 8bit (2048Mbit)

15

BA0, BA1, BA2

10

8k

S0#, S1#

Module Dimensions

in mm

67.60 (long) x 30(high) x 3.80 [max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate

Clock Cycle/Data bit rate

Latency

SLN04G72G2BK2MT-CCRT

4096MB

10.6 GB/s

1.5ns/1333MT/s

9-9-9

SLN04G72G2BK2MT-DCRT

4096MB

12.8 GB/s

1.25ns/1600MT/s

11-11-11

Pin Name

A0-9, A11 – A14

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0 – BA2

Bank Address Inputs

DQ0 – DQ63

Data Input / Output

CB0 – CB07

ECC check bits

DM0-DM8

Input Data Mask

DQS0 – DQS8

Data Strobe, positive line

DQS0# - DQS8#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0 – CKE1

Clock Enable

S0#, S1#

Chip Select

CK0 – CK1

Clock Inputs, positive line

CK0# - CK1#

Clock Inputs, negative line

Figure 1: Mechanical Dimensions

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 3

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

Event#

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

VDD

Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)

VREFDQ

Reference voltage: DQ, DM (VDD/2)

VREFCA

Reference voltage: Control, command, and address (VDD/2)

VSS

Ground

VTT

Termination voltage: Used for control, command, and address (VDD/2).

VDDSPD

Serial EEPROM Positive Power Supply

SCL

Serial Clock for Presence Detect

SDA

Serial Data Out for Presence Detect

SA0 – SA1

Presence Detect Address Inputs

ODT0, ODT1

On-Die Termination

NC

No Connection

Pin Configuration

Frontside

Symbol

1

VREFDQ

53

VSS

103

A3

155

VSS

3

VSS

55

DQ24

105

A1

157

DM5

5

DQ0

57

DQ25

107

A0

159

DQ42

7

DQ1

59

DM3

109

VDD

161

DQ43

9

VSS

61

VSS

111

CK0

163

VSS

11

DM0

63

DQ26

113

CK0#

165

DQ48

13

DQ2

65

DQ27

115

VDD

167

DQ49

15

DQ3

67

VSS

117

A10/AP

169

VSS

17

VSS

69

CB0

119

BA0

171

DQS6#

19

DQ8

71

CB1

121

WE#

173

DQS6

21

DQ9

Key

123

VDD

175

VSS

23

VSS

73

VSS

125

CAS#

177

DQ50

25

DQS1#

75

DQS8#

127

S0#

179

DQ51

27

DQS1

77

DQS8

129

S1#

181

VSS

29

VSS

79

VSS

131

VDD

183

DQ56

31

DQ10

81

CB2

133

DQ32

185

DQ57

33

DQ11

83

CB3

135

DQ33

187

VSS

35

VSS

85

VDD

137

VSS

189

DM7

37

DQ16

87

CKE0

139

DQS4#

191

DQ58

39

DQ17

89

CKE1

141

DQS4

193

DQ59

41

VSS

91

BA2

143

VSS

195

VSS

43

DQS2#

93

VDD

145

DQ34

197

SA0

45

DQS2

95

A12/BC#

147

DQ35

199

VDDSPD

47

VSS

97

A8

149

VSS

201

SA1

49

DQ18

99

A5

151

DQ40

203

VTT

51

DQ19

101

VDD

153

DQ41

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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Backside

Symbol

2

VSS

54

DQ28

104

A4

156

DQS5

4

DQ4

56

DQ29

106

A2

158

VSS

6

DQ5

58

VSS

108

BA1

160

DQ46

8

VSS

60

DQS3#

110

VDD

162

DQ47

10

DQS0#

62

DQS3

112

CK1

164

VSS

12

DQS0

64

VSS

114

CK1#

166

DQ52

14

VSS

66

DQ30

116

VDD

168

DQ53

16

DQ6

68

DQ31

118

NC(S3#)

170

VSS

18

DQ7

70

VSS

120

NC(S2#)

172

DM6

20

VSS

72

CB4

122

RAS#

174

DQ54

22

DQ12

Key

124

VDD

176

DQ55

24

DQ13

74

CB5

126

ODT0

178

VSS

26

VSS

76

DM8

128

ODT1

180

DQ60

28

DM1

78

VSS

130

A13

182

DQ61

30

Reset#

80

CB6

132

VDD

184

VSS

32

VSS

82

CB7

134

DQ36

186

DQS7#

34

DQ14

84

VREFCA

136

DQ37

188

DQS7

36

DQ15

86

VDD

138

VSS

190

VSS

38

VSS

88

NC(A15)

140

DM4

192

DQ62

40

DQ20

90

A14

142

DQ38

194

DQ63

42

DQ21

92

A9

144

DQ39

196

VSS

44

DM2

94

VDD

146

VSS

198

EVENT#

46

VSS

96

A11

148

DQ44

200

SDA

48

DQ22

98

A7

150

DQ45

202

SCL

50

DQ23

100

A6

152

VSS

204

VTT

52

VSS

102

VDD

154

DQS5#

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 5

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR3 SDRAM SO-UDIMM,

2 RANK AND 18 COMPONENTS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

DQS0

DM0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

VDDSPD SPD

VDD/VDDQ D0-D17

VREFDQ

VREFCA

D0-D17

VSS

CK0,CK1

Notes:

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3. DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4. Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5. For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240O±1%.

6. Refer to associated figure for SPD details.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D0

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D9

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D1

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D10

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D2

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D11

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D3

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D12

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D4

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D13

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D5

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D14

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D6

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D15

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D7

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D16

DQSCS

S1

CB0

CB1

CB2

CB3

CB5

CB4

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D8

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D17

DQSCS

BA0-BA2BA0-BA2: SDRAM D0-D17

A0-A14 A0-A14: SDRAM D0-D17

RAS RAS: SDRAM D0-D17

CAS CAS: SDRAM D0-D17

WE WE: SDRAM D0-D17

ODT0 ODT: SDRAM D0-D8

CKE1 CKE: SDRAM D9-D17

CK: SDRAM D0-D17

CK0,CK1CK: SDRAM D0-D17

RESET RESET: SDRAM D0-D17

CKE0 CKE: SDRAM D0-D8

ODT1 ODT: SDRAM D9-D17

DQS8

DM8

DQS8

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 6

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

VDD

-0.4

1.975

V

I/O Supply Voltage

VDDQ

-0.4

1.975

V

Voltage on any pin relative to VSS

VIN, VOUT

-0.4

1.975

V

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V

(All other pins not under test = 0V)

II

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-16

16

CK, CK#

-16

16

DM

-2

2

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

-5

5

µA

DQ, DQS, DQS#

VREF LEAKAGE CURRENT ; VREF is on a valid level

IVREF

-8

8

µA

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

NOM

MAX

UNITS

Supply Voltage

VDD

1.283

1.350

1.450

V

I/O Supply Voltage

VDDQ

1.283

1.350

1.450

V

I/O Reference Voltage

VREF

0.49 x VDDQ

0.50 x VDDQ

0.51x VDDQ

V

I/O Termination Voltage (system)

VTT

0.49 x VDDQ-20mV

0.50 x VDDQ

0.51x VDDQ+20mV

V

Input High (Logic 1) Voltage

VIH (DC90)

VREF + 90mV

VDDQ + 0.3

V

Input Low (Logic 0) Voltage

VIL (DC90)

-0.3

VREF – 90mV

V

Under 1.5V operation this DDR3L device operates in accordance to the following specification:

SGN04G72G1BM2MT-XXRT

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Input High (Logic 1) Voltage

VIH (AC135)

VREF + 135mV

-

V

Input Low (Logic 0) Voltage

VIL (AC135)

-

VREF – 135mV

V

CAPACITANCE

At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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IDD Specifications and Conditions

(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283 – 1.45V)

Parameter

& Test Condition

Symbol

12800-11-11-11

10600-9-9-9

Unit

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

IDD0

459

450

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as IDD4W

IDD1

576

558

mA

PRECHARGE POWER-DOWN

CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at VREF

Slow Exit

IDD2P

216

mA

Fast Exit

252

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at VREF

IDD2Q

360

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD2N

378

mA

ACTIVE POWER-DOWN CURRENT:

All device banks open; tCK = tCK (IDD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at VREF (always fast exit)

IDD3P

378

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD3N

576

540

mA

OPERATING READ CURRENT:

All device banks open, Continuous burst reads; One

module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

IDD4R

954

846

mA

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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Parameter

& Test Condition

Symbol

12800-11-11-11

10600-9-9-9

Unit

OPERATING WRITE CURRENT:

All device banks open, Continuous burst writes; One

module rank active; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

IDD4W

981

873

mA

BURST REFRESH CURRENT:

tCK = tCK (IDD); refresh command at every tRFC (IDD)

interval, CKE is HIGH, CS# is HIGH between valid

commands; All other Control and Address bus inputs

are changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD5

1098

1089

mA

SELF REFRESH CURRENT:

CK and CK# at 0V; CKE ≤ 0.2V; All other Control and

Address bus inputs are floating at VREF; DQ’s are

floating at VREF

IDD6

216

mA

OPERATING CURRENT*) :

Four device bank interleaving READs, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK

(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are not changing during

DESELECT; DQ inputs changing once per clock cycle

IDD7

1512

1458

mA

*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)

mode.

TIMING VALUES USED FOR IDD MEASUREMENT

SYMBOL

12800-11-11-11

10600-9-9-9

Unit

CL (IDD)

11

9

tCK

tRCD (IDD)

13.75

13.5

ns

tRC (IDD)

48.75

49.5

ns

tRRD (IDD)

6

ns

tCK (IDD)

1.25

1.5

ns

tRAS MIN (IDD)

35

36

ns

tRAS MAX (IDD)

70’200

ns

tRP (IDD)

13.75

13.5

ns

tRFC (IDD)

160

ns

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9

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DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283 – 1.45V)

AC CHARACTERISTICS

12800-11-11-11

10600-999

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Clock cycle time

CL = 11

tCK (11)

1.25

-

ns

CL = 10

tCK (10)

1.5

<1.875

1.5

<1.875

CL = 9

tCK (9)

1.5

<1.875

1.5

<1.875

CL = 8

tCK (8)

1.875

<2.5

1.875

<2.5

CL = 7

tCK (7)

1.875

<2.5

1.875

<2.5

CL = 6

tCK (6)

2.5

3.3

2.5

3.3

CL = 5

tCK (5)

3.0

3.3

3.0

3.3

Internal READ command to first

data

tAA

13.75

-

13.5

-

CK high-level width

tCH (AVG)

0.47

0.53

0.47

0.53

tCK

CK low-level width

tCL (AVG)

0.47

0.53

0.47

0.53

tCK

Data-out high-impedance

window from CK/CK#

tHZ

225

250

ps

Data-out low-impedance window

from CK/CK#

tLZ

-450

225

-500

250

ps

DQ and DM input setup time

relative to DQS VREF=1V/ns

tDS1V

160

-

180

-

ps

DQ and DM input hold time

relative to DQS VREF=1V/ns

tDH1V

145

-

165

-

ps

DQ and DM input pulse width

( for each input )

tDIPW

360

-

400

-

ps

DQS, DQS# to DQ skew, per

access

tDQSQ

100

125

ps

DQ-DQS hold, DQS to first DQ

to go non-valid, per access

tQH

0.38

-

0.38

-

tCK

(AVG)

DQS input high pulse width

tDQSH

0.45

0.55

0.45

0.55

tCK

DQS input low pulse width

tDQSL

0.45

0.55

0.45

0.55

tCK

DQS, DQS# rising to/from CK,

CK#

tDQSCK

-225

225

-255

255

ps

DQS, DQS# rising to/from CK,

CK# when DLL disabled

tDQSCK

DLL_DIS

1

10

1

10

ns

DQS falling edge to CK rising

- setup time

tDSS

0.18

-

0.2

-

tCK

DQS falling edge from CK rising

- hold time

tDSH

0.18

-

0.2

-

tCK

DQS read preamble

tRPRE

0.9

Note1

0.9

Note1

tCK

DQS read postamble

tRPST

0.3

Note2

0.3

Note2

tCK

DQS write preamble

tWPRE

0.9

-

0.9

-

tCK

DQS write postamble

tWPST

0.3

-

0.3

-

tCK

Positive DQS latching edge to

associated clock edge

tDQSS

- 0.27

0.27

- 0.25

+ 0.25

tCK

Address and control input pulse

width ( for each input )

tIPW

560

-

620

-

ps

CTRL, CMD, Addr setup to CK,

CK#

tIS(Base)

45

-

65

-

ps

CTRL, CMD, Addr setup to CK,

CK# VREF @ 1V/ns

tIS(1V)

220

-

240

-

ps

1 The maximum preamble is bound by tLZDQS (MAX)

2 The maximum postamble is bound by tHZDQS (MAX)

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 10

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283 – 1.45V)

AC CHARACTERISTICS

12800-11-11-11

10600-999

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

CTRL, CMD, Addr hold to CK,

CK#

tIH(Base)

120

-

140

-

ps

CTRL, CMD, Addr hold to CK,

CK# VREF @ 1V/ns

tIH(1V)

220

-

240

-

ps

CAS# to CAS# command delay

tCCD

4

-

4

-

tCK

ACTIVE to ACTIVE (same bank)

command period

tRC

48.75

-

49.5

-

ns

ACTIVE to ACTIVE minimum

command period

tRRD

max

4nCK,6ns

max

4nCK,6ns

ns

ACTIVE to READ or WRITE

delay

tRCD

13.75

-

13.5

-

ns

Four bank

Activate period

1K Page size

tFAW

30

-

30

-

ns

2K Page size

40

-

45

-

ACTIVE to PRECHARGE

command

tRAS

35

72’200

36

70’200

ns

Internal READ to precharge

command delay

tRTP

max

4nCK,7.5ns

-

max

4nCK,7.5ns

-

ns

Write recovery time

tWR

15

-

15

-

ns

Auto precharge write recovery +

precharge time

tDAL

tWR + tRP/tCK

-

tWR + tRP/tCK

-

ns

Internal WRITE to READ

command delay

tWTR

max

4nCK,7.5ns

-

max

4nCK,7.5ns

-

ns

PRECHARGE command period

tRP

13.75

-

13.5

-

ns

LOAD MODE command cycle

time

tMRD

4

-

4

-

tCK

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

tRFC

160

70’200

160

70’200

ns

Average periodic refresh interval

0 °C ≤ TCASE ≤ 85°C

tREFI

-

7.8

-

7.8

µs

85 °C < TCASE ≤ 95°C

tREFI (IT)

-

3.9

-

3.9

RTT turn-on from ODTL on

reference

tAON

-225

225

-250

250

ps

RTT turn-on from ODTL off

reference

tAOF

0.3

0.7

0.3

0.7

tCK

Asynchronous RTT turn-on

delay (power Down with DLL off)

tAONPD

2

8.5

2

8.5

ns

Asynchronous RTT turn-off

delay (power Down with DLL off)

tAOFPD

2

8.5

2

8.5

ns

RTT dynamic change skew

tADC

0.3

0.7

0.3

0.7

tCK

Exit self refresh to commands

not requiring a locked DLL

tXS

max

5nCK,tR

FC + 10ns

-

max

5nCK,tR

FC + 10ns

-

ns

Write levelling setup from rising

CK, CK# crossing to rising DQS,

DQS# crossing

tWLS

165

-

195

-

ps

Write levelling setup from rising

DQS, DQS# crossing to rising

CK, CK# crossing

tWLH

165

-

195

-

ps

First DQS, DQS# rising edge

tWLMRD

40

-

40

-

tCK

DQS, DQS# delay

tWLDQSEN

25

-

25

-

tCK

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 11

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DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = 1.283 – 1.45V)

AC CHARACTERISTICS

12800-11-11-11

10600-999

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Exit reset from CKE HIGH to a

valid command

tXPR

max

5nCK,

tRFC + 10ns

-

max

5nCK,

tRFC + 10ns

-

tCK

Begin power supply ramp to

power supplies stable

tVDDPR

-

200

-

200

ms

RESET# LOW to power supplies

stable

tRPS

0

200

0

200

ms

RESET# LOW to I/O and RTT

High-Z

tIOz

-

20

-

20

ns

Exit precharge power-down to

any non-READ command

tXP

max

3nCK,6ns

-

max

3nCK,6ns

-

tCK

CKE minimum high/low time

tCKE

max

3nCK,

5ns

-

max

3nCK,

5.625ns

-

tCK

Temperature Sensor with Serial Presence-Detect EEPROM

SCL SDA

EVENT

SA2

SA1

SA0

EVENT

WP/

R1

0Ω

Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter / Condition

Symbol

MIN

MAX

Unit

Supply voltage

VDDSPD

+3

+3.6

V

Supply current: VDD = 3.3V

IDD

+2.0

mA

Input high voltage: Logic 1; SCL, SDA

VIH

+1.45

VDDSPD +1

V

Input low voltage: Logic 0; SCL, SDA

VIL

-

550

mV

Output low voltage: IOUT= 2.1mA

VOL

-

400

mV

Input current

IIN

-5.0

5.0

µA

Temperature sensing range

TBD

°C

Temperature sensor accuracy

TBD

°C

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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A.C. Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Symbol

Parameter / Condition

MIN

MAX

Unit

fSCL

SCL clock frequency

10

400

kHz

tBUF

Bus Free Time Between STOP and START

1300

ns

tF

SDA fall time

300

ns

tR

SDA rise time

300

ns

tHD:DAT

Data hold time (accepted for Input Data)

0

ns

Data Hold Time (guaranteed for Output Data)

300

900

ns

tH:STA

Start condition hold time

600

ns

tHIGH

High Period of SCL

600

Ns

tLOW

Low Period of SCL

1300

Ns

tSU:DAT

Data setup time

100

Ns

tSU:STA

Start condition setup time

600

Ns

tSU:STO

Stop condition setup time

600

Ns

tTIMEOUT

SMBus SCL Clock Low Timeout

25

35

Ms

tI

Noise Pulse Filtered at SCL and SDA Inputs

100

Ns

tWR

Write Cycle Time

5

Ms

tPU

Power-up Delay to Valid Temperature Recording

100

Ms

Temperature Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Parameter

Test Conditions/Comments

MAX

Unit

Temperature Reading Error

Class B, JC42.4 compliant

+75°C ≤ TA ≤ +95°C, active range

±1.0

°C

+40°C ≤ TA ≤ +125°C, monitor range

±2.0

°C

-40°C ≤ TA ≤ +125°C, sensing range

±3.0

°C

ADC Resolution

12

Bits

Temperature Resolution

0.0625

°C

Conversion Time

100

Ms

Thermal Resistance1 θJA

Junction-to-Ambient (Still Air)

92

°C/W

1 Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal

resistance value refers to the case of a package being used on a standard 2-layer PCB.

Slave Address Bits of Temperature Sensor

Device

Device Type Identifier

Select Address Signals

R/W#

b71

b6

b5

b4

b3

b2

b1

b0

EEPROM

1

0

1

0

A2

A1

A0

R/W#

Temp. Sensor

0

1

A2

A1

A0

R/W#

1 The most significant bit, b7, is sent first.

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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SERIAL PRESENCE-DETECT MATRIX

Byte

Byte Description

12800-11-11-11

10600-9-9-9

0

CRC RANGE, EEPROM BYTES, BYTES USED

0x92

1

SPD REVISON

0x11

2

DRAM DEVICE TYPE

0x0B

3

MODULE TYPE (FORM FACTOR)

0x08

4

SDRAM DEVICE DENSITY & BANKS

0x03

5

SDRAM DEVICE ROW & COLUMN COUNT

0x19

6

MODULE NOMINAL VOLTAGE, VDD

0x02

7

MODULE RANKS & DEVICE DQ COUNT

0x09

8

ECC TAG & MODULE MEMORY BUS WIDTH

0x0B

9

FINE TIMEBASE DIVIDEND/DIVISOR

0x11

10

MEDIUM TIMEBASE DIVIDEND

0x01

11

MEDIUM TIMEBASE DIVISOR

0x08

12

MIN SDRAM CYCLE TIME (tCK MIN)

0x0A

0x0C

13

BYTE 13 RESERVED

0x00

14

CAS LATENCIES SUPPORTED (CL4 => CL11)

0xFE

0x7E

15

CAS LATENCIES SUPPORTED (CL12 => CL18)

0x00

16

MIN CAS LATENCY TIME (tAA MIN)

0x69

17

MIN WRITE RECOVERY TIME (tWR MIN)

0x78

18

MIN RAS# TO CAS# DELAY (tRCD MIN)

0x69

19

MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)

0x30

20

MIN ROW PRECHARGE DELAY (tRP MIN)

0x69

21

UPPER NIBBLE FOR tRAS & tRC

0x11

22

MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)

0x18

0x20

23

MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)

0x81

0x89

24

MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB

0x00

25

MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB

0x05

26

MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)

0x3C

27

MIN INTERNAL READ TO PRECHARGE CMD DELAY

(tRTP MIN)

0x3C

28

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB

0x00

29

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB

0xF0

30

SDRAM DEVICE OUTPUT DRIVERS SUPPORTED

0x83

31

SDRAM DEVICE THERMAL & REFRESH OPTIONS

0x05

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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Byte

Byte Description

12800-11-11-11

10600-9-9-9

32

DDR3-MODULE THERMAL SENSOR

0x80

33-59

BYTES 33-59 RESERVED

0x00

60

MODULE HEIGHT (NOMINAL)

0x0F

61

MODULE THICKNESS (MAX)

0x11

62

REFERENCE RAW CARD ID

0x03

63

ADDRESS MAPPING EDGE CONECTOR TO DRAM

0x00

64-116

BYTES 64-116 RESEVED

0x00

117

MODULE MFR ID (LSB)

0x83

118

MODULE MFR ID (MSB)

0xDA

119

MODULE MFR LOCATION ID

0x01 (Switzerland)

0x02 (Germany)

0x03 (USA)

120

MODULE MFR YEAR

X

121

MODULE MFR WEEK

X

122-125

MODULE SERIAL NUMBER

X

126-127

CRC

0xFDF0

0x282E

128-145

MODULE PART NUMBER

"SLN04G72G2BK2MT-xx"

146

MODULE DIE REV

X

147

MODULE PCB REV

X

148

DRAM DEVICE MFR ID (LSB)

0x80

149

DRAM DEVICE MFR (MSB)

0x2C

150-175

MFR RESERVED BYTES 150-175

0x00

176-255

CUSTOMER RESERVED BYTES 176-255

0xFF

Part Number Code

S

L

N

04G

72

G2

B

K

2

MT

-

DC

*

R

T

1

2

3

4

5

6

7

8

9

10

11

12

13

14

*RoHs compl.

Swissbit AG

DDR3-1600 MT/s

SDRAM DDR3L

204 Pin SoDIMM

Chip Vendor (Micron)

Depth (4GB)

2 Module Ranks

Width

Chip Rev. K

PCB-Type (S3E3E1)

Chip organisation x8

* optional / additional information

T= Thermal Sensor

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 15

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Revision History

Revision

Changes

Date

1.0

Initial Revision

13.12.2012

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

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Locations

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Switzerland

Phone: +41 (0)71 913 03 03

Fax: +41 (0)71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone: +49 (0)30 93 69 54 – 0

Fax: +49 (0)30 93 69 54 – 55

_____________________________

Swissbit NA, Inc.

1117 E Plaza Drive Unit E Suites 105/205

Eagle, ID 83616

USA

Phone: +1 208 258-6254

Fax: +1 208 938-4525

_____________________________

Swissbit Japan, Inc.

3F Core Koenji,

2-1-24 Koenji-Kita, Suginami-Ku,

Tokyo 166-0002

Japan

Phone: +81 3 5356 3511

Fax: +81 3 5356 3512

________________________________

Data Sheet Rev.1.0 13.12.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 17

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17

Declaration of Conformity

We

Manufacturer: Swissbit AG

Industriestrasse 4

CH-9552 Bronschhofen

Switzerland

declare under our sole responsibility that the product

Product Type: 4GB DDR3L SO-UDIMM

Brand Name: SWISSMEMORY™

Product Series: DDR3L SO-UDIMM

Part Number: SLN04G72G2BK2MT-xxxRT

to which this declaration relates is in conformity with the following directives:

2002/96/EC Category 3 (WEEE)

following the provisions of Directive

Restriction of the use of certain hazardous substances

2011/65/EU

Swissbit AG, Dezember 2012

Manuela Kögel

Head of Quality Management

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Swissbit:

SLN04G72G2BK2MT-DCRT