TSC2007IPWG4 - Texas Instruments

TSC2007

FEATURES APPLICATIONS

DESCRIPTION

PENIRQ

I C

Serial

Interface

and

Control

2SCL

SDA

A[0:1]

X+

X-

Y+

Y-

AUX

TEMP

Mux

VDD/REF

GND

SAR

ADC

Internal

Clock

Touch

Screen

Drivers

Interface

Preprocessing

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

1.2V to 3.6V, 12-Bit, Nanopower, 4-WireMicro TOUCH SCREEN CONTROLLER with I

C™ Interface

•Cellular Phones23

•4-Wire Touch Screen Interface

•PDA, GPS, and Media Players•Single 1.2V to 3.6V Supply/Reference

•Portable Instruments•Ratiometric Conversion

•Point-of-Sale Terminals•Effective Throughput Rate:

•Multiscreen Touch Control Systems– Up to 20kHz (8-Bit) or 10kHz (12-Bit)•Preprocessing to Reduce Bus Activity•I

C Interface Supports:

The TSC2007 is a very low-power touch screen– Standard, Fast, and High-Speed Modes

controller designed to work with power-sensitive,•Simple, Command-Based User Interface:

handheld applications that are based on an advancedlow-voltage processor. It works with a supply voltage–TSC2003 Compatible

as low as 1.2V, which can be supplied by a– 8- or 12-Bit Resolution

single-cell battery. It contains a complete, ultra-low•On-Chip Temperature Measurement

power, 12-bit, analog-to-digital (A/D) resistive touchscreen converter, including drivers and the control•Touch Pressure Measurement

logic to measure touch pressure.•Digital Buffered PENIRQ

In addition to these standard features, the TSC2007•On-Chip, Programmable PENIRQ Pull-Up

offers preprocessing of the touch screen•Auto Power-Down Control

measurements to reduce bus loading, thus reducing•Low Power:

the consumption of host processor resources that canthen be redirected to more critical functions.– 32.24 µA at 1.2V, Fast Mode, 8.2kHz Eq Rate– 39.31 µA at 1.8V, Fast Mode, 8.2kHz Eq Rate

The TSC2007 supports an I

C serial bus and datatransmission protocol in all three defined modes:– 53.32 µA at 2.7V, Fast Mode, 8.2kHz Eq Rate

standard, fast, and high-speed. It offers•Enhanced ESD Protection:

programmable resolution of 8 or 12 bits to– ± 8kV HBM

accommodate different screen sizes and performanceneeds.– ± 1kV CDM– ± 25kV Air Gap Discharge

The TSC2007 is available in a 12-lead,(1.555 ± 0.055mm) x (2.055 ± 0.055mm), 3 x 4 array,– ± 15kV Contact Discharge

wafer chip-scale package (WCSP), and a 16-pin,•1.5 x 2 WCSP-12 and 5 x 6.4 TSSOP-16

TSSOP package. The TSC2007 is characterized forPackages

the – 40 ° C to +85 ° C industrial temperature range.U.S. Patent NO. 6246394; other patents pending.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2I2C is a trademark of NXP Semiconductors.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ABSOLUTE MAXIMUM RATINGS

(1)

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

TYPICAL TYPICAL NO MISSINGINTEGRAL GAIN CODES SPECIFIED TRANSPORTLINEARITY ERROR RESOLUTION PACKAGE PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) (BITS) TYPE DESIGNATOR RANGE MARKING NUMBER QUANTITY

TSC2007IPW Tube, 9016-Pin,

5 x 6.4 PW – 40 ° C to +85 ° C TSC2007

Tape andTSC2007IPWRTSSOP

Reel, 2000TSC2007I ± 1.5 0.1 11

Small Tape12-Pin,

TSC2007IYZGT

and Reel, 2503 x 4 Matrix,

YZG – 40 ° C to +85 ° C TSC2007I1.5 x 2

Tape andTSC2007IYZGRWCSP

Reel, 3000

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI website at www.ti.com .

Over operating free-air temperature range (unless otherwise noted).

PRAMETER TSC2007 UNIT

Analog input X+, Y+, AUX to GND – 0.4 to V

+ 0.1 VVoltage

Analog input X – , Y – to GND – 0.4 to V

+ 0.1 VVoltage range VDD/REF pin to GND – 0.3 to +5 VDigital input voltage to GND – 0.3 to V

+ 0.3 VDigital output voltage to GND – 0.3 to V

+ 0.3 VPower dissipation (T

Max - T

)/ θ

TSSOP package 86Thermal impedance, θ

Low-K 113 ° C/WWCSP package

High-K 62Operating free-air temperature range, T

– 40 to +85 ° CStorage temperature range, T

STG

– 65 to +150 ° CJunction temperature, T

Max +150 ° CVapor phase (60 sec) +215 ° CLead temperature

Infrared (15 sec) +220 ° CIEC contact discharge

(2)

X+, X – , Y+, Y – ± 15 kVIEC air discharge

(2)

X+, X – , Y+, Y – ± 25 kV

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure toabsolute-maximum rated conditions for extended periods may affect device reliability.(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.

Product Folder Link(s): TSC2007

ELECTRICAL CHARACTERISTICS

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

At T

= – 40 ° C to +85 ° C, V

= +1.2V to +3.6V, unless otherwise noted.

TSC2007

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUXILIARY ANALOG INPUT

Input voltage range 0 V

Input capacitance 12 pF

Input leakage current – 1 +1 µA

A/D CONVERTER

Resolution Programmable: 8 or 12 bits 12 Bits

No missing codes 12-bit resolution 11 Bits

Integral linearity ± 1.5 LSB

(1)

= 1.8V – 1.2 LSBOffset error

= 3.0V – 3.1 LSB

= 1.8V 0.7 LSBGain error

= 3.0V 0.1 LSB

TOUCH SENSORS

= +25 ° C, V

= 1.8V, command ' 1011 ' set ' 0000 ' 51 k ΩPENIRQ pull-up resistor, R

IRQ

= +25 ° C, V

= 1.8V, command ' 1011 ' set ' 0001 ' 90 k Ω

Y+, X+ 6 ΩSwitch

on-resistance

Y – , X – 5 Ω

Switch drivers drive current

(2)

100ms duration 50 mA

INTERNAL TEMPERATURE SENSOR

Temperature range – 40 +85 ° C

= 3V 1.94 ° C/LSBDifferential

method

(3)

= 1.6V 1.04 ° C/LSBResolution

= 3V 0.35 ° C/LSBTEMP1

(4)

= 1.6V 0.19 ° C/LSB

= 3V ± 2 ° C/LSBDifferential

method

(3)

= 1.6V ± 2 ° C/LSBAccuracy

= 3V ± 3 ° C/LSBTEMP1

(4)

= 1.6V ± 3 ° C/LSB

INTERNAL OSCILLATOR

= 1.2V 3.19 MHz

= 1.8V 3.66 MHz8-Bit

= 2.7V 3.78 MHz

= 3.6V 3.82 MHzInternal clock frequency, f

CCLK

= 1.2V 1.6 MHz

= 1.8V 1.83 MHz12-Bit

= 2.7V 1.88 MHz

= 3.6V 1.91 MHz

= 1.6V 0.0056 %/ ° CFrequency drift

= 3.0V 0.012 %/ ° C

(1) LSB means Least Significant Bit. With VDD/REF pin = +1.6V, one LSB is 391 µV.(2) Specified by design, but not tested. Exceeding 50mA source current may result in device degradation.(3) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.(4) Temperature drift is – 2.1mV/ ° C.

Product Folder Link(s): TSC2007

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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ELECTRICAL CHARACTERISTICS (continued)At T

= – 40 ° C to +85 ° C, V

= +1.2V to +3.6V, unless otherwise noted.

TSC2007

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT/OUTPUT

Logic family CMOS

1.2V ≤V

< 1.6V 0.7 × V

+ 0.3 VV

1.6V ≤V

≤3.6V 0.7 × V

+ 0.3 V

1.2V ≤V

< 1.6V – 0.3 0.2 × V

1.6V ≤V

≤3.6V – 0.3 0.3 × V

SCL and SDA pins – 1 1 µALogic level

SCL and SDA pins 10 pF

= 2 TTL loads V

– 0.2 V

= 2 TTL loads 0 0.2 V

LEAK

Floating output – 1 1 µA

OUT

Floating output 10 pF

Data format Straight binary

POWER-SUPPLY REQUIREMENTS

Power-supply voltage, V

Specified performance 1.2 3.6 V

32.56k eq rate 128 190 µAV

= 1.2V

8.2k eq rate 32.24 µA12-bit Fast mode

34.42k eq rate 165 240 µAQuiescent supply current

(clock = 400kHz) V

= 1.8V(V

with sensor off)

8.2k eq rate 39.31 µAPD[1:0] = 0,0

34.79k eq rate 226.2 335 µAV

= 2.7V

8.2k eq rate 53.32 µA

Power down supply current Not addressed, SCL = SDA = 1 0 0.8 µA

POWER ON/OFF SLOPE REQUIREMENTS

off ramp T

= – 40 ° C to +85 ° C 2 kV/s

= – 40 ° C to +85 ° C, V

= 0V 1.2 sV

off time

= – 20 ° C to +85 ° C, V

= 0V 0.3 s

on ramp T

= – 40 ° C to +85 ° C 12 kV/s

Product Folder Link(s): TSC2007

PIN CONFIGURATIONS

AUX

SCL

SDA

PENIRQ

VDD/REF

X+

Y+

X-

Y-

GND

TSC2007

C lumnso

(FRONTVIEW)

A CB D

GND

A0 A1VDD/REF

Y-Y+X+

SCL

PENIRQ SDA

AUX

Rows

X-

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

PW PACKAGE

YZG PACKAGETSSOP-16

WCSP-12(TOP VIEW)

(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)

PIN ASSIGNMENTSPIN NO.

PINTSSOP WCSP NAME I/O A/D DESCRIPTION

1 A2 VDD/REF Supply voltage and external reference input

2 A3 X+ I A X+ channel input

3 B3 Y+ I A Y+ channel input

4 C3 X – I A X – channel input

5 D3 Y – I A Y – channel input

6 D2 GND Ground

7 — NC No connection

8 — NC No connection

9 — NC No connection

10 B1 PENIRQ O D Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.

11 C1 SDA I/O D Serial data I/O

Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to12 D1 SCL I/O D

delay a bus transfer.

13 C2 A1 I D Address input bit 1

14 B2 A0 I D Address input bit 0

15 — NC No connection

16 A1 AUX I A Auxiliary channel input

Product Folder Link(s): TSC2007

TIMING INFORMATION

tHD, STA

tSU, DAT

tHD, DAT

tSU, STA

tSU, STO

tHD, STA

tLOW

tHIGH

tRtF

tBUF

SDA

START

CONDITION

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

SCL

TIMING REQUIREMENTS: I

C Standard Mode (SCL = 100kHz)

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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Figure 1. Detailed I/O Timing

All specifications typical at – 40 ° C to +85 ° C, V

= 1.6V, unless otherwise noted.

2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency f

SCL

0 100 kHz

Bus free time between a STOP and START condition t

BUF

4.7 µs

Hold time (repeated) START condition t

HD, STA

4.0 µs

Low period of SCL clock t

LOW

4.7 µs

High period of the SCL clock t

HIGH

4.0 µs

Setup time for a repeated START condition t

SU, STA

4.7 µs

Data hold time t

HD, DAT

0 3.45 µs

Data setup time t

SU, DAT

250 ns

Rise time for both SDA and SCL signals (receiving) t

= total bus capacitance 1000 ns

Fall time for both SDA and SCL signals (receiving) t

= total bus capacitance 300 ns

Fall time for both SDA and SCL signals (transmitting) t

= total bus capacitance 250 ns

Setup time for STOP condition t

SU, STO

4.0 µs

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, V

= 1.8V 434.7 µsCycle time

12 bits 49 SCL + 148 CCLK, V

= 1.8V 570.9 µs

8 bits V

= 1.8V 2.3 kSPSEffective throughput

12 bits V

= 1.8V 1.75 kSPS

8 bits V

= 1.8V 16.1 kHzEquivalent rate = effective throughput × 7

12 bits V

= 1.8V 12.26 kHz

Product Folder Link(s): TSC2007

TIMING REQUIREMENTS: I

C Fast Mode (SCL = 400kHz)

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

All specifications typical at – 40 ° C to +85 ° C, V

= 1.6V, unless otherwise noted.

2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency f

SCL

0 400 kHz

Bus free time between a STOP and START condition t

BUF

1.3 µs

Hold time (repeated) START condition t

HD, STA

0.6 µs

Low period of SCL clock t

LOW

1.3 µs

High period of the SCL clock t

HIGH

0.6 µs

Setup time for a repeated START condition t

SU, STA

0.6 µs

Data hold time t

HD, DAT

0 0.9 µs

Data setup time t

SU, DAT

100 ns

Rise time for both SDA and SCL signals (receiving) t

= total bus capacitance 20+0.1 × C

300 ns

Fall time for both SDA and SCL signals (receiving) t

= total bus capacitance 20+0.1 × C

300 ns

Fall time for both SDA and SCL signals (transmitting) t

= total bus capacitance 20+0.1 × C

250 ns

Setup time for STOP condition t

SU, STO

0.6 µs

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, V

= 1.8V 134.7 µsCycle time

12 bits 49 SCL + 148 CCLK, V

= 1.8V 203.4 µs

8 bits V

= 1.8V 7.42 kSPSEffective throughput

12 bits V

= 1.8V 4.92 kSPS

8 bits V

= 1.8V 51.97 kHzEquivalent rate = effective throughput × 7

12 bits V

= 1.8V 34.42 kHz

TIMING REQUIREMENTS: I

C High-Speed Mode (SCL = 1.7MHz)All specifications typical at – 40 ° C to +85 ° C, V

= 1.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency f

SCL

0 1.7 MHz

Hold time (repeated) START condition t

HD, STA

160 ns

Low period of SCL clock t

LOW

320 ns

High period of the SCL clock t

HIGH

120 ns

Setup time for a repeated START condition t

SU, STA

160 ns

Data hold time t

HD, DAT

0 150 ns

Data setup time t

SU, DAT

10 ns

Rise time for SCL signal (receiving) t

= total bus capacitance 20 80 ns

Rise time for SDA signal (receiving) t

= total bus capacitance 20 160 ns

Fall time for SCL signal (receiving) t

= total bus capacitance 20 80 ns

Fall time for SDA signal (receiving) t

= total bus capacitance 20 160 ns

Fall time for both SDA and SCL signals (transmitting) t

= total bus capacitance 20 160 ns

Setup time for STOP condition t

SU, STO

160 ns

Capacitive load for each bus line C

= total capacitance of one bus line in pF 400 pF

8 bits 40 SCL + 127 CCLK, V

= 1.8V 58.2 µsCycle time

12 bits 49 SCL + 148 CCLK, V

= 1.8V 109.7 µs

8 bits V

= 1.8V 17.17 kSPSEffective throughput

12 bits V

= 1.8V 9.12 kSPS

8 bits V

= 1.8V 120.22 kHzEquivalent rate = effective throughput × 7

12 bits V

= 1.8V 63.81 kHz

Product Folder Link(s): TSC2007

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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TIMING REQUIREMENTS: I

C High-Speed Mode (SCL = 3.4MHz)All specifications typical at – 40 ° C to +85 ° C, V

= 1.6V, unless otherwise noted.

2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SCL clock frequency f

SCL

0 3.4 MHz

Hold time (repeated) START condition t

HD, STA

160 ns

Low period of SCL clock t

LOW

160 ns

High period of the SCL clock t

HIGH

60 ns

Setup time for a repeated START condition t

SU, STA

160 ns

Data hold time t

HD, DAT

0 70 ns

Data setup time t

SU, DAT

10 ns

Rise time for SCL signal (receiving) t

= total bus capacitance 10 40 ns

Rise time for SDA signal (receiving) t

= total bus capacitance 10 80 ns

Fall time for SCL signal (receiving) t

= total bus capacitance 10 40 ns

Fall time for SDA signal (receiving) t

= total bus capacitance 10 80 ns

Fall time for both SDA and SCL signals (transmitting) t

= total bus capacitance 10 80 ns

Setup time for STOP condition t

SU, STO

160 ns

Capacitive load for each bus line C

= total capacitance of one bus line in pF 100 pF

8 bits 40 SCL + 127 CCLK, V

= 1.8V 46.5 µsCycle time

12 bits 49 SCL + 148 CCLK, V

= 1.8V 95.3 µs

8 bits V

= 1.8V 21.52 kSPSEffective throughput

12 bits V

= 1.8V 10.49 kSPS

8 bits V

= 1.8V 150.65 kHzEquivalent rate = effective throughput × 7

12 bits V

= 1.8V 73.46 kHz

Product Folder Link(s): TSC2007

TYPICAL CHARACTERISTICS

-40 -20 0 20 40 60 80 100

Temperature(°C)

Power-DownSupplyCurrent(nA)

100

V =1.6V

V =3.6V

DD V =3.0V

-40 -20 0 20 40 60 80 100

Temperature(°C)

SupplyCurrent( A)

350

300

250

200

150

100

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

600

500

400

300

200

100

SupplyCurrent( A)m

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

300

250

200

150

100

SupplyCurrent( A)m

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

T =+25 C°

I CSpeed=400kHz

PD1=PD0=0

X,Y,ZConversionat200SSPS

withMAV

TouchSensorModeledBy:

2k forX-PlaneW

2k forY-PlaneW

1k forZ(TouchResistance)W

MAVBypassed

Temperature( C)°

SupplyCurrent( A)m

-40 -20

0 20 40 60 80 100

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

250

200

150

100

3.6

SupplyCurrent( A)

High-SpeedMode=3.4MHz

FastMode=400kHz

StandardMode=100kHz

TSC2007

www.ti.com

...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

At T

= – 40 ° C to +85 ° C, V

= +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,and MAV filter enabled (see MAV Filter section), unless otherwise noted.

POWER-DOWN SUPPLY CURRENT SUPPLY CURRENTvs TEMPERATURE vs TEMPERATURE

Figure 2. Figure 3.

SUPPLY CURRENT SUPPLY CURRENTvs SUPPLY VOLTAGE (AUX Conversion) vs SUPPLY VOLTAGE

Figure 4. Figure 5.

SUPPLY CURRENT (Part Not Addressed) SUPPLY CURRENT (Part Not Addressed)vs TEMPERATURE vs SUPPLY VOLTAGE

Figure 6. Figure 7.

Product Folder Link(s): TSC2007

Temperature( C)°

Deltafrom+25 C(LSB)°

-40 -20

-2

-4

-6

200 40 60 80 100

V =1.8V

Temperature( C)°

Deltafrom+25 C(LSB)°

-40 -20

-2

-4

-6

200 40 60 80 100

V =1.8V

R ( )W

1.2 1.6 2.0 2.4 2.8 3.2

3.6

V (V)

Y+

X+

Y-

X-

-40 -20 0 20 40 60 80 100

Temperature(°C)

R(W)

Y+

X+,Y+:V =3.0VtoPin

X-,Y-:PintoGND

Y-

X-

X+

-40 -20 0 20 40 60 80 100

Temperature(°C)

R( )W

Y+

X+,Y+:V =1.8VtoPin

X ,Y :PintoGND- -

Y-

X-

X+

-40 -20 0 20 40 60 80 100

Temperature(°C)

TEMPDiodeVoltage(mV)

850

800

750

700

650

600

550

500

450

400

V =1.8V

TEMP2

94.2mV

TEMP1

MeasurementIncludes

A/DConverterOffset

andGainErrors

137.5mV

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)At T

= – 40 ° C to +85 ° C, V

= +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,and MAV filter enabled (see MAV Filter section), unless otherwise noted.

CHANGE IN GAIN CHANGE IN OFFSETvs TEMPERATURE vs TEMPERATURE

Figure 8. Figure 9.

SWITCH ON-RESISTANCE SWITCH ON-RESISTANCEvs SUPPLY VOLTAGE vs TEMPERATURE

Figure 10. Figure 11.

SWITCH ON-RESISTANCE TEMP DIODE VOLTAGEvs TEMPERATURE vs TEMPERATURE

Figure 12. Figure 13.

Product Folder Link(s): TSC2007

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

588

586

584

582

580

578

576

574

3.6

TEMP1DiodeVoltage(mV)

V =VREFDD

MeasurementIncludes

A/DConverterOffset

andGainErrors

V (V)

1.2 1.6 2.0 2.4 2.8 3.2

704

702

700

698

696

694

692

690

3.6

TEMP2DiodeVoltage(mV)

V =VREFDD

MeasurementIncludes

A/DConverterOffset

andGainErrors

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.40

3.30

3.20

3.10

3.00

2.90

2.80

2.70

0 20 40 60 80 100

V =1.2V

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.70

3.65

3.60

0 20 40 60 80 100

V =1.8V

Temperature( C)°

InternalOscillatorClockFrequency(MHz)

-40 -20

3.90

3.85

3.80

3.75

3.70

0 20 40 60 80 100

V =3.0V

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

TYPICAL CHARACTERISTICS (continued)At T

= – 40 ° C to +85 ° C, V

= +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, non-continuous AUX measurement,and MAV filter enabled (see MAV Filter section), unless otherwise noted.

TEMP1 DIODE VOLTAGE TEMP2 DIODE VOLTAGEvs SUPPLY VOLTAGE vs SUPPLY VOLTAGE

Figure 14. Figure 15.

INTERNAL OSCILLATOR CLOCK FREQUENCY INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE vs TEMPERATURE

Figure 16. Figure 17.

INTERNAL OSCILLATOR CLOCK FREQUENCYvs TEMPERATURE

Figure 18.

Product Folder Link(s): TSC2007

OVERVIEW

X+

Y+

X-

Y-

AuxiliaryInput GND

TSC2007

GND

1 Fm0.1 Fm

Touch

Screen

GPIO

SDA

SCL

Host

Processor

PENIRQ

SDA

SCL

VDD/REF

AUX

GND

1.2kW1.2kW

1.8VDC

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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The TSC2007 is an analog interface circuit for a human interface touch screen device. All peripheral functionsare controlled through the command byte and onboard state machines. The TSC2007 features include:•Very low-power touch screen controller•Very small onboard footprint•Relieves host from tedious routine tasks by preprocessing, thus saving resources for more critical tasks•Ability to work on very low supply voltage•Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required•Miniature, yet complete; requires no external supporting component•Enhanced electrostatic discharge (ESD) protection

The TSC2007 consists of the following blocks (refer to the block diagram on the front page):•Touch Screen Sensor Interface•Auxiliary Input (AUX)•Temperature Sensor•Acquisition Activity Preprocessing•Internal Conversion Clock•I

C Interface

Communication with the TSC2007 is done via an I

C serial interface. The TSC2007 is an I

C slave device;therefore, data are shifted into or out of the TSC2007 under control of the host microprocessor, which alsoprovides the serial data clock.

Control of the TSC2007 and its functions is accomplished by writing to the command register of an internal statemachine. A simple command protocol compatible with I

C is used to address this register.

A typical application of the TSC2007 is shown in Figure 19 .

Figure 19. Typical Circuit Configuration

Product Folder Link(s): TSC2007

TOUCH SCREEN OPERATION

4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT

ConductiveBar

InsulatingMaterial(Glass)

Silver

Ink

TransparentConductor(ITO)

BottomSide

Transparent

Conductor(ITO)

TopSide

X+

X-

Y+

Y-

ITO=IndiumTinOxide

RTOUCH +RX−plate @XPosition

4096 ǒZ2

Z1*1Ǔ

(1)

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

A resistive touch screen operates by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). Thechange in the resistance ratio marks the location on the touch screen.

The TSC2007 supports resistive 4-wire configurations, as shown in Figure 20 . The circuit determines location intwo coordinate pair dimensions, although a third dimension can be added for measuring pressure.

A 4-wire touch screen is typically constructed as shown in Figure 20 . It consists of two transparent resistivelayers separated by insulating spacers.

Figure 20. 4-Wire Touch Screen Construction

The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of theY position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+and Y – drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by thevoltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+lead does not affect the conversion because of the high input impedance of the A/D converter.

Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X positionon the screen. This process provides the X and Y coordinates to the associated processor.

Measuring touch pressure (Z) can also be done with the TSC2007. To determine pen or finger touch, thepressure of the touch must be determined. Generally, it is not necessary to have very high performance for thistest; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations are shown using the12-bit resolution mode). There are several different ways of performing this measurement. The TSC2007supports two methods. The first method requires knowing the X-plate resistance, the measurement of theX-position, and two additional cross panel measurements (Z

and Z

) of the touch screen (see Figure 21 ).Equation 1 calculates the touch resistance:

Product Folder Link(s): TSC2007

RTOUCH +RX−plate @XPosition

4096 ǒ4096

Z1*1Ǔ*RY−plate @ǒ1*YPosition

4096 Ǔ

(2)

X-Position

MeasureX-Position

MeasureZ -Position

Touch

X+ Y+

X-Y-

Z -Position

Touch

X+ Y+

Y-X-

MeasureZ -Position

Z -Position

Touch

X+ Y+

Y-X-

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position andY-position, and Z

.Equation 2 also calculates the touch resistance:

Figure 21. Pressure Measurement

When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across thetouch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result ofmechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.This settling time must be accounted for, or else the converted value is incorrect. Therefore, a delay must beintroduced between the time the driver for a particular measurement is turned on, and the time a measurement ismade.

In some applications, external capacitors may be required across the touch screen for filtering noise picked up bythe touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of thesecapacitors provides a low-pass filter to reduce the noise, but creates an additional settling time requirement whenthe panel is touched. The settling time typically shows up as gain error.

To solve this problem, the TSC2007 can be commanded to turn on the drivers only, without performing aconversion. Time can then be allowed to perform a conversion before the command is issued.

The TSC2007 touch screen interface can measure position (X,Y) and pressure (Z).

Product Folder Link(s): TSC2007

INTERNAL TEMPERATURE SENSOR

Converter

GND

VDD

TEMP1

TEMP2

+IN

-IN

DV+kT

q@ln(N)

(3)

T+q@DV

k@ln(N)

(4)

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

In some applications, such as battery recharging, an ambient temperature measurement is required. Thetemperature measurement technique used in the TSC2007 relies on the characteristics of a semiconductorjunction operating at a fixed current level. The forward diode voltage (V

) has a well-defined characteristicversus temperature. The ambient temperature can be predicted in applications by knowing the +25 ° C value ofthe V

voltage and then monitoring the delta of that voltage as the temperature changes.

The TSC2007 offers two modes of temperature measurement. The first mode requires calibration at a knowntemperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown inFigure 22 , is used during this measurement cycle. This voltage is typically 580mV at +25 ° C with a 10 µA current.The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (T

) of thisvoltage is very consistent at – 2.1mV/ ° C. During the final test of the end product, the diode voltage would bestored at a known room temperature, in system memory, for calibration purposes by the user. The result is anequivalent temperature measurement resolution of 0.35 ° C/LSB (1LSB = 732 µV with V

REF

= 3.0V).

Figure 22. Functional Block Diagram of Temperature Measurement Mode

The second mode does not require a test temperature calibration, but uses a two-measurement (differential)method to eliminate the need for absolute temperature calibration and for achieving 2 ° C/LSB accuracy. Thismode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times largerthan the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion isrepresented by:

Where:

N = the resistance ratio = 91.k = Boltzmann's constant = 1.3807 × 10

– 23

J/K (joules/kelvins).q = the electron charge = 1.6022 × 10

– 19

C (coulombs).T = the temperature in kelvins (K).

This method can provide a much improved absolute temperature measurement, but a lower resolution of1.6 ° C/LSB. The resulting equation to solve for T is:

Where:

ΔV = V

(TEMP2) – V

(TEMP1) (in mV)

∴T = 2.573 ⋅ΔV (in K)

or T = 2.573 ⋅ΔV – 273 (in ° C)

Temperature 1 and temperature 2 measurements have the same timing as the other data acquisition cyclesshown in Figure 33 and Figure 34 .

Product Folder Link(s): TSC2007

ANALOG-TO-DIGITAL CONVERTER

Converter

-REF

+REF

+IN

-IN

PenTouch

Control

Logic

C3-C0

MAV

VDD

GND

TEMP1

TEMP2

RIRQ 90kW50kW

AUX

GND

X+

X-

Y+

Y-

VDD/REF PENIRQ

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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Figure 23 shows the analog inputs of the TSC2007. The analog inputs (X, Y, and Z touch panel coordinates, chiptemperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR)A/D converter. The A/D architecture is based on capacitive redistribution architecture, which inherently includes asample-and-hold function.

Figure 23. Analog Input Section (Simplified Diagram)

A unique configuration of low on-resistance switches allows an unselected A/D converter input channel toprovide power and an accompanying pin to provide ground for driving the touch panel. By maintaining adifferential input to the converter and a differential reference input architecture, it is possible to negate errorscaused by the driver switch on-resistance.

Product Folder Link(s): TSC2007

Reference

Reference Mode

Converter

+IN +REF

Y+

VDD/REF

X+

Y-

GND

-REF

-IN

Converter

+IN +REF

Y+

VDD/REF

X+

Y-

GND

-REF

-IN

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

The TSC2007 uses an external voltage reference that is applied to the VDD/REF pin. The upper referencevoltage range is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V, single-supplyoperation of the chip.

There is a critical item regarding the reference when making measurements while the switch drivers are on. Forthis discussion, it is useful to consider the basic operation of the TSC2007 (see Figure 19 ). The application usedin the following example shows the device being used to digitize a resistive touch screen. If the touch screencontroller uses a single-ended reference mode, as shown in Figure 24 , a measurement of the current Y positionof the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y – drivers,and digitizing the voltage on X+. For this measurement, the resistance in the X+ lead does not affect theconversion; it does affect the settling time, but the resistance is usually small enough that this timing is not aconcern. However, because the resistance between Y+ and Y – is fairly low, the on-resistance of the Y driversdoes make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V inputor a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lostacross the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of thetouch screen, providing an additional source of error. Therefore, the TSC2007 does not support single-endedreference mode.

Figure 24. Simplified Diagram of Single-Ended Reference

This situation is resolved, as shown in Figure 25 , by using the differential mode; the +REF and – REF inputs areconnected directly to Y+ and Y – , respectively. This mode makes the A/D converter ratiometric. The result of theconversion is always a percentage of the external reference, regardless of how it changes in relation to theon-resistance of the internal switches.

Figure 25. Simplified Diagram of Differential Reference(Both Y Switches Enabled, X+ is Analog Input)

Product Folder Link(s): TSC2007

Touch Screen Settling

Variable Resolution

8-Bit Conversion

Conversion Clock and Conversion Time

Data Format

OutputCode

FS=Full-ScaleVoltage=VREF

(1)

1LSB=V /4096

REF

(1)

FS 1LSB-

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

InputVoltage (V)

(2)

TSC2007

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In some applications, external capacitors may be required across the touch screen to filter noise picked up by thetouch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide alow-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched.The settling time typically shows up as a gain error. The problem is that the input and/or reference has notsettled to its final steady-state value before the A/D converter samples the input(s) and provides the digitaloutput. Additionally, the reference voltage may continue to change during the measurement cycle.

To resolve these settling-time problems, the TSC2007 can be commanded to turn on the drivers only withoutperforming a conversion (see Table 3 ). Time can then be allowed, before the command is issued, to perform aconversion. Generally, the time it takes to communicate the conversion command over the I

C bus is adequatefor the touch screen to settle.

The TSC2007 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often practicalfor measuring slow changing signals such as touch pressure. Performing the conversions at lower resolutionreduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowerspower consumption.

The TSC2007 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed,and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, aconversion result can be read by transferring only one data byte. The internal clock runs twice as fast at 4MHz.

The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewerclock cycles and provides lower power consumption.

The TSC2007 contains an internal clock, which drives the state machines inside the device that perform themany functions of the part. This clock is divided down to provide a clock that runs the A/D converter. Thefrequency of this clock is 4MHz clock for 8-bit mode, and 2MHz for the 12-bit mode.

The TSC2007 output data are in straight binary format as shown in Figure 26 . This figure shows the ideal outputcode for the given input voltage and does not include the effects of offset, gain, or noise.

(1) Reference voltage at converter: +REF – ( – REF). See Figure 23 .(2) Input voltage at converter, after multiplexer: +IN – ( – IN). See Figure 23 .

Figure 26. Ideal Input Voltages and Output Codes

Product Folder Link(s): TSC2007

Touch Detect

GND

TEMP1

TEMP2

VDD

PenTouch

X+

Y+

Y-

HighwhentheX+orY+

driverison,orwhenany

sensorconnection/short-

circuittestsareactivated.

GND

Sense

Viasgotosystemanaloggroundplane.

GND

Highwhen

theX+orY+

driverison.

Control

Logic

RIRQ

VDD/REF

PENIRQ

Connectto

AnalogSupply

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

The PENIRQ can be used as an interrupt to the host. R

IRQ

is an internal pull-up resistor with a programmablevalue of either 50k Ω(default) or 90k Ω. Write command '1011' (setup command) followed by data '0001' sets thepull-up to 90k Ω.NOTE: The first three bits must be '0's and the select bit is the last bit. To change the pull-upback to 50k Ω, issue write command '1011' followed by data '0000'.

An example for the Y-position measurement is detailed in Figure 27 . The PENIRQ output is pulled high by aninternal pull-up. While in power-down mode with PD0 = 0, the Y – driver is on and connected to GND, and thePENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to groundthrough the touch screen, and the PENIRQ output goes low because of the current path through the panel toGND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-position, the X+input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current fromflowing through the touch screen, thus causing no errors.

In addition to the measurement cycles for X-, Y-, and Z-position, commands that activate the X-drivers, Y-drivers,and Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQpull-down transistor, and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Underthese conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to theTSC2007 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel istouched. In order to re-enable the pen-interrupt output function under these circumstances, a command bytemust be written to the TSC2007 with PD0 = 0.

When the bus master sends the address byte with the R/ W bit = 0, and the TSC2007 sends an acknowledge, thepen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then thepen-interrupt function is enabled at the end of a conversion. This action is approximately 100 µs (12-bit mode) or50 µs (8-bit mode) after the TSC2007 receives a STOP/START condition, following the receipt of a commandbyte (see Figure 31 and Figure 30 for further details about when the conversion cycle begins).

In both cases previously listed, it is recommended that whenever the host writes to the TSC2007, the masterprocessor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts whenthe PENIRQ line is disabled in the cases previously listed.

Figure 27. Example of a Pen-Touch Induced Interrupt via the PENIRQ Pin

Product Folder Link(s): TSC2007

Preprocessing

7Acquired

Data

7m asue rementsinput

intotemporaryarray

Sortby

descendingorder

Averagingoutp tu

fromwindowof3

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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The TSC2007 has a combined MAV filter (median value filter and averaging filter).

MAV Filter

If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate thedata without noise. In this case, the median value filter operation helps remove the noise. The array of sevenconverted results is sorted first. The middle three values are then averaged to produce the output value of theMAV filter.

The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperaturemeasurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter maybe bypassed through the setup command; see Table 3 and Table 4 .

Figure 28. MAV Filter Operation (Patent Pending)

Product Folder Link(s): TSC2007

C INTERFACE

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

The TSC2007 supports the I

C serial bus and data transmission protocol in all three defined modes: standard,fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receivingdata as a receiver. The device that controls the message is called a master. The devices that are controlled bythe master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),controls the bus access, and generates the START and STOP conditions. The TSC2007 operates as a slave onthe I

C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.

The following bus protocol has been defined (see Figure 29 ):•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the dataline while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy — Both data and clock lines remain HIGH.

Start Data Transfer — A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,defines a START condition.

Stop Data Transfer — A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,defines the STOP condition.

Data Valid — The state of the data line represents valid data, when, after a START condition, the data line isstable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a START condition and terminated with a STOP condition. The numberof data bytes transferred between START and STOP conditions is not limited and is determined by themaster device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.Within the I

C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock rate),and a high-speed mode (1.7MHz or 3.4MHz clock rate) are each defined. The TSC2007 works in all threemodes.

Acknowledge — Each receiving device, when addressed, is obliged to generate an acknowledge after thereception of each byte. The master device must generate an extra clock pulse that is associated with thisacknowledge bit.A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course,setup and hold times must be taken into account. A master must signal an end of data to the slave by notgenerating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, theslave must leave the data line HIGH to enable the master to generate the STOP condition.

Product Folder Link(s): TSC2007

C Fast or Standard Mode (F/S Mode)

SDA

SCL

1 2 76 8 9 1 2 3-8 8 9

SlaveAddress

MSB

RepeatedIfMoreBytesAreTransferred

R/W

DirectionBit

Acknowledgement

SignalfromReceiver

Acknowledgement

SignalfromReceiver

START

Condition

ACK ACK

STOPCondition

orRepeated

STARTCondition

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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Figure 29 details how data transfer is accomplished on the I

C bus. Depending upon the state of the R/ W bit, twotypes of data transfer are possible:1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is theslave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slaveaddress and each received byte.2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, istransmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes aretransmitted by the slave to the master. The master returns an acknowledge bit after all received bytes otherthan the last byte. At the end of the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer endswith a STOP condition or a repeated START condition. Because a repeated START condition is also thebeginning of the next serial transfer, the bus is not released.

The TSC2007 may operate in the following two modes:1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte isreceived, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginningand end of a serial transfer. Address recognition is performed by hardware after reception of the slaveaddress and direction bit.2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receivermode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data aretransmitted on SDA by the TSC2007 while the serial clock is input on SCL. START and STOP conditions arerecognized as the beginning and end of a serial transfer.

In I

C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Informationsection.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with aSTART condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master hasfinished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transitionon SDA while SCL is high, as shown in Figure 29 . The bus is free for another transmission after a STOPcondition has occurred. Figure 29 shows the complete F/S mode transfer on the I

C, 2-wire serial interface. Theaddress byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDAstate is only allowed to change while SCL is low, except for the START and STOP conditions. Data aretransmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit wordplus acknowledge bit).

Figure 29. Complete Fast- or Standard-Mode Transfer

Product Folder Link(s): TSC2007

C High-Speed Mode (Hs Mode)

8-BitMasterCode00001xxx

IfPthen

FastorStandardMode

IfSr(dottedlines)

thenHigh-SpeedMode

1 6 7 8 92to5

2to51 6 7 8 9 1 6 7 8 9

2to5

SDA

SCL

SDA

SCL

=CurrentSourcePull-Up

=ResistorPull-Up

A=Acknowledge(SD LOWA )

N=NotAckno ledgew (SDAHIGH)

S START= Condition

P=STOP Con iiond t

Sr=RepeatedSTAR CondT iti no

NtH

High-SpeedMode

FastorStandardMode

tFS

Sr P

7-BitSlaveAddress R/WA nx(8-BitDATA + A/N)

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

The TSC2007 can operate with high-speed I

C masters. To do so, the pull-up resistor on SCL must be changedto an active pull-up, as recommended in the I

C specification.

Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I

C busspecification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:1. START condition (S)2. 8-bit master code (00001xxx)3. Not-acknowledge bit (N)

Figure 30 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only fortriggering Hs mode, and are not to be used for slave addressing or any other purpose. The master codeindicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet theHs mode specification. Because no device is allowed to acknowledge the master code, the master code isfollowed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches toHs-mode and enables the current-source pull-up circuit for SCL (at time t

shown in Figure 30 ). Because otherdevices can delay the serial transfer before t

by stretching the LOW period of SCL, the master enables thecurrent-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thusspeeding up the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/ W bitaddress, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) conditionand after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-upcircuit. This disabling enables other devices, such as the TSC2007, to delay the serial transfer (until theconverted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The masterre-enables its current-source pull-up circuit again when all devices have released SCL, and SCL reaches a HIGHlevel, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S modeafter a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link anumber of Hs mode transfers, separated by repeated START conditions (Sr).

Figure 30. Complete High-Speed Mode Transfer

Product Folder Link(s): TSC2007

DIGITAL INTERFACE

ADDRESS BYTE

COMMAND BYTE

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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The TSC2007 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset tocomply with the I

C standard for A/D converters and are always set at '10010'. The logic state of the addressinput pins (A1-A0) determines the two LSBs of the device address to activate communication. Therefore, amaximum of four devices with the same preset code can be connected on the same bus at one time.

The A1-A0 address inputs are read whenever an address byte is received, and should be connected to thesupply pin (VDD/REF) or the ground pin (GND). The slave address is latched into the TSC2007 on the fallingedge of SCL after the read/write bit has been received by the slave.

The last bit of the address byte (R/ W) defines the operation to be performed. When set to a '1', a read operationis selected; when set to a ‘ 0 ’ , a write operation is selected. Following the START condition, the TSC2007monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, theappropriate device select bits, and the R/ W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 1. I

C Slave Address Byte

MSB LSBD7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 A1 A0 R/ W

Bit D0: R/ W

1: I

C master read from TSC (I

C read addressing).

0: I

C master write to TSC (I

C write addressing).

Table 2. Command Byte Definition (Excluding the Setup Command)

(1)

BIT NAME DESCRIPTION

D7-D4 C3-C0 All Converter Function Select bits as detailed in Table 3 , except for the setup command ('1011').00: Power down between cycles. PENIRQ enabled.01: A/D converter on. PENIRQ disabled.D3-D2 PD1-PD0

10: A/D converter off. PENIRQ enabled.11: A/D converter on. PENIRQ disabled.0: 12-bit (Lower speed referred to as the 2MHz clock).D1 M

1: 8-bit (Higher speed referred to as the 4MHz clock).D0 X Don't care.

(1) The command byte definition for the setup command is shown in Table 4 .

Bits D7-D4: C3-C0 — Converter function select bits. These bits select the input to be converted and the converterfunction to be executed, activate the drivers, and configure the PENIRQ pull-up resistor (R

IRQ

). Table 3 lists thepossible converter functions.

Bits D3-D2: PD1-PD0 — Power-down bits. These two bits select the power-down mode that the TSC2007 will bein after the current command completes, as shown in Table 2 .

It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. Ifmultiple X-, Y-, and Z-position measurements will be done one right after another (such as when averaging), PD0=1 will leave the touch screen drivers on at the end of each conversion cycle.

Bit D1: M — Mode bit. If M = 0, the TSC2007 is in 12-bit mode. If M = 1, 8-bit mode is selected.

Bit D0: X — Don ’ t care.

Product Folder Link(s): TSC2007

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

When the TSC2007 powers up, the power-down bits must be written to ensure that the device is placed into themode that achieves the lowest power. Therefore, immediately after power-up, send a command byte that setsPD1 = PD0 = 0, so that the device will be in the lowest power mode, powering down between conversions.

Table 3. Converter Function Select

INPUT TOA/D REFERENCEC3 C2 C1 C0 FUNCTION CONVERTER X-DRIVERS Y-DRIVERS ACK MODE

0 0 0 0 Measure TEMP0 TEMP0 OFF OFF Y Single-Ended0 0 0 1 Reserved N/A OFF OFF N Single-Ended0 0 1 0 Measure AUX AUX OFF OFF Y Single-Ended0 0 1 1 Reserved N/A OFF OFF N Single-Ended0 1 0 0 Measure TEMP1 TEMP1 OFF OFF Y Single-Ended0 1 0 1 Reserved N/A OFF OFF N Single-Ended0 1 1 0 Reserved N/A OFF OFF N Single-Ended0 1 1 1 Reserved N/A OFF OFF N Single-Ended1 0 0 0 Activate X-drivers N/A ON OFF Y Differential1 0 0 1 Activate Y-drivers N/A OFF ON Y Differential1 0 1 0 Activate Y+, X-drivers N/A X – ON Y+ ON Y Differential1 0 1 1 Setup command

(1)

N/A OFF OFF N N/A1 1 0 0 Measure X position Y+ ON OFF Y Differential1 1 0 1 Measure Y position X+ OFF ON Y Differential1 1 1 0 Measure Z1 position X+ X – ON Y+ ON Y Differential1 1 1 1 Measure Z2 position Y – X – ON Y+ ON Y Differential

(1) The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, exceptfor the power-on reset. The default value for these bits after power-on reset is 0000. Table 4 shows the definition of these data bits.

Table 4. Command Byte Definition for the Setup Command

BIT NAME DESCRIPTION

D7-D4 C3-C0 = '1011' Setup command; must write '1011'.D3-D2 PD1-PD0 = '00' Reserved; must write '00'.0: Use the onboard MAV filter (default).D1 Filter control

1: Bypass the onboard MAV filter.0: R

IRQ

= 50k Ω(default).D0 PENIRQ pull-up resistor (R

IRQ

) select

1: R

IRQ

= 90k Ω.

Product Folder Link(s): TSC2007

START A CONVERTER FUNCTION/WRITE CYCLE

SDA

SCL

10 0 1 0

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

AddressByte CommandByte

Acquisition Conversion

STOPor

RepeatedSTART

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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A conversion/write cycle begins when the master issues the address byte containing the slave address of theTSC2007, with the eighth bit equal to a 0 (R/ W = 0), as shown in Table 1 . Once the eighth bit has been received,and the address matches the A1-A0 address input pin setting, the TSC2007 issues an acknowledge.

When the master receives the acknowledge bit from the TSC2007, the master writes the command byte to theslave (see Table 2 ). After the command byte is received by the slave, the slave issues another acknowledge bit.The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in Figure 31 .

Figure 31. Complete I

C Serial Write Transmission

If the master sends additional command bytes after the initial byte, but before sending a STOP or repeatedSTART condition, the TSC2007 does not acknowledge those bytes.

The input multiplexer channel for the A/D converter is selected when bits C3 through C0 are clocked in. If theselected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisitionperiod begins.

When R/ W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of thecommand byte has been latched, and ends when a STOP or repeated START condition has been issued. A/Dconversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter aredisabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respectivetouch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 31 .

Product Folder Link(s): TSC2007

READ A CONVERSION/READ CYCLE

SDA

SCL

10 0 1 0 A1 A0

R/W

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 0 00 0 1

START TSC2007

ACK

MASTER

ACK

MASTER

NACK

STOPor

Repeated

START

AddressByte DataByte1 DataByte2

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

For best performance, the I

C bus should remain in an idle state while an A/D conversion is taking place. Thisidling prevents digital clock noise from affecting the bit decisions being made by the TSC2007. The mastershould wait for at least 10 µs before attempting to read data from the TSC2007 to realize this best performance.However, the master does not need to wait for a completed conversion before beginning a read from the slave, iffull 12-bit performance is not necessary.

Data access begins with the master issuing a START condition followed by the address byte (see Table 1 ) withR/ W = 1.

When the eighth bit has been received and the address matches, the slave issues an acknowledge. The firstbyte of serial data then follows (D11-D4, MSB first).

After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master toindicate that the last data byte has been received. If the master somehow acknowledges the second data byte,invalid data are returned (FFh). This condition applies to both 12-and 8-bit modes. See Figure 32 for a completeI

C read transmission.

Figure 32. Complete I

C Serial Read Transmission

Product Folder Link(s): TSC2007

THROUGHPUT RATE AND I

C BUS TRAFFIC

12-Bit Operation

8-Bit Operation

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus ismuch lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. Thethroughput is further limited by the I

C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bitresolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I

C bandwidth for thesystem to use on other devices.

Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For V

= 1.2V, the frequencyreduces to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.

For 12-bit operation, sending the conversion result across the I

C bus takes 49 bus clocks (SCL clock). Eachwrite cycle takes 20 I

C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycletakes 29 I

C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Sevensample-and-conversions take 19 x 7 internal clocks to complete. The MAV filter loop requires 19 internal clocks.For V

= 1.2V, the complete processed data cycle time calculations are shown in Table 5 . Because the firstacquisition cycle overlaps with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For12-bit mode, (19 × 7 + 19) – 4 = 148 CCLKs plus I/O are required.

For 8-bit operation, sending the conversion result across the I

C bus takes 40 bus clocks (SCL clock). Each writecycle takes 20 I

C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 20I

C cycles (START, STOP, address byte, 2 ACKs, and data byte 1). Seven sample-and-conversions takes 16 x 7internal clocks to complete. The MAV filter loop requires 19 internal clocks. For V

= 1.2V, the completeprocessed data cycle time calculations are shown in Table 5 . Because the first acquisition cycle overlaps with theI/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 8-bit mode, (16 × 7 + 19) – 4 = 127CCLKs plus I/O are required.

Table 5. Measurement Cycle Time Calculations

STANDARD MODE: 100kHz (Period = 10 µs)

8-Bit 40 × 10 µs + 127 × 313ns = 439.8 µs (2.27kSPS through the I

C bus)12-Bit 49 × 10 µs + 148 × 625ns = 582.5 µs (1.72kSPS through the I

C bus)

FAST MODE: 400kHz (Period = 2.5 µs)

8-Bit 40 × 2.5 µs + 127 × 313ns = 139.8 µs (7.15kSPS through the I

C bus)12-Bit 49 × 2.5 µs + 148 × 625ns = 215 µs (4.65kSPS through the I

C bus)

HIGH-SPEED MODE: 1.7MHz (Period = 588ns)

8-Bit 40 × 588ns + 127 × 313ns = 63.3 µs (15.79kSPS through the I

C bus)12-Bit 49 × 588ns + 148 × 625ns = 121.3 µs (8.24kSPS through the I

C bus)

HIGH-SPEED MODE: 3.4MHz (Period = 294ns)

8-Bit 40 × 294ns + 127 × 313ns = 51.6 µs (19.39kSPS through the I

C bus)12-Bit 49 × 294ns + 148 × 625ns = 106.9 µs (9.35kSPS through the I

C bus)

As an example, use V

= 1.2V and 12-bit mode with the Fast-mode I

C clock (f

SCL

= 400kHz). The equivalentTSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =32.55kSPS). The supply current to the TSC for this rate and configuration is 128 µA. To achieve an equivalentsample throughput of 8.2kSPS using the device without preprocessing, the TSC2007 consumes only (8.2/32.55)× 128 µA = 32.24 µA.

Product Folder Link(s): TSC2007

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

Table 6. Effective and Equivalent Throughput RatesTSCCONVERSION EFFECTIVE EQUIVALENT NO. NO. CCLKSUPPLY I

C BUS SPEED CYCLE TIME THROUGHPUT THROUGHPUT OF OF f

CCLK

PERIODSVOLTAGE (f

SCL

) RESOLUTION ( µs) (kSPS) (kSPS) SCL CCLK (kHz) (ns)

8-bit 433.6 2.31 16.14 40 127 3780 264.6100kHz

Standard

12-bit 568.7 1.76 12.31 49 148 1880 531.9

8-bit 133.6 7.49 52.40 40 127 3780 264.6400kHz

Fast

12-bit 201.2 4.97 34.79 49 148 1880 531.92.7V

8-bit 57.1 17.50 122.53 40 127 3780 264.61.7MHz

High-Speed

12-bit 107.5 9.30 65.09 49 148 1880 531.9

8-bit 45.4 22.04 154.31 40 127 3780 264.63.4MHz

High-Speed

12-bit 93.1 10.74 75.16 49 148 1880 531.9

8-bit 434.7 2.30 16.10 40 127 3660 273.2100kHz

Standard

12-bit 570.9 1.75 12.26 49 148 1830 546.4

8-bit 134.7 7.42 51.97 40 127 3660 273.2400kHz

Fast

12-bit 203.4 4.92 34.42 49 148 1830 546.41.8V

8-bit 58.2 17.17 120.22 40 127 3660 273.21.7MHz

High-Speed

12-bit 109.7 9.12 63.81 49 148 1830 546.4

8-bit 46.5 21.52 150.65 40 127 3660 273.23.4MHz

High-Speed

12-bit 95.3 10.49 73.46 49 148 1830 546.4

8-bit 439.8 2.27 15.92 40 127 3190 313.5100kHz

Standard

12-bit 582.5 1.72 12.02 49 148 1600 625.0

8-bit 139.8 7.15 50.07 40 127 3190 313.5400kHz

Fast

12-bit 215.0 4.65 32.56 49 148 1600 625.01.2V

8-bit 63.3 15.79 110.51 40 127 3190 313.51.7MHz

High-Speed

12-bit 121.3 8.24 57.70 49 148 1600 625.0

8-bit 51.6 19.39 135.72 40 127 3190 313.53.4MHz

High-Speed

12-bit 106.9 9.35 65.47 49 148 1600 625.0

Product Folder Link(s): TSC2007

Acquisition1

6SCLs

Conversion1

15CCLKs

STOPor

REPEATEDSTART()

Conversion2

15CCLKs

Conversion7

15CCLKs

MAVFilter

19CCLKs

Acquisition2

4CCLKs

148CCLKs(FilterisEnabled,12-BitMode)

SDA

SCL

10 0 10

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

TSC2007

ACK

CCLK

AddressByte CommandByte

10 0 1 0

A1 A0 0

R/W

AddressByte

I CWrite

2I C

2Read

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 000 0 1

DataByte1

MASTER

ACK

MASTER

NACK

STOPor

REPEATEDSTART

DataByte2

ClockStretched

Acquisition1

6SCLs

Conversion1

15CCLKs

STOPor

REPEATEDSTART()

15CCLKs(FilterisDisabled,12-BitMode)

SDA

SCL

10 0 1 0

A1 A0

R/W

0C3 C2 C1 C0 PD1 PD0 M X 0

START

TSC2007

ACK

TSC2007

ACK

TSC2007

ACK

ClockStretched

CCLK

AddressByte CommandByte

10 0 1 0

A1 A0 0

R/W

AddressByte

D11 D10 D9 D8 D7 D6 D5 D4 0

D3 D2 D1 D0 000 0 1

DataByte1

MASTER

ACK

MASTER

NACK

STOPor

REPEATEDSTART

DataByte2

I C

2Write I C

2Read

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ..................................................................................................................................................................................................................................................

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Figure 33. Data Acquisition Cycle (Filter Enabled)

Figure 34. Data Acquisition Cycle (Filter Disabled)

Product Folder Link(s): TSC2007

POWER-ON RESET (POR)

1.2Vto3.6V

0.9V

0.3V

VDD

tVDD_OFF_RAMP

tVDD_OFF

tVDD_ON_RAMP

Temperature( C)°

V OffTimeforValidPOR(s)

-40 -20

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0 20 40 60 80 100

RecommendedV OffTime

forT = 40 Cto+85 C- ° °

TypicalV OffTimeforVariousTemperatures

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

During TSC2007 power-up, an internal power-on reset (POR) is automatically implemented. The POR brings theTSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I

C address. TheTSC2007 senses the power-up curve to decide whether or not to implement a POR.

It is required to follow the power-on/off slope and interval requirements, as provided in the ElectricalCharacteristics , in order to ensure a proper POR of the TSC2007.

Figure 35. Power-On Reset Timing

Table 7. Timing Requirements for Figure 35PARAMETER TEST CONDITIONS MIN MAX UNIT

off ramp T

= – 40 ° C to +85 ° C 2 kV/s

= – 40 ° C to +85 ° C, V

= 0V 1.2 sV

off time

= – 20 ° C to +85 ° C, V

= 0V 0.3 s

on ramp T

= – 40 ° C to +85 ° C 12 kV/s

Figure 36. V

Off Time vs Temperature

Product Folder Link(s): TSC2007

LAYOUT

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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The following layout suggestions should obtain optimum performance from the TSC2007. Keep in mind thatmany portable applications have conflicting requirements for power, cost, size, and weight. In general, mostportable devices have fairly clean power and grounds because most of the internal components are very lowpower. This situation would mean less bypassing for the converter power and less concern regarding grounding.However, each situation is unique and the following suggestions should be reviewed carefully.

For optimum performance, care should be taken with the physical layout of the TSC2007 circuitry. The basicSAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,and digital inputs that occur immediately before latching the output of the analog comparator. Therefore, duringany single conversion for an n-bit SAR converter, there are nwindows in which large external transient voltagescan easily affect the conversion result. Such glitches might originate from switching power supplies, nearbydigital logic, and high power devices. The degree of error in the digital output depends on the reference voltage,layout, and the exact timing of the external event. The error can change if the external event changes in timewith respect to the SCL input.

With this consideration in mind, power to the TSC2007 should be clean and well-bypassed. A 0.1 µF ceramicbypass capacitor should be placed as close to the device as possible. In addition, a 1 µF to 10 µF capacitor mayalso be needed if the impedance of the connection between VDD/REF and the power supply is high.

A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by aninternal op amp. If an external reference voltage originates from an op amp, make sure that it can drive anybypass capacitor that is used without oscillation.

The TSC2007 architecture offers no inherent rejection of noise or voltage variation with regard to using anexternal reference input, which is of particular concern when the reference input is tied to the power supply. Anynoise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filteredout, voltage variation because of line frequency (50Hz or 60Hz) can be difficult to remove. Some packageoptions have pins labeled as VOID. Avoid any active trace going under any pin marked as VOID unless it isshielded by a ground or power plane.

The GND pin should be connected to a clean ground point. In many cases, this point is the analog ground. Avoidconnections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run aground trace directly from the converter to the power-supply entry or battery connection point. The ideal layoutincludes an analog ground plane dedicated to the converter and associated analog circuitry.

In the specific case of use with a resistive touch screen, care should be taken with the connection between theconverter and the touch screen. Resistive touch screens have fairly low resistance; therefore, the interconnectionshould be as short and robust as possible. Loose connections can be a source of error when the contactresistance changes with flexing or vibrations.

As indicated previously, noise can be a major source of error in touch-screen applications (for example,applications that require a back-lit LCD panel). This electromagnetic interfence (EMI) noise can be coupledthrough the LCD panel to the touch screen and cause flickering of the converted A/D converter data. Severalthings can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connectedto ground, which couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y – , X+, andX – to ground, can also help. Note, however, that the use of these capacitors increases screen settling time andrequires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screensensor used. The PENIRQ pull-up resistor (R

IRQ

) may be adequate for most of sensors.

Product Folder Link(s): TSC2007

TSC2007

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...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

Revision History

Changes from Original (March 2007) to Revision A ....................................................................................................... Page

•Added IEC discharge information to Absolute Maximum Ratings table ................................................................................ 2•Added Power On/Off Slope Requirements section to Electrical Characteristics ................................................................... 4•Added pin 1 identifier to YZG pinout drawing ........................................................................................................................ 5•Changed t

to t

in Timing Requirements tables .................................................................................................................. 6•Changed Fall time for both SDA and SCL signals from 10 (min) and 80 (max) to 20 (min) and 160 (max) in TimingRequirements table for High-Speed mode ............................................................................................................................ 7•Changed resistance ratio from 80 to 91 in the Internal Temperature Sensor section ......................................................... 15•Changed Tresult from 2.648 to 2.573 (because of change to resistance ratio) ................................................................. 15•Added text to clarify temperature 1 and 2 measurement timings in last sentence on page ................................................ 15•Changed text in Reference mode to clarify singled-ended operation .................................................................................. 17•Changed Figure 27 caption text from PINTDAV to PENIRQ ............................................................................................... 19•Added " patent pending " to Figure 28 ................................................................................................................................... 20•Added subsections to Throughput Rate and I2C Bus Traffic section to clarify 8- and 12-bit operation .............................. 28•Added Power-On Reset section .......................................................................................................................................... 31

Product Folder Link(s): TSC2007

MECHANICAL DATA

TSC2007

SBAS405A – MARCH 2007 – REVISED MARCH 2009 ......................................................................................................................................................

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Product Folder Link(s): TSC2007

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TSC2007IPW ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples

TSC2007IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples

TSC2007IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TSC2007IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TSC2007IYZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM Purchase Samples

TSC2007IYZGT ACTIVE DSBGA YZG 12 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM Request Free Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2011

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TSC2007IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TSC2007IYZGR DSBGA YZG 12 3000 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1

TSC2007IYZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TSC2007IPWR TSSOP PW 16 2000 367.0 367.0 35.0

TSC2007IYZGR DSBGA YZG 12 3000 210.0 185.0 35.0

TSC2007IYZGT DSBGA YZG 12 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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