THL3504_Rev.1.11_E
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THL3504
24-channel Constant Current LED Driver with LVDS Interface
DESCRIPTIONS
The THL3504 i s an LED driver with 24 channe l constant
current sink outputs. The constant current values for
three output groups are determined by external resistors.
The embedded oscillator and PWM controller
individually generates 256-step brightness set by the
dedicated registers for each channel.
The serial interface of 2-pair LVDS lines (clock and
data) features high-level noise tolerance, high-speed, and
long-distance transmission.
The LVDS allowing cascaded and multidrop connection
offers the maximum flexibility for designers to place and
connect LED drivers.
The simple and one-way communication protocol is
easily-controlled and requires less CPU resources.
APPLICATIONS
Amusement
LED Backlight
LED Display
Digital Signage
Illumination
FEATURES
< Driver part >
- Constant Current Output: 24 channels
- Output Sink Current: up to 40mA /ch
- Output voltage: up to 40V
- Individual Brightness Control: 256 steps
-Group Brightness Control: 64 steps
- Output disable/enable
< Serial interface part >
- 2-pair Serial LVDS Input or 3-wire Serial CMOS Input
up to 10Mbps
- Bridge Function Converting 3-wire Serial
CMOS Input to 2-pair Serial LVDS Output
- Repeater function of 2-pair Serial LVDS Input / Output
with Waveform and Timing Correction
- Device Address Selection up to 62 addresses
- General call to all devices
Protection Circuits
UVLO, Short Circuit Protectio n, Thermal Shut down
Supply Voltage: 3.0~5.5V
Package: QFN 48-pin Exposed Pad
Input Logic
Registers
Constant
Address Data
PWM Controller
A0~A5
SCL_OUTn
SCL_OUTp
SDA_OUTn
SDA_OUTp
SCL_INn
SCL_INp
SDA_INn
SDA_INp
Oscillator
MODE
CSn
SI
SCK SCL
SDA
Block Diagram
SCL
SDA
REXT0
REXT1
REXT2
Current
Generator
Current Sink
3-wire to 2-wire
Re-timing
conversion
LVDS Input LVDS Output
OUT0~OUT7 OUT8~OUT15 OUT16~OUT23
Current Sink
Current Sink
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ABSOLUTE MAXIMUM RATINGS
*Note1: As for the A0 pin, the maximu m value is VDD+0.5V. While power su ppl y is not applied, the voltage on the A0
pin must be lower than 0.5V.
RECOMMENDED OPERATING CONDIT IONS
*Note2: Since overshoot of current waveform may occur depending on usage conditions, the LEDs with more than
80mA pulse forward current as absolute maximum ratings are recommended
ELECTRICAL CHARACTERISTICS
Parameter Condition Min Typ Max Unit
VDD Supply Voltage -0.4 6.0 V
Digital Input Voltage *Note１-0.5 6.0 V
LED Driver Output Voltage 40 V
Storage Temperature -55 150 °C
Junction Temperature, Tj 150 °C
Parameter Condition Min Typ Max Unit
VDD Supply Voltage 3.0 5.5 V
LED Driver Output Voltage 35 V
LED Driver Output Current *Note2 40 mA/ch
Operating Ambient Temperature, Ta -40 85 °C
Parameter Min Typ Max Unit
11 mA
18 mA
13 mA
21 mA
28 mA
10 MHz
2.5 V
0.1 V
±3 %
±6 %
10 μA
0.7VDD V
0.3VDD V
0.05VDD V
±10 μA
VIC=1.2V ±100 mV
±30 μA
VDD=3.0V 240 mV
VDD=3.3V 350 mV
VDD=5.0V 420 mV
VDD=5.5V 480 mV
1.1 1.25 1.4 V
Condtion
VDD=3.3V, Iout=20mA(REXT=2.4kΩ)
without LVDS output termination resistors
VDD=3.3V, Iout=20mA(REXT=2.4kΩ)
with LVDS output termination resistors 100Ω
VDD=5.0V, Iout=20mA(REXT=2.4kΩ)
without LVDS output termination resistors
VDD=5.0V, Iout=20mA(REXT=2.4kΩ)
with LVDS output termination resistors 100Ω
VDD
Supply Current
*Note1
VDD=5.0V, Iout=20mA(REXT=2.4kΩ)
with LVDS output termination resistors 100Ω
UVLO Threshold Voltage (VDD Rising)
Osillator Frequency(fosc)
UVLO Hysteresis
Constant Current Mismatch Between Channels
Constant Current Mismatch Between Devices
LED Driver Output Leakage Current
Digital Input, High Level Voltage (VIH)
Digital Input, Low Level Voltage (VIL)
Digital Input, Hysteresis
LVDS Output, Common Mode Voltage (VOC)
Digital Input, Leakage Current
LVDS Input, Differential Voltage (VID)
LVDS Input, Leakage Current
LVDS Output, Differential Voltage (VOD)
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3-wire Serial CMOS Level Input (MODE=High)
2-pair Serial LVDS Output
2-pair Serial LVDS Input (MODE=Low)
*1. In cascading connection, termination resistors are necessary for LVDS outputs. In this case, 2.4mA to 4.8mA current
flows at each resistor depending on the power supp ly volt age. Therefore, the current consumption is larger than the case
without the termination resistors.
*2. SCL, SDATransition Time Measurement Condition
Symbol Parameter Condition Min Typ Max Unit
fSCK SCK Frequency 10 MHz
tCH SCK High Time 40 ns
tCL SCK Low Time 40 ns
tDVCH SI Setup Time 10 ns
tCHDX SI Hold Time 10 ns
tCHSL CSn Not Active Hold Time 40 ns
tSLCH CSn Active Setup Time 40 ns
tCHSH CSn Active Hold Time 40 ns
tSHCH CSn Not Active Setup Time 40 ns
tSHSL CSn Not Active Time 200 ns
Symbol Parameter Condition Min Typ Max Unit
tr, tf SCL, SDA Transition Time *2 10 ns
tSTAH Header Condition Hold Time 6 10 20 ns
tDSU SDA Setup Time 6 10 20 ns
tDHO SCL Falling Edge Hold Time 5 ns
tPWE End Pulse Width 25 40 70 ns
tPD SCL Propagation Delay 30 ns
Symbol Parameter Condition Min Typ Max Unit
fSCL SCL Frequency 10 MHz
tDAH SCL High Time 25 ns
tDAL SCL Low Time 25 ns
tSTAH Header Condition Hold Time 4 ns
tDSU SDA Setup Time 4 ns
tDHO SCL Falling Edge Hold Time 3 ns
SCL_OUTp
SCL_OUTn
SDA_OUTp
SDA_OUTn
100Ω
100Ω
Open
Open
< Without termination resistors >< With termination resistors >
Termination Resistor:100Ω
OUTp
OUTn
Load Capacitance:50pF
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* Abbreviation
This document refers to the differential signals in unipolar shorthand; for example, SCL_IN, SDA_IN, SCL_OUT, and
SDA_OUT mean (SCL_INp - SCL_INn), (SDA_INp - SDA_INn), (SCL_OUTp - SCL_OUTn), and (SDA_OUTp -
SDA_OUTn) respectively.
* A falling transition of the SDA_IN while the SCL_IN is high is defined as ”Header Condition“. Please refer to the sec-
tion “2-pai r S erial LVDS Input” for detai ls.
INp: SCL_INp, SDA_INp
INn: SCL_INn, SDA_INn
OUTp
OUTn
OUTp-OUTn 0V
VOC=(OUTp+OUTn)/2
VOD
80%
20%
tr tf
LVDS Spec
INp
INn VID
OUTp: SCL_OUTp, SDA_OUTp
OUTn: SCL_OUTn, SDA_OUTn
VIC=(INp+INn)/2
Bit 7 Bit 0
tCHSL tSLCH tCHSH tSHCH
tCH
tCL
tDVCH tCHDX
Bit 0Bit 7
tSHSL
tSTAH
tDAL tDAH
tDSU tDHO
tPWE
SCL_IN
SDA_IN
CSn
SCK
SI
Bit 0
Bit 7
tPD
Header Condition
tPD
Bit 0Bit 7
SCL_OUT
SDA_OUT
SCL_OUT
SDA_OUT
End Pulse
tSTAH tDSU tDHO
Header Condition
Timing Diagram
3-wire Serial Input/2-pair Serial LVDS Output Timing
2-pair Serial LVDS Input/Output Timing
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PIN CONFIGURATIONS
* The exposed pad is connected to GND inside the device.
The exposed pad should be soldered to GND on the PCB.
PIN DESCRIPTION
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
MODE
REXT2
A5
A4
VDD
REXT1
48 47 46 45 44 43 42 41 40 39 38 37
GND 136
OUT17
SDA_INn 235
OUT16
SDA_INp 334
OUT15
SCL_INn 433
OUT14
SCL_INp 532
OUT13
VDD 631
OUT12
GND 730
OUT11
SCL_OUTp 829
OUT10
SCL_OUTn 928
OUT9
SDA_OUTp 10 27 OUT8
SDA_OUTn 11 26 OUT7
GND 12 25 OUT6
13 14 15 16 17 18 19 20 21 22 23 24
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
A0
A1
A2
A3
VDD
REXT0
(Top View)
Exposed Pad
(Bottom Side)
Pin Name Type Description
MODE Digital Input
Serial Interface Input Mode Select
Low: 2-pair Serial LVDS Input
High: 3-wire Serial CMOS Input
SCL_INp(SCK) LVDS Input/
Digital Input
MODE=Low: 2-pair Serial LVDS Clock Input - Positive
MODE=High: 3-wire Serial Clock Input (SCK)
SCL_INn(CSn) LVDS Input/
Digital Input
MODE=Low: 2-pair Serial LVDS Clock Input - Negative
MODE=High: 3-wire Serial Chip Select Input (CSn)
SDA_INp(SI) LVDS Input/
Digital Input
MODE=Low: 2-pair Serial LVDS Data Input - Positive
MODE=High: 3-wire Serial Data Input (SI)
SDA_INn LVDS Input/
Digital Input
MODE=Low: 2-pair Serial LVDS Data Input - Negative
MODE=High: Reserved (Connect to Low)
SCL_OUTp LVDS Output 2-pair Serial LVDS Clock Output - Positive
SCL_OUTn LVDS Output 2-pair Serial LVDS Clock Output - Negative
SDA_OUTp LVDS Output 2-pair Serial LVDS Data Output - Positive
SDA_OUTn LVDS Output 2-pair Serial LVDS Data Output - Negative
OUT0-OUT23
Constant
Current Out
p
ut
LED Driver Output Channel 0 - 23
REXT0 Analog Output Resistor connection for the constant current outputs (OUT0-OUT7)
REXT1 Analog Output Resistor connection for the constant current outputs (OUT8-OUT15)
REXT2 Analog Output Resistor connection for the constant current outputs (OUT16-OUT23)
A0-A5 Digital Input Device address input Bit0 - 5
VDD ―Power supply
GND ―Ground
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REGISTER NOTATION
Address is noted in hex with the prefix “R“. For example, R00 is a register of address 00.
Bit location is noted by “[]“. For example, R00[5:0] is bit 5 down to bit 0 of address 00.
Register value is noted in binary with the suffix “b“. For example, R00[5:0]=000000b
Register value is noted in decimal without a suffix. For example, R04[7:0]=160
Register value is noted in hex with the suffix “h“. For example, R04=A0h
REGISTER MAP
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FUNCTIONAL DESCRIPTION
External reference resistor
The constant current value of LED driver output channels are determined by the resist ors connected between REXT0,
REXT1, REXT2 and GND. The external resistor value is calculated by the follo wing equation.
For example, when Iout=20mA, REXT=0.6/20 x 80=2.4[kΩ]
Writing to registers
The device includes 25-byte registers (R00-R18 ) for setting. Writing to registers is executed through the serial interface
and the value is maintained as long as power is applied. The register value can not be read.
Writing to registers should be invoked aft er the power supply (VD D) of all the devices in cascading and multidrop con-
nection gets stable above 3.0V.
Then after power-up, if using 2-pair serial LVDS input, initialization of 2-pair serial LVDS input must be done before
writing to registers. However, in case all the registers are continuously rewritten, in other words repeatedly refreshed, the
initialization of 2-pair serial LVDS input is not necessary after pow er-up and instantaneous interrupti on.
Please refer to the section “Initialization of 2-pair Serial LVDS Input” for details.
UVLO
The device ha s an internal UV LO (Under-Volta ge Locked-O ut) circuit to prevent the device from malfunction at low
supply voltage. Until power supply (VDD) has reached 2.5V (typical value), the UVLO holds the internal logic circuit in
a reset condition, and keeps the LED driver outputs and LVDS outputs in Hi-Z state. The UVLO circuit has hysteresis. If
power supply falls below 2.4V (typical value), the device gets into the above UVLO state in which the internal logic
circuit is reset and the regsiters are reset to default value.
Short Circuit Protection
The device includes short circuit protection circuits for each pin of the external reference resistor s, REXT0-REXT2 to
prevent the LED driver outputs from driving excessive current. If LED driver outputs turn on with the REXT0-REXT2
pin shorted to such as GND, overcurrent flowing in output transistors may causes permanent damage to the device.
The short circuit protection is a function to shutdown outputs immediately when the device detects short circuit condition
on REXT0-REXT2 pin. If short circuit condition is resolved, normal operation automatically resumes.
However, this function can not always prevent breakdown or damage to the device depending on usage situation and
duration of abnormality.
Thermal Shutdown
The device includes thermal shutdown c ircuit to prevent d amages caused by exc essive heat. If the j unction temperatu re
exceeds the absolute maximum rating (Tj=150°C), the thermal shutdown circuit turn off all LED driver outputs. The
thermal shutdown circuits has hysteresis. If Tj falls enough, normal operation automatically resumes.
However, this function can not always prevent breakdown or damage to the device depending on usage situation and
duration of abnormality.
REXT[kΩ]= 0.6 [V]
Iout [mA] ×80 (Typical Value at Iout=20mA)
Internal Reset Signal
Power Supply(VDD)
UVLO Threshold(2.5V typ.)
Hysterisys (0.1V typ.)
(Active-Low)
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Serial Communication Protocol
2-pair serial LVDS input or 3-wire serial CMOS level input is selected as a serial interface for register setting by the
MODE pin. The 2-pair serial LVDS input and 3-wire serial CMOS level input share input pins (SCL_INp/SCL_INn,
SDA_INp/SDA_INn) which are used as 2-pair serial LVDS in put when the MODE p in is set to low, and used as 3-wire
serial CMOS level input when the MODE pin is set to high.
-The serial interface is clock synchronous and used only for writing to registers (one-way commu nication).
- The data length is 8-bit in MSB first bit order. As for how to recognize the first bit, please refer to the section “2-pair
serial LVDS input” and “3-wire serial CMOS level input”.
-The first 8 bits that includes the first bit is defined as “1st byte” and the next 8 bits as “2nd byte” and so on.
- “1st Byte” is assigned to the device address. If device address is set to 00 h, all the devices are selected to be written
except the device which has a device address 00111111 by the A5-A0 pins.
- “2nd Byte” is assigned to the register address.
- The bytes after “3rd Byte” is assigned to register values to write. The register addres s is incremented every time 8-bit
register value is written. For example, the value of “3rd Byte” is written to the register at the address indicated in “2nd
byte“, and the value of “4th byte” is written to the register at the add ress (“2nd byte“+1).
- Don’t write except the registers R00-R18
< Serial Data >
Device Address Setting
The lower 6 bits out of 8-bit serial interface device address are set by the A0-A5 pin.The higher 2 bits are fixed at 00.
For example,
in case A5=Low, A4=Low, A3=Low, A2=Low, A1=Low, A0=High,
the device address is set to 00000001 (01h).
-If the A0-A5 pins are all set to high, the register of the device can not be written. Please set all the A0-A5 pins to high
in order to use onl y 2-pair to 2-pair re peater functi on or 3-wire to 2-pai r bridge func tion withou t using LED driv er out-
puts.
- Since the device address 00000000 (00h) is the one to be used for writing to all devices, basically don’t use it.
- Please set device addresses within the range from 00000001 (0 1h) to 00111110 (3Eh) in normal use.
The first bit
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Device Address Register Address
Register Value Register Value
1st Byte 2nd Byte
3rd Byte Last Byte
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Serial Interface Connection
THL3501 (16-channel open-drain outputs), THL3502(24-channel open-drain outputs), THL3503(16-channel constant-
current outputs), and THL3504(24-channel constant-current outputs) are all communication protocol compatible with
each other so that they can be mixed in cascade and multidrop connection scheme (Please note that multiple LVDS out-
puts can not be connected to each other.).
*THL3501, THL3502, THL3503, and THL3504 are collectively referred to as THL350X hereafter.
Cascade Connection by 2-pair serial LVDS
The THL350X can convert 3-wire serial output from the host such as micro-controller or CPU to 2-pair serial LVDS,
which is connected to the 2-pair serial LVDS input of a following device in a po int-to-point topo logy. As for the max i-
mum number of devices to be cascaded, please refer to an application note.
Multidrop Connection by 2-pair serial LVDS
The THL350X can convert 3-wire serial output from the host such as micro-controller or CPU to 2-pair serial LVDS,
which is connected to the 2-pair serial LVDS input of following multiple devices in a multidrop topology. As for the
maximum number of devices to be multidropped, please refer to an application note.
Multidrop Connection by 3-wire serial
3-wire serial output from the host such as micro-controller or CPU is connected to following multiple devices in a multi-
drop topology.
Host THL350X
SCL
SDA
3-wire serial 2-pair serial LVDS 2-pair serial LVDS
MODE pin=High MODE pin=Low MODE pin=Low
CSn
SCK
SI
THL350X THL350X
Host
SCL
SDA
2-pair serial LVDS
MODE pin=High
MODE pin=Low MODE pin=Low
CSn
SCK
SI
3-wire serial
THL350X
THL350X THL350X
Host
3-wire serial
MODE pin=High MODE pin=High
CSn
SCK
SI
THL350X THL350X
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3-wire Serial CMOS Level Input
When the MODE pin is set to high, the serial interface for writing to registers becomes 3-wire serial CMOS level input.
The chip select (CSn), serial clock (SCK), serial data (SI) of 3-wire serial CMOS level input are input to the SCL_INn
pin, the SCL_INp pin, the SDA_IN pin respectively. The SDA_INn must be tied to low.
- While the CSn stays low, the data input SI is latched by rising edges of the clock input SCK .
- The data latched by the first clock rising edge after the CSn falls is assigned the “first bit“.
- The “Last Byte” is written to a register when the CSn rises after Bit0 (in other words, “Last Byte” will not be written to
a register until the CSn rises).
- If the CSn rises in the m iddle o f a byte, the byt e is not writ ten to a register, then the comm unicatio n resumes from “1st
Byte” when the CSn falls next.
< 3-wire Serial CMOS Level Input >
2-pair serial LVDS
When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input
(SCL_INp/SCL_INn, SDA_INp/SDA_INn).
- The data input SDA_IN is latched by rising edges of the cloc k inpu t SCL_IN.
- A falling transition of the SDA_IN while the SCL_IN is high is defined as ”Header Condition“, and the data latched by
the first clock rising edge after the “Header Condition” is assigned the “first bit“. Except ”Header Condition”, the transi-
tions of the data input SDA_IN are allowed while th e cloc k inp ut SCL_IN is low.
- The “Last Byte” is written to a register at the reception of an active-low pulse “End Pulse” (actually, “Last Byte” is
written to a register at the rising edge of the “End Pulse“). W hen the “End Pulse” ri ses, the data outp ut SDA _OUT must
be high.
-If the ”Header Condition” is received in the middle of a byte, the byte is not written to a register, then the commun ica-
tion resumes from “1st Byte“.
< 2-pair serial LVDS input >
* The 3-wire to 2-p air b ridge function can convert 3 -wire serial output from the h ost such as micro -controller or CPU to
2-pair sereal LVDS. Please refer to the section “3-wire to 2-pair bridge function” for details.
SCL_INp (SCK)
SDA_INp (SI)
SCL_INn (CSn)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit
0
bit7 bit6
765432
1
076 765432
1
0
“1st Byte“ “2nd Byte“ “Last Byte“
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0bit7 bit6
765432
1
076 765432
1
0
“1st Byte“ “2nd Byte“ “Last Byte“
End Pulse
Header Condition
SCL_IN
SDA_IN
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3-wire to 2-pair bridge function
When the MODE pin is set t o high, the serial interface for writing to registers becomes 3-wire serial CMOS level input
(CSn, CK, SI), which is converted to 2-wire se rial and transferred to the LVDS output pins.
- While the CSn is active low, the data input SI is latched and transferred to the LVDS output SDA_OUT on the rising
edges of the clock input SCK. There is about 10ns setup time between the clock output SCL_OUT and the data output
SDA_OUT.
- When the CSn falls, “Header Condition” is generated on 2-pair LVDS outpu t.
- After the CSn rises, an active-low pulse "End Pulse” (the pulse width: 40ns typ) is added on the clock output
SCL_OUT.
- When the CSn rises, the data out put SDA_OUT is forced high. In the result, the low to high transi tio n of the clock out-
put SCL_OUT "End Pulse” occurs while the data output SDA_OU T is high
< 3-wire to 2-pair bridge >
2-pair to 2-pair repeater function
When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input
(SCL_INp/SCL_INn, SDA_INp/SDA_INn). The timing between the clock and the data is compensated and then they are
transferred to the LVDS output pins.
- The data input SDA_IN is latched and transferred to the LVDS output SDA_OUT on the rising edges of the clock input
SCL_IN. There is about 10ns setup time between the cl ock output SCL_OUT and the data output SDA_OUT.
- The “Header Condition” is regenerated and transferred to the output.
< 2-pair to 2-pair repeater function >
SCL_INp (SCK)
SDA_INp (SI)
SCL_INn (CSn)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0bit7 bit6
765432
1
076 765432
1
0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6
765432
1
076 765432
1
0
“1st Byte“ “2nd Byte“ “Last Byte“
End Pulse
Header Condition
SCL_OUT
SDA_OUT
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6
765432
1
076 765432
1
0End Pulse
Header Condition
SCL_IN
SDA_IN
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6
765432
1
076 765432
1
0
“1st Byte“ “2nd Byte“ “Last Byte“
SCL_OUT
SDA_OUT
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Initialization of 2-pair Serial LVDS Input
After power-up, if using 2-pair serial LVDS input, initialization of 2-pair serial LVDS input must be done before writing
to registers. Without the initialization of 2-pair serial LVDS input, the first writing to regi sters (“1st Byte”-”Last Byte”)
may possibly fail. However, the initialization of 2-pair serial LVDS input is not necessary in case failure in the first writ-
ing to registers can be allowed; for example , in case all the registers (R00-R18) are continuously rewritten, in other
words repeatedly refreshed.
In order to initialize 2-pair serial LVDS input, please input active-low pulse (pulse width: 200ns min.) of the CSn into 3-
wire serial CMOS level input of the first device which converts 3-wire to 2-pair. In consequence, the 2-pair serial LVDS
input of all the following devices are initialized. In cascading connection, it takes the propagation delay of all stages in
cascaded chain to finish the initialization of 2-pair serial LVDS input.
< Initialization of 2-pair Serial LVDS Input >
Host
SCL
SDA
3-wire serial 2-pair serial LVDS 2-pair serial LVDS
CSn
SCK
SI
Active-low pulse input 2-pair serial LVDS inputs to be initialized
THL350X THL350X
765432
1
0
SCL_INp (SCK)
SDA_INp (SI)
SCL_INn (CSn)
Initialization Pattern Example 1
(High)
(High)
Input active-low pulse input to the CSn
Min.200ns
SCL_OUT
SDA_OUT
(High)
765432
1
0
Initialization Pattern
Initialization Pattern Example 2
Input 1st Byte (Device Address)=FFh
SCL_INp (SCK)
SDA_INp (SI)
SCL_INn (CSn)
SCL_OUT
SDA_OUT
3-wire serial
CMOS level input
2-pair serial
LVDS Output
Initialization Pattern
3-wire serial
CMOS level input
2-pair serial
LVDS Output
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Individual Brightness Control
The Brightness for each LED output channel (OUT0-OUT23) are individually programmable in 256 steps by the register
configuration (R01-R15). The individual Brightness is contro lled by PWM duty cycle.
The ratio of ON time for the constant current outpu ts is expressed in the follo wing equation.
ON time ratio = Individual Brightness Control Register Value / 256
The bigger setting valu e results in the larger ON time ratio, therefore hi gher brightness. When the register value is 0, the
output current sink is held OFF, therefore the LED turns off.
< Individual Brightness Control >
Global Brightness Control
In addition to the individual brightness control for each LED driver output channels, the brightness of all channe ls is glo-
bally programmable in 64 steps by the register configuration (R00[5:0]). The global brightness controller partially masks
pulses generated by the individual brightness controller.
The ratio of ON time for the constant current outputs which is totally set by both the individual brightness contr ol and
global brightness control is expressed in the following equation.
ON time ratio = (Individual Brightness Control register value/256) x (Global Brightness Control register value+1)/64
The bigger setting value results in the larger ON time ratio, therefore higher brightness.
< Global Brightness Control >
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Individual Brightness:255
ON Dugy=255/256
Individual Brightness:254
ON Dugy =254/256
Individual Brightness:2
ON Dugy=2/256
Individual Brightness:1
ON Dugy =1/256
Individual Brightness:0
ON Dugy =0/256
approximately 27μs
123450678910 63626160
5958575655 12340
123450678910 63626160
5958575655 12340
123450678910 63626160
5958575655 12340
123450678910 63626160
5958575655 12340
123450678910 63626160
5958575655 12340
11
11
11
11
11
Global Brightness:63
ON Duty=64/64
Global Brightness:62
ON Duty =63/64
Global Brightness:2
ON Duty =3/64
Global Brightness:1
ON Duty=2/64
Global Brightness:0
ON Duty=1/64
approximately 27μs
approximately 1.7ms
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Increment timing of Global Brightness Control
Global brightness control is started soon at the timing of incremented.new resister data and previous data is destructed.
Therefore, please be careful about brightness changes for short periods depending on the timing of increm ented new
data. < Increment timing of Global Brightness Control >
PWM Phase Control Mode
The PWM pulse start position of each channel is controlled in different phases to reduce switching noise.
The phase control mode is selectable in 2 way s by the register configu rati on (R00[7]).
In normal mode (R00[7]=0), the PWM pulse start positions of all channels are different from each other.
In group control mode (R00[7]=1), the PWM pulse start positions of 2 or 3 channel groups are different from each other.
< PWM Phase Control Mode >
1234506789
10 20191817
1615141312 012321
11
Global Brightness:：7
ON Duty =8/64
resister writing
Global Brightness:：1
ON Duty =2/64
1234506789
10 6543
2101312 8910117
11
Global Brightness:：7
ON Duty =8/64
resister writing
Global Brightness:：1
ON Duty =2/64
OUT0
OUT1
OUT2
Delay
Delay
Delay
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
Delay
Delay
Delay
Normal Mode(R00[7]=0)
Group Control Mode(R00[7]=1)
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Group
0
Group 1
THL3504_Rev.1.11_E
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When multiple LED output channels need to be connected in parallel to driv e, the PWM phase control mode must be set
to group control mode (R00[7]=1), and the channels in th e same group must be connected in parallel to drive.
< Grouping of Group Control Mode >
LED Driver Output Enable
All of the LED driver outputs can be disabled by register configuration (R00 [6]). When disab led (R00[6]= 0), all of the
LED driver outputs go into OFF (Hi-Z) state, LEDs turn off.
OUT(n)
OUT(n+1)
OUT(n+2)
Same group
Pin Name
Group Output Channel
Group0 OUT0, OUT1, OUT2
Group1 OUT3, OUT4, OUT5
Group2 OUT6, OUT7, OUT8
Group3 OUT9, OUT10, OUT11
Group4 OUT12, OUT13, OUT14
Group5 OUT15, OUT16, OUT17
Group6 OUT18, OUT19, OUT20
Group7 OUT21, OUT22, OUT23
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Package Dimensions
QFN 48-pin
7.00 bsc
7.00 bsc
TOP VIEW SIDE VIEW
S
SEATING PLANE
1 PIN INDEX
Unit:mm
5.50 +/-0.10
5.50 +/-0.10
BOTTO M VIEW
①
48
0.09 R M IN
1 PIN INDEX
0.20 R
0.35
0.35
0.40 +/-0.05
0 .4 0 + /-0 .0 5
0.25 +0.05/-0.07
0.50 bsc
S
0.05
0.45
0.10
0.05 M AX
0.20 R E F.
0.65～0.70
0.90 M A X
THL3504_Rev.1.11_E
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to the
customer’s design. We are not responsible for possible errors and omissions in this material. Please note if errors or
omissions should be found in th is material, we may not be able to correct them immediately.
3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents
of this material without our prior perm ission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product , we wi ll be
exempted from the responsibility unless it directly relates to the production process or functions of the product.
5. This product is presumed to be used for general electric equipment, no t for the applications which require very high
reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control
equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation
means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate
measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently
redundant or error preventive design applied to the use of the prod uct so as no t to have our product cause any social or
public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under
the Foreign Exchange and Foreign Trade Control Law.
9. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damage ｓ may cause a smoking and
ignition. Therefore, you are encouraged to implement safety measures by adding protect ion devices, such as fuses.
THine Electronics, Inc.
E-mail: sales@thine.co.jp