DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT4520
Dual 4-bit synchronous binary
counter
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
FEATURES
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP0)
and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3= LOW)
independent of nCP0 and nCP1.
APPLICATIONS
•Multistage synchronous counting
•Multistage asynchronous counting
•Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay nCP0, nCP1 to nQnCL= 15 pF; VCC =5 V2424ns
t
PHL propagation delay nMR to nQn13 13 ns
fmax maximum clock frequency 68 64 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per counter notes 1 and 2 29 24 pF
December 1990 3
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 9 1CP0, 2CP0clock inputs (LOW-to-HIGH, edge-triggered)
2, 10 1CP1, 2CP1clock inputs (HIGH-to-LOW, edge-triggered)
3, 4, 5, 6 1Q0 to 1Q3data outputs
7, 15 1MR, 2MR asynchronous master reset inputs (active HIGH)
8 GND ground (0 V)
11, 12, 13, 14 2Q0 to 2Q3data outputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑= LOW-to-HIGH clock transition
↓= HIGH-to-LOW clock transition
nCP0nCP1MR MODE
↑H L counter advances
L↓L counter advances
↓X L no change
X↑L no change
↑L L no change
H↓L no change
XXHQ
0
to Q3= LOW
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990 5
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP0 to nQn
77
28
22
240
48
41
300
60
51
360
72
61
ns 2.0
4.5
6.0
Fig.8
tPHL/ tPLH propagation delay
nCP1 to nQn
77
28
22
240
48
41
300
60
51
360
72
61
ns 2.0
4.5
6.0
Fig.8
tPHL propagation delay
nMR to nQn
44
16
13
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.9
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.8
tWclock pulse width
HIGH or LOW 80
16
14
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tWmaster reset pulse width
HIGH 120
24
20
39
14
11
150
30
26
180
36
31
ns 2.0
4.5
6.0
Fig.7
trem removal time
nMR to nCP0; nCP1
0
0
0
−28
−10
−8
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.7
tsu set-up time
nCP1 to nCP0;
nCP0 to nCP1
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
fmax maximum clock pulse
frequency 6.0
30
35
19
58
69
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
December 1990 6
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
nCP0, nCP1
nMR 0.80
1.50
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP0 to nQn
28 53 66 80 ns 4.5 Fig.8
tPHL/ tPLH propagation delay
nCP1 to nQn
25 53 66 80 ns 4.5 Fig.8
tPHL propagation delay
nMR to nQn
16 35 44 53 ns 4.5 Fig.9
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.8
tWclock pulse width
HIGH or LOW 20 10 25 30 ns 4.5 Fig.7
tWmaster reset pulse width
HIGH 20 12 25 30 ns 4.5 Fig.7
trem removal time
nMR to nCP0; nCP1
0−8 0 0 ns 4.5 Fig.7
tsu set-up time
nCP1 to nCP0;
nCP0 to nCP1
16 6 20 24 ns 4.5 Fig.8
fmax maximum clock pulse
frequency 30 58 24 20 MHz 4.5 Fig.7
December 1990 7
Philips Semiconductors Product specification
Dual 4-bit synchronous binary counter 74HC/HCT4520
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.7 Waveforms showing removal time for nMR; minimum nCP0, nCP1, nMR pulse widths and maximum clock
pulse frequency.
Conditions:
nCP1= HIGH while nCP0 is triggered on a LOW-to-HIGH transition; tW
and trem also apply when nCP0= LOW and nCP1 is triggered on a
HIGH-to-LOW transition.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing set-up times for nCP0 to nCP1 and nCP1 to nCP0, propagation delays and output
transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing propagation delay from nMR to nQn output.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
