PWM
CONTROLLER
+12V
ISOLATION
AND
FEEDBACK
+100V
SECONDARY
SIDE
CIRCUIT
HI
CONTROL
DRIVE
LO
DRIVE
HI
VDD
UCC27200A/1A
VSS
LI
HB
HO
HS
LO
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
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UCC2720xA 120-V Boot, 3-A Peak, High-Frequency, High-Side and Low-Side Driver
1 Features 3 Description
The UCC2720xA family of high-frequency N-channel
1• Drives Two N-Channel MOSFETs in High-Side MOSFET drivers include a 120-V bootstrap diode and
and Low-Side Configuration high-side/low-side driver with independent inputs for
• Negative Voltage Handling on HS (–18V) maximum control flexibility. This allows for N-channel
• Maximum Boot Voltage 120 V MOSFET control in half-bridge, full-bridge, two-switch
forward and active clamp forward converters. The
• Maximum VDD Voltage 20 V low-side and the high-side gate drivers are
• On-Chip 0.65-V VF, 0.6-ΩRD Bootstrap Diode independently controlled and matched to 1-ns
• Greater than 1 MHz of Operation between the turn-on and turn-off of each other. The
UCC2720xA are based on the popular UCC27200/1
• 20-ns Propagation Delay Times drivers, but offer some enhancements. In order to
• 3-A Sink, 3-A Source Output Currents improve performance in noisy power supply
• 8-ns Rise/7-ns Fall Time with 1000-pF Load environments the UCC2720xA has an enhanced ESD
• 1-ns Delay Matching input structure and also has the ability to withstand a
maximum of –18 V on its HS pin.
• Undervoltage Lockout for High-Side and Low-Side
Driver An on-chip bootstrap diode eliminates the external
discrete diodes. Under-voltage lockout is provided for
• Offered in 8-Pin SOIC (D), PowerPAD™ SOIC-8 both the high-side and the low-side drivers forcing the
(DDA), SON-8 (DRM), SON-9 (DRC) and SON-10 outputs low if the drive voltage is below the specified
(DPR) Packages threshold.
• Specified from –40°C to 140°C Two versions of the UCC27200A are offered. The
UCC27200A has high-noise immune CMOS input
2 Applications thresholds while the UCC27201A has TTL-compatible
• Power Supplies for Telecom, Datacom, and thresholds.
Merchant Markets Both devices are offered in an 8-pin SOIC (D),
• Half-Bridge Applications and Full-Bridge PowerPad SOIC-8 (DDA), SON-8 (DRM) package, a
Converters 9-pin SON-9 (DRC) package and a 10-pin SON-10
• Isolated Bus Architecture (DPR) package.
• Two-Switch Forward Converters Device Information(1)
• Active-Clamp Forward Converters PART NUMBER PACKAGE BODY SIZE (NOM)
• High-Voltage Synchronous-Buck Converters SOIC (8) 4.90 mm × 3.91 mm
• Class-D Audio Amplifiers HSOP (8) 4.89 mm × 3.90 mm
UCC27200A,
UCC27201A VSON (9) 3.00 mm × 3.00 mm
Simplified Application Diagram VSON (8) 4.00 mm × 4.00 mm
UCC27201A WSON (10) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27200A
,
UCC27201A
SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
1 Features.................................................................. 18 Application and Implementation ........................ 14
2 Applications ........................................................... 18.1 Application Information............................................ 14
3 Description............................................................. 18.2 Typical Application ................................................. 14
4 Revision History..................................................... 29 Power Supply Recommendations...................... 20
5 Pin Configuration and Functions......................... 310 Layout................................................................... 20
6 Specifications......................................................... 510.1 Layout Guidelines ................................................. 20
6.1 Absolute Maximum Ratings ...................................... 510.2 Layout Example .................................................... 21
6.2 ESD Ratings.............................................................. 511 Device and Documentation Support................. 22
6.3 Recommended Operating Conditions....................... 511.1 Documentation Support ........................................ 22
6.4 Thermal Information.................................................. 611.2 Related Links ........................................................ 22
6.5 Electrical Characteristics........................................... 611.3 Community Resources.......................................... 22
6.6 Typical Characteristics.............................................. 811.4 Trademarks........................................................... 22
7 Detailed Description............................................ 12 11.5 Electrostatic Discharge Caution............................ 22
7.1 Overview................................................................. 12 11.6 Glossary................................................................ 22
7.2 Functional Block Diagram....................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 12 Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2011) to Revision B Page
• Added Negative Voltage Handling on HS (–18 V) to Features List ...................................................................................... 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (February 2011) to Revision A Page
• Added SON-10 (DPR) Package to the List of FEATURES.................................................................................................... 1
• Added SON-10 (DPR) Package to the DESCRIPTION ......................................................................................................... 1
• Changed the PIN FUNCTIONS table..................................................................................................................................... 4
• Added Additional PIN FUNCTIONS information..................................................................................................................... 4
• Added ordering information for the SON-10 (DPR)................................................................................................................ 5
• Added note, "DPR(SON-10) package comes either in a small reel of 250 pieces as part number UCC27200ADPRT,
or large reels pieces as part number UCC27200ADPRR.".................................................................................................... 5
• Added the SON-10 package to the ORDERING INFORMATION table................................................................................. 5
• Added the SON-10 package to the THERMAL INFORMATION table................................................................................... 5
• Changed the "Minimum input pulse width" value From: 50 ns Max To: 50 ns Typ................................................................ 7
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Exposed
Thermal
Die Pad
NC
LO
VSS
LI
HI
NC
VDD 10
HO
HS
HB
8
7
6
9
1
3
4
5
2
1
2
3
4
9
7
6
5
VDD
HB
HO
HS
VSS
Exposed
Thermal
Die Pad*
LO
LI
HI
8
N/C
1
2
3
4
8
7
6
5
VDD
HB
HO
HS
VSS
Exposed
Thermal
Die Pad*
LO
LI
HI
1
2
3
4
8
7
6
5
VDD
HB
HO
HS
VSS
Exposed
Thermal
Die Pad
LO
LI
HI
1
2
3
4
8
7
6
5
VDD
HB
HO
HS
LO
VSS
LI
HI
UCC27200A
,
UCC27201A
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SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
5 Pin Configuration and Functions
D Package DDA Package
8-Pin SOIC 8-Pin SOIC With Exposed PowerPAD
Top View Top View
DRM Package DRC Package
8-Pin SON 9-Pin SON
Top View Top View
DPR Package
10-Pin SON
Top View
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Pin Functions
PIN I/O DESCRIPTION
NAME DRM/D/DDA DRC DPR
Positive supply to the lower gate driver. De-couple this pin to
VDD 1 1 1 I VSS (GND). Typical decoupling capacitor range is 0.22 μF to
1.0 μF.
High-side bootstrap supply. The bootstrap diode is on-chip but
the external bootstrap capacitor is required. Connect positive
HB 2 2 2 I side of the bootstrap capacitor to this pin. Typical range of HB
bypass capacitor is 0.022 μF to 0.1 μF, the value is dependant
on the gate charge of the high-side MOSFET however.
High-side output. Connect to the gate of the high-side power
HO 3 3 3 O MOSFET.
High-side source connection. Connect to source of high-side
HS 4 4 4 I power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI 5 6 7 I High-side input.
LI 6 7 8 I Low-side input.
Negative supply terminal for the device which is generally
VSS 7 8 9 O grounded.
Low-side output. Connect to the gate of the low-side power
LO 8 9 10 O MOSFET.
N/C — 5 5/6 — No connection. Pins labeled N/C have no connection.
Connect to a large thermal mass trace or GND plane to
PowerPAD(1) — — — — dramatically improve thermal performance.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DDA and DRM packages only. Electrically referenced to VSS
(GND).
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature, unless noted, all voltages are with respect to VSS (1)
MIN MAX UNIT
Supply voltage range, (2) VDD –0.3 20 V
Input voltages on LI and HI, VLI, VHI –0.3 20 V
DC –0.3 VDD + 0.3
Output voltage on LO, VLO V
Repetitive pulse <100 ns(3) –2 VDD + 0.3
DC VHS – 0.3 VHB + 0.3
VHB + 0.3,
Output voltage on HO, VHO V
Repetitive pulse <100 ns(3) VHS – 2 (VHB - VHS
<20)
DC –1 120
Voltage on HS, VHS V
Repetitive pulse <100 ns(3) –18 120
Voltage on HB, VHB –0.3 120 V
Voltage On HB-HS –0.3 120 V
Operating virtual junction temperature range, TJ–40 150 °C
Lead temperature (soldering, 10 sec.) 300 °C
Power dissipation at TA= 25°C (D package) (4) 1.3 W
Power dissipation at TA= 25°C (DDA package) (4) 2.7 W
Power dissipation at TA= 25°C (DRM package) (4) 3.3 W
Power dissipation at TA= 25°C (DRC package) (4) 2.86 W
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization and are not production tested.
(4) This data was taken using the JEDEC proposed high-K test PCB. See the THERMAL CHARACTERISTICS section for details.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VDD Supply voltage 8 12 17 V
VHS Voltage on HS –1 105 V
Voltage on HS, (repetitive pulse <100 ns) –15 110 V
VHB VHS + 8, VHS + 17,
Voltage on HB V
VDD –1 115
Voltage slew rate on HS 50 V / ns
TJOperating junction temperature range –40 140 °C
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6.4 Thermal Information UCC27200A UCC27200A UCC27200A UCC27200A UCC27200A
/UCC27201A /UCC27201A /UCC27201A /UCC27201A /UCC27201A
THERMAL METRIC(1) UNIT
DRM (VSON) DRC (VSON) DPR (WSON) D (SOIC) DDA (HSOP)
8 PINS 9 PINS 10 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 36.2 43.7 34.8 106.5 40.5 °C/W
RθJC(top) Junction-to-case (top) thermal 41.6 49.9 32.1 52.9 49 °C/W
resistance
RθJB Junction-to-board thermal resistance 13.2 19.1 11.9 46.6 10.2 °C/W
ψJT Junction-to-top characterization 0.6 0.6 0.2 9.6 3.1 °C/W
parameter
ψJB Junction-to-board characterization 13.4 19.3 12.2 46.1 9.7 °C/W
parameter
RθJC(bot) Junction-to-case (bottom) thermal 3.1 3.8 1.3 — 1.5 °C/W
resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA= TJ= –40°C to
+140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current VLI = VHI = 0 0.4 0.8 mA
UCC27200A f = 500 kHz, CLOAD = 0 2.5 4
IDDO VDD operating current mA
UCC27201A f = 500 kHz, CLOAD = 0 3.8 5.5
IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8 mA
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4 mA
IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.0005 1 uA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.1 mA
INPUT
VHIT Input rising threshold UCC27200A 5.8 8 V
VLIT Input falling threshold UCC27200A 3 5.4 V
VIHYS Input voltage hysteresis UCC27200A 0.4 V
VHIT Input voltage threshold UCC27201A 1.7 2.5 V
VLIT Input voltage threshold UCC27201A 0.8 1.6 V
VIHYS Input voltage Hysteresis UCC27201A 100 mV
RIN Input pulldown resistance UCC27201A 100 200 350 kΩ
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold 6.2 7.1 7.8 V
VDD threshold hysteresis 0.5 V
VHB rising threshold 5.8 6.7 7.2 V
VHB threshold hysteresis 0.4 V
BOOTSTRAP DIODE
VFLow-current forward voltage I VDD - HB = 100 μA 0.65 0.85 V
VFI High-current forward voltage I VDD - HB = 100 mA 0.85 1.1 V
IVDD - HB = 100 mA and 80
RDDynamic resistance, ΔVF/ΔI 0.6 1.0 Ω
mA
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Electrical Characteristics (continued)
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA= TJ= –40°C to
+140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO GATE DRIVER
VLOL Low level output voltage ILO = 100 mA 0.18 0.4 V
ILO = –100 mA, VLOH = VDD -
TJ= -40 to 125°C 0.25 0.4
VLO
VLOH High level output voltage V
ILO = –100 mA, VLOH = VDD -
TJ= -40 to 140°C 0.25 0.42
VLO
Peak pullup current VLO = 0 V 3 A
Peak pulldown current VLO = 12 V 3 A
HO GATE DRIVER
VHOL Low level output voltage IHO = 100 mA 0.18 0.4 V
IHO = –100 mA, VHOH = VHB-
TJ= -40 to 125°C 0.25 0.4
VHO
VHOH High level output voltage V
IHO = –100 mA, VHOH = VHB-
TJ= -40 to 140°C 0.25 0.42
VHO
Peak pullup current VHO = 0 V 3 A
Peak pulldown current VHO = 12 V 3 A
PROPAGATION DELAYS
TJ= -40 to 125°C CLOAD = 0 20 45
tDLFF VLI falling to VLO falling ns
TJ= -40 to 140°C CLOAD = 0 20 50
TJ= -40 to 125°C CLOAD = 0 20 45
tDHFF VHI falling to VHO falling ns
TJ= -40 to 140°C CLOAD = 0 20 50
TJ= -40 to 125°C CLOAD = 0 20 45
tDLRR VLI rising to VLO rising ns
TJ= -40 to 140°C CLOAD = 0 20 50
TJ= -40 to 125°C CLOAD = 0 20 45
tDHRR VHI rising to VHO rising ns
TJ= -40 to 140°C CLOAD = 0 20 50
DELAY MATCHING
tMON LI ON, HI OFF 1 7 ns
tMOFF LI OFF, HI ON 1 7 ns
OUTPUT RISE AND FALL TIME
tRLO, HO CLOAD = 1000 pF 8 ns
tFLO, HO CLOAD = 1000 pF 7 ns
tRLO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.35 0.6 us
tFLO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.3 0.6 us
MISCELLANEOUS
Minimum input pulse width that changes the output 50 ns
Bootstrap diode turnoff time IF= 20 mA, IREV = 0.5 A(1) (2) 20 ns
(1) Typical values for TA= 25°C
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
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10 1000
Frequency - kHz
0.1
10.0
100
1.0
IDDO - Operating Current - mA
-40oC
25oC
150oC
125oC
VDD = 12 V
No Load on Outputs
10 1000
Frequency - kHz
0.1
10.0
100
1.0
IDDO - Operating Current - mA
-40oC
25oC
150oC
125oC
VDD = 12 V
No Load on Outputs
Input
(HI, LI)
Output
(HO, LO)
TMON TMOFF
LI
HI
LO
HO
TDLRR, TDHRR
TDLFF, TDHFF
UCC27200A
,
UCC27201A
SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
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Figure 1. Timing Diagram
6.6 Typical Characteristics
Figure 2. UCC27200A IDD Operating Current vs Frequency Figure 3. UCC27201A IDD Operating Current vs Frequency
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1.0
1.4
1.6
1.8
2.0
1.2
HI, LI - Input Threshold Voltage - V
-50 -25 0 75 100 125 150
TA- Temperature - oC
25 50
Rising
Falling
VDD = 12 V
40
42
44
46
48
50
HI, LI - Input Threshold Voltage/VDD Voltage - %
-50 -25 0 75 100 125 150
TA- Temperature - oC
25 50
Rising
Falling
VDD = 12 V
40
42
44
46
48
50
HI, LI - Input Threshold Voltage/VDD Voltage - %
Rising
Falling
8 10 12 16 20
VDD - Supply Voltage - V
14 18
T = 25oC
8 10 12 16 20
VDD - Supply Voltage - V
1.0
1.2
1.4
1.6
1.8
2.0
14 18
HI, LI - Input Threshold Voltage - V
Rising
Falling
T = 25oC
10 1000
Frequency - kHz
0.1
10.0
100
1.0
IHBO - Operating Current - mA
-40oC
25oC
150oC
125oC
HB = 12 V
No Load on Outputs
10 1000
Frequency - kHz
0.001
1.0
100
0.01
IHBSO - Operating Current - mA
-40oC
25oC
150oC
125oC
HB = 12 V
No Load on Outputs
0.1
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Typical Characteristics (continued)
Figure 4. Boot Voltage Operating Current vs Frequency Figure 5. HB to VSS Operating Current vs Frequency
Figure 7. UCC27201A Input Threshold vs Supply Voltage
Figure 6. UCC27200A Input Threshold vs Supply Voltage
Figure 8. UCC27200A Input Threshold vs Temperature Figure 9. UCC27201A Input Threshold vs Temperature
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-50 -25 0 25 100 125
14
18
22
26
32
36
50 75 150
16
20
24
30
34
TA- Temperature - oC
Propagation Delay - ns
28
TDLFF
TDLRR
TDHFF
TDHRR
VDD = VHD = 12 V
14
18
22
26
30
36
16
20
24
28
34
Propagation Delay - ns
-50 -25 0 75 100 125 150
TA- Temperature - oC
25 50
32
TDLFF
TDLRR
TDHFF
TDHRR
VDD = VHB = 12 V
5.8
6.2
6.6
7.0
7.4
7.8
6.0
6.4
6.8
7.2
7.6
Threshold - V
-50 -25 0 75 100 125 150
TA- Temperature - oC
25 50
VDD Rising Threshold
HB Rising Threshold
-50 -25 0 75 100 125 150
TA- Temperature - oC
0
0.2
0.4
0.6
0.8
25 50
0.1
0.3
0.5
0.7
Hysteresis - V
VDD UVLO Hysteresis
HB UVLO Hysteresis
-50 -25 0 25 100 125
TA- Temperature - oC
0.05
0.15
0.25
0.35
0.45
50 75 150
0.0
0.10
0.20
0.30
0.40
VOH - LO/HO Output Voltage - V
ILO = IHO = -100 mA VDD = VHB = 16 V
VDD = VHB = 12 V
VDD = VHB = 8 V
VDD = VHB = 20 V
-50 -25 0 25 100 125
TA- Temperature - oC
0.05
0.15
0.25
0.35
0.45
50 75 150
0.0
0.10
0.20
0.30
0.40 ILO = IHO = 100 mA
VDD = VHB = 16 V
VDD = VHB = 12 V
VDD = VHB = 8 V
VDD = VHB = 20 V
VOL - LO/HO Output Voltage - V
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Typical Characteristics (continued)
Figure 10. Lo and Ho High Level Output Voltage vs Figure 11. Lo and Ho Low Level Output Voltage vs
Temperature Temperature
Figure 12. Undervoltage Lockout Threshold vs Temperature Figure 13. Undervoltage Lockout Threshold Hysteresis vs
Temperature
Figure 14. UCC27200A Propagation Delays vs Temperature Figure 15. UCC27201A Propagation Delays vs Temperature
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0.5 0.6 0.9
Diode Voltage - V
0.001
0.01
0.1
1.0
10.0
100.0
0.7 0.8
Diode Current - mA
0 4 12 20
VDD, VHB - Supply Voltage - V
0
300
400
700
8 16
100
200
500
600
IDD, IHB - Supply Current - mA
IDD
IHB
Inputs Low
T = 25oC
0 4 6 10
VLO, VHO - Output Voltage - V
0
1.5
2.0
3.5
8 12
0.5
1.0
2.5
3.0
ILO, IHO - Output Current - A
VDD = VHB = 12 V
Pull-Down Current
Pull-Up Current
2
-50 -25 0 75 125 150
TA- Temperature - ?C
0
7
25 50 100
1
2
Delay Matching - ns
3
4
5
6
VDD = VHB = 12 V
UCC27200ATMON
UCC27200ATMOFF
UCC27201ATMOFF
UCC27201ATMON
8 10 12 16 20
VDD = VHB - Supply Voltage - V
16
18
20
22
24
26
14 18
Propagation Delay - ns
LI Rising
LI Falling
T = 25oC
HI Rising
HI Falling
8 10 16 18 20
VDD = VHB - Supply Voltage - V
18
20
26
12 14
22
24
Propagation Delay - ns
T = 25oC
LI Rising
LI Falling
HI Rising
HI Falling
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Typical Characteristics (continued)
Figure 16. UCC27200A Propagation Delay vs Supply Voltage Figure 17. UCC27201A Propagation Delay vs Supply Voltage
Figure 18. Delay Matching vs Temperature Figure 19. Output Current vs Output Voltage
Figure 20. Diode Current vs Diode Voltage Figure 21. Quiescent Current vs Supply Voltage
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LEVEL
SHIFT
UVLO
UVLO
5
3
8
4
6 7
2
1
HI
LI
VDD
HB
HO
HS
LO
VSS
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7 Detailed Description
7.1 Overview
The UCC27200A and UCC27201A are high-side and low-side drivers. The high-side and low-side each have
independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for
the high-side driver bias supply is internal to the UCC27200A and UCC27201A. The UCC27200A is the CMOS
compatible input version and the UCC27201A is the TTL or logic compatible version. The high-side driver is
referenced to the switch node (HS) which is typically the source pin of the high side MOSFET and drain pin of
the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions
contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Input Stages
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200A is
200 kΩnominal and input capacitance is approximately 2 pF. The 200 kΩis a pulldown resistance to Vss
(ground). The CMOS-compatible input of the UCC27200A provides a rising threshold of 48% of VDD and falling
threshold of 45% of VDD. The inputs of the UCC27200A are intended to be driven from 0 to VDD levels.
The input stages of the UCC27201A incorporate an open-drain configuration to provide the lower input
thresholds. The input impedance is 200 kΩnominal and input capacitance is approximately 4 pF. The 200 kΩis
a pulldown resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and
a falling threshold of 1.6 V.
7.3.1.1 UVLO (Undervoltage Lockout)
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold
is 6.7 V with 0.4-V hysteresis.
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Feature Description (continued)
7.3.1.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
7.3.1.3 Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and
the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The
boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
7.3.1.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
7.4 Device Functional Modes
The device operates in normal mode and VULO mode. See UVLO (Undervoltage Lockout) for more information
on UVLO operation mode. In normal mode, the output stage is dependent on the sates of the HI and LI pins.
Table 1. Device Logic Table
HI PIN LI PIN HO(1) LO(2)
L L L L
L H L H
H L H L
H H H H
(1) HO is measured with respect to the HS.
(2) LO is measured with respect to the VSS.
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+ +
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,
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
8.2 Typical Application
An open loop half-bridge converter was used to calculate performance in an actual application.
Figure 22. Open Loop Half-Bridge Converter
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7
8
Vss
1VDD
LO
Cvdd
L bondwire
Rsink
Rsource
L pin
L trace
L bondwire
L bondwire
Driver
Output
Stage
L pin
L pin
L trace
Isink
L trace Cgs
Rg
L trace
ISOURCE
UCC27200A
,
UCC27201A
www.ti.com
SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
Typical Application (continued)
8.2.1 Design Requirements
UCC27201A Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Supply Voltage, VDD 12 V
Voltage on HS, VHS 0 V to 100 V
Voltage on HB, VHB 12 V to 112 V
Output 4 V, 20 A
Frequency 200 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Switching the MOSFETs
Achieving optimum drive performance at high frequency efficiently requires special attention to layout and
minimizing parasitic inductances. Take care at the driver die and package level as well as the PCB layout to
reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and
current flow paths during the turnon and turnoff of the MOSFET by charging and discharging its CGS
capacitance.
Figure 23. MOSFET Drive Paths and Circuit Parasitics
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: UCC27200A UCC27201A
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
Voltage
Current
Voltage
Current
t, ns
LO Falling, V or A
2 1 0 1 2 3 4 5
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
LO Current, A
LO Voltage, V
UCC27200A
,
UCC27201A
SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
www.ti.com
The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of
the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual
measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the
drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time.
Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the
actual switching process and limitations due to parasitic inductances.
Figure 25. Turnoff Voltage and Current Switching Diagram
Figure 24. Turnoff Voltage and Current vs Time
Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason
the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is
specified as 0.18 V at 100-mA dc current implying 1.8-ΩRDS(on). With 12-V drive voltage, no parasitic inductance
and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side
drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current
waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver
MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately
3.3 A as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The
internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads. The
SON-8 package reduces the internal parasitic inductances by more than 50%.
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,
UCC27201A
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SLUSAF9B –FEBRUARY 2011–REVISED JULY 2015
Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and
fall time of 7 ns is conservatively rated.
Figure 26. VLO and VHO Rise Time, 1-nf Load, 5 ns/div Figure 27. VLO and VHO Fall Time, 1-nf Load, 5-ns/div
8.2.2.2 Dynamic Switching of the MOSFETs
The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold
voltage. Using the turnoff case as the example, when the gate to source threshold voltage is reached the drain
voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off
plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be
removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop, half-
bridge power converter was utilized to evaluate performance in actual applications. The schematic of the half-
bridge converter is shown in . The turn off waveforms of the UCC27200A driving two MOSFETs in parallel is
shown in Figure 28 and Figure 29.
Figure 29. VHO Fall Time in Half-Bridge Converter
Figure 28. VLO Fall Time in Half-Bridge Converter
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8.2.2.3 Delay Matching and Narrow Pulse Widths
The total delays encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The sync-buck topology switching
requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and
2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the
transformer if there is imbalance in the high and low side pulse widths in a steady-state condition.
Narrow pulse width performance is an important consideration when transient and short circuit conditions are
encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very
narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions.
The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and
narrow pulse width performance. The delay matching waveforms are shown in Figure 30 and Figure 31. The
UCC2720x driver narrow pulse performance is shown in Figure 32 and Figure 33.
Figure 30. VLO and VHO Rising Edge Delay Matching Figure 31. VLO and VHO Falling Edge Delay Matching
Figure 32. 20-ns Input Pulse Delay Matching Figure 33. 10-ns Input Pulse Delay Matching
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8.2.2.4 Boot Diode Performance
The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high-side bias
internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc
characteristics to consider are VFand dynamic resistance. A low VFand high dynamic resistance results in a
high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V
VFand dynamic resistance of 0.6 Ωfor reliable charge transfer to the bootstrap capacitor. The dynamic
characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified
with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than
with forward current applied. The UCC2720x boot diode recovery is specified at 20ns at IF= 20 mA, IREV = 0.5 A.
At 0 mA IFthe reverse recovery time is 15 ns.
Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every
switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to
charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the
voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often
less than a comparable Schottky diode.
8.2.3 Application Curves
Figure 35. VHO Fall Time in Half-Bridge Converter
Figure 34. VLO Fall Time in Half-Bridge Converter
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9 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 8 V to 17 V. The lower end of this
range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 17 V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias
voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the
device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification
VDD(hys).Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary
power supply output is smaller than the hysteresis specification of the device is important to avoid triggering
device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has
dropped below the V(OFF) threshold which must be accounted for while evaluating system shutdown timing
design requirements. Likewise, at system startup, the device does not begin operation until the VDD pin voltage
has exceeded above the V(ON) threshold. The quiescent current consumed by the internal circuit blocks of the
device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source
current pulses delivered by the HO pin is also supplied through the same VDD pin is important. As a result, every
time a current is sourced out of the HO pin a corresponding current pulse is delivered into the device through the
VDD pin. Thus ensuring that a local bypass capacitor is provided between the VDD and GND pins and located
as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount
capacitor is a must. TI recommends using a capacitor in the range 0.22 uF to 4.7 uF between VDD and GND. In
a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-uF
to 0.1-uF local decoupling capacitor is recommended between the HB and HS pins.
10 Layout
10.1 Layout Guidelines
To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.
• Locate the driver as close as possible to the MOSFETs.
• Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
• Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by
connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the
MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.
• Use similar rules for the HS node as for GND for the high side driver.
• Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is
preferable where possible.
• Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.
For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic
inductance.
• Avoid LIand HI(driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
• Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can
even lead to decreased reliability of the whole system.
These references and links to additional information may be found at www.ti.com.
1. Additional layout guidelines for PCB land patterns may be found in Application Brief SLUA271
2. Additional thermal performance guidelines may be found in Application Reports SLMA002 and SLMA004
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,
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www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•QFN/SON PCB Attachment,SLUA271
•PowerPAD Thermally Enhanced Package,SLMA002
•PowerPAD Made Easy,SLMA004
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
UCC27200A Click here Click here Click here Click here Click here
UCC27201A Click here Click here Click here Click here Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 3-Sep-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UCC27200AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A
UCC27200ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A
UCC27200ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A
UCC27200ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A
UCC27200ADRCR ACTIVE VSON DRC 9 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 200A
UCC27200ADRCT ACTIVE VSON DRC 9 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 200A
UCC27200ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200A
UCC27200ADRMT ACTIVE VSON DRM 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200A
UCC27201AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27201A
UCC27201ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201A
UCC27201ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201A
UCC27201ADPRR ACTIVE WSON DPR 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27201A
UCC27201ADPRT ACTIVE WSON DPR 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27201A
UCC27201ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27201A
UCC27201ADRCR ACTIVE VSON DRC 9 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 201A
UCC27201ADRCT ACTIVE VSON DRC 9 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 201A
UCC27201ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU
NIPDAUAG | Call TI Level-2-260C-1 YEAR -40 to 140 27201A
PACKAGE OPTION ADDENDUM
www.ti.com 3-Sep-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UCC27201ADRMT ACTIVE VSON DRM 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAG | Call TI Level-1-260C-UNLIM -40 to 140 27201A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27201A :
•Automotive: UCC27201A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 3-Sep-2018
Addendum-Page 3
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27200ADDAR SO
Power
PAD
DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27200ADR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
UCC27200ADRCR VSON DRC 9 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27200ADRCT VSON DRC 9 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27200ADRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27200ADRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADDAR SO
Power
PAD
DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
UCC27201ADPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
UCC27201ADRCR VSON DRC 9 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27201ADRCT VSON DRC 9 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27201ADRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27200ADDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
UCC27200ADR SOIC D 8 2500 340.5 338.1 20.6
UCC27200ADRCR VSON DRC 9 3000 367.0 367.0 35.0
UCC27200ADRCT VSON DRC 9 250 210.0 185.0 35.0
UCC27200ADRMR VSON DRM 8 3000 367.0 367.0 35.0
UCC27200ADRMT VSON DRM 8 250 210.0 185.0 35.0
UCC27201ADDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
UCC27201ADPRR WSON DPR 10 3000 367.0 367.0 35.0
UCC27201ADPRT WSON DPR 10 250 210.0 185.0 35.0
UCC27201ADR SOIC D 8 2500 340.5 338.1 20.6
UCC27201ADRCR VSON DRC 9 3000 367.0 367.0 35.0
UCC27201ADRCT VSON DRC 9 250 210.0 185.0 35.0
UCC27201ADRMR VSON DRM 8 3000 367.0 367.0 35.0
UCC27201ADRMT VSON DRM 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
4202561/G
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