Product Folder Sample & Buy Technical Documents Support & Community Tools & Software UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 UCC2720xA 120-V Boot, 3-A Peak, High-Frequency, High-Side and Low-Side Driver 1 Features 3 Description * The UCC2720xA family of high-frequency N-channel MOSFET drivers include a 120-V bootstrap diode and high-side/low-side driver with independent inputs for maximum control flexibility. This allows for N-channel MOSFET control in half-bridge, full-bridge, two-switch forward and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 1-ns between the turn-on and turn-off of each other. The UCC2720xA are based on the popular UCC27200/1 drivers, but offer some enhancements. In order to improve performance in noisy power supply environments the UCC2720xA has an enhanced ESD input structure and also has the ability to withstand a maximum of -18 V on its HS pin. 1 * * * * * * * * * * * * Drives Two N-Channel MOSFETs in High-Side and Low-Side Configuration Negative Voltage Handling on HS (-18V) Maximum Boot Voltage 120 V Maximum VDD Voltage 20 V On-Chip 0.65-V VF, 0.6- RD Bootstrap Diode Greater than 1 MHz of Operation 20-ns Propagation Delay Times 3-A Sink, 3-A Source Output Currents 8-ns Rise/7-ns Fall Time with 1000-pF Load 1-ns Delay Matching Undervoltage Lockout for High-Side and Low-Side Driver Offered in 8-Pin SOIC (D), PowerPADTM SOIC-8 (DDA), SON-8 (DRM), SON-9 (DRC) and SON-10 (DPR) Packages Specified from -40C to 140C 2 Applications * * * * * * * Power Supplies for Telecom, Datacom, and Merchant Markets Half-Bridge Applications and Full-Bridge Converters Isolated Bus Architecture Two-Switch Forward Converters Active-Clamp Forward Converters High-Voltage Synchronous-Buck Converters Class-D Audio Amplifiers Simplified Application Diagram +12V An on-chip bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold. Two versions of the UCC27200A are offered. The UCC27200A has high-noise immune CMOS input thresholds while the UCC27201A has TTL-compatible thresholds. Both devices are offered in an 8-pin SOIC (D), PowerPad SOIC-8 (DDA), SON-8 (DRM) package, a 9-pin SON-9 (DRC) package and a 10-pin SON-10 (DPR) package. Device Information(1) PART NUMBER UCC27200A, UCC27201A +100V UCC27201A SECONDARY SIDE CIRCUIT VDD HB DRIVE HI LI CONTROL HI PWM CONTROLLER PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm HSOP (8) 4.89 mm x 3.90 mm VSON (9) 3.00 mm x 3.00 mm VSON (8) 4.00 mm x 4.00 mm WSON (10) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. HO HS DRIVE LO LO UCC27200A/1A VSS ISOLATION AND FEEDBACK 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2011) to Revision B Page * Added Negative Voltage Handling on HS (-18 V) to Features List ...................................................................................... 1 * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Original (February 2011) to Revision A Page * Added SON-10 (DPR) Package to the List of FEATURES .................................................................................................... 1 * Added SON-10 (DPR) Package to the DESCRIPTION ......................................................................................................... 1 * Changed the PIN FUNCTIONS table ..................................................................................................................................... 4 * Added Additional PIN FUNCTIONS information..................................................................................................................... 4 * Added ordering information for the SON-10 (DPR)................................................................................................................ 5 * Added note, "DPR(SON-10) package comes either in a small reel of 250 pieces as part number UCC27200ADPRT, or large reels pieces as part number UCC27200ADPRR." .................................................................................................... 5 * Added the SON-10 package to the ORDERING INFORMATION table................................................................................. 5 * Added the SON-10 package to the THERMAL INFORMATION table ................................................................................... 5 * Changed the "Minimum input pulse width" value From: 50 ns Max To: 50 ns Typ................................................................ 7 2 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View VDD 1 HB 2 HO 3 HS 4 DDA Package 8-Pin SOIC With Exposed PowerPAD Top View 8 7 6 5 LO VSS LI HI VDD 1 HB 2 HO 3 6 LI HS 4 5 HI DRM Package 8-Pin SON Top View VDD 1 HB 2 HS 4 7 VSS 7 VSS 6 LI 9 LO 8 VSS 7 LI HO 3 6 HI HS 4 5 N/C VDD 1 HB 2 HO 3 Exposed Thermal Die Pad DRC Package 9-Pin SON Top View 8 LO Exposed Thermal Die Pad* 8 LO 5 HI Exposed Thermal Die Pad* DPR Package 10-Pin SON Top View VDD 1 HB 2 HO 3 HS NC 10 LO 9 VSS 8 LI 4 7 HI 5 6 NC Exposed Thermal Die Pad Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 3 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com Pin Functions PIN DRM/D/DDA DRC DPR VDD 1 1 1 I/O DESCRIPTION I Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 F to 1.0 F. HB 2 2 2 I High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 F to 0.1 F, the value is dependant on the gate charge of the high-side MOSFET however. HO 3 3 3 O High-side output. Connect to the gate of the high-side power MOSFET. HS 4 4 4 I High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI 5 6 7 I High-side input. LI 6 7 8 I Low-side input. VSS 7 8 9 O Negative supply terminal for the device which is generally grounded. LO 8 9 10 O Low-side output. Connect to the gate of the low-side power MOSFET. N/C -- 5 5/6 -- No connection. Pins labeled N/C have no connection. PowerPAD (1) -- -- -- -- Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. (1) 4 NAME Pin VSS and the exposed thermal die pad are internally connected on the DDA and DRM packages only. Electrically referenced to VSS (GND). Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature, unless noted, all voltages are with respect to VSS Supply voltage range, (2) (1) VDD Input voltages on LI and HI, VLI, VHI Output voltage on LO, VLO DC Repetitive pulse <100 ns (3) DC MIN MAX UNIT -0.3 20 V -0.3 20 V -0.3 VDD + 0.3 -2 VDD + 0.3 V VHS - 0.3 VHB + 0.3 VHS - 2 VHB + 0.3, (VHB - VHS <20) DC -1 120 Repetitive pulse <100 ns (3) -18 120 Voltage on HB, VHB -0.3 120 Voltage On HB-HS -0.3 120 V Operating virtual junction temperature range, TJ -40 150 C 300 C Output voltage on HO, VHO Voltage on HS, VHS Repetitive pulse <100 ns (3) Lead temperature (soldering, 10 sec.) Power dissipation at TA = 25C (D package) (4) V V V 1.3 W Power dissipation at TA = 25C (DDA package) (4) 2.7 W Power dissipation at TA = 25C (DRM package) (4) 3.3 W Power dissipation at TA = 25C (DRC package) (4) 2.86 W 150 C Storage temperature, Tstg (1) (2) (3) (4) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal. Values are verified by characterization and are not production tested. This data was taken using the JEDEC proposed high-K test PCB. See the THERMAL CHARACTERISTICS section for details. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VDD Supply voltage PARAMETER 8 12 17 V VHS Voltage on HS -1 105 V Voltage on HS, (repetitive pulse <100 ns) VHB Voltage on HB -15 110 V VHS + 8, VDD -1 VHS + 17, 115 V 50 V / ns -40 140 C Voltage slew rate on HS TJ Operating junction temperature range UNIT Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 5 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 6.4 Thermal Information THERMAL METRIC RJA (1) UCC27200A /UCC27201A UCC27200A /UCC27201A UCC27200A /UCC27201A DRM (VSON) DRC (VSON) DPR (WSON) D (SOIC) DDA (HSOP) 8 PINS 9 PINS 10 PINS 8 PINS 8 PINS UNIT 36.2 43.7 34.8 106.5 40.5 C/W RJC(top) Junction-to-case (top) thermal resistance 41.6 49.9 32.1 52.9 49 C/W RJB Junction-to-board thermal resistance 13.2 19.1 11.9 46.6 10.2 C/W JT Junction-to-top characterization parameter 0.6 0.6 0.2 9.6 3.1 C/W JB Junction-to-board characterization parameter 13.4 19.3 12.2 46.1 9.7 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 3.1 3.8 1.3 -- 1.5 C/W (1) Junction-to-ambient thermal resistance UCC27200A UCC27200A /UCC27201A /UCC27201A For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40C to +140C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IDD VDD quiescent current VLI = VHI = 0 0.4 0.8 UCC27200A f = 500 kHz, CLOAD = 0 2.5 4 UCC27201A f = 500 kHz, CLOAD = 0 3.8 5.5 mA IDDO VDD operating current IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8 mA IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4 mA IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.0005 1 IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 VHIT Input rising threshold UCC27200A VLIT Input falling threshold UCC27200A VIHYS Input voltage hysteresis UCC27200A 0.4 VHIT Input voltage threshold UCC27201A 1.7 VLIT Input voltage threshold UCC27201A VIHYS Input voltage Hysteresis UCC27201A RIN Input pulldown resistance UCC27201A 0.1 mA uA mA INPUT 5.8 3 0.8 8 5.4 V V V 2.5 1.6 V V 100 mV 100 200 350 k 6.2 7.1 7.8 V UNDERVOLTAGE PROTECTION (UVLO) VDD rising threshold VDD threshold hysteresis 0.5 VHB rising threshold 5.8 VHB threshold hysteresis 6.7 V 7.2 0.4 V V BOOTSTRAP DIODE VF Low-current forward voltage I VDD - HB = 100 A 0.65 0.85 V VFI High-current forward voltage I VDD - HB = 100 mA 0.85 1.1 V RD Dynamic resistance, VF/I I VDD - HB = 100 mA and 80 mA 0.6 1.0 6 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Electrical Characteristics (continued) over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40C to +140C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ILO = 100 mA 0.18 0.4 TJ = -40 to 125C ILO = -100 mA, VLOH = VDD VLO 0.25 0.4 TJ = -40 to 140C ILO = -100 mA, VLOH = VDD VLO 0.25 0.42 UNIT LO GATE DRIVER VLOL VLOH Low level output voltage High level output voltage V V Peak pullup current VLO = 0 V 3 A Peak pulldown current VLO = 12 V 3 A HO GATE DRIVER VHOL VHOH Low level output voltage IHO = 100 mA 0.18 0.4 TJ = -40 to 125C IHO = -100 mA, VHOH = VHBVHO 0.25 0.4 TJ = -40 to 140C IHO = -100 mA, VHOH = VHBVHO 0.25 0.42 High level output voltage V V Peak pullup current VHO = 0 V 3 A Peak pulldown current VHO = 12 V 3 A TJ = -40 to 125C CLOAD = 0 20 45 TJ = -40 to 140C CLOAD = 0 20 50 TJ = -40 to 125C CLOAD = 0 20 45 TJ = -40 to 140C CLOAD = 0 20 50 TJ = -40 to 125C CLOAD = 0 20 45 TJ = -40 to 140C CLOAD = 0 20 50 TJ = -40 to 125C CLOAD = 0 20 45 TJ = -40 to 140C CLOAD = 0 20 50 PROPAGATION DELAYS tDLFF VLI falling to VLO falling tDHFF VHI falling to VHO falling tDLRR VLI rising to VLO rising tDHRR VHI rising to VHO rising ns ns ns ns DELAY MATCHING tMON LI ON, HI OFF 1 7 ns tMOFF LI OFF, HI ON 1 7 ns OUTPUT RISE AND FALL TIME tR LO, HO CLOAD = 1000 pF 8 tF LO, HO CLOAD = 1000 pF 7 ns tR LO, HO (3 V to 9 V) CLOAD = 0.1 F 0.35 0.6 us tF LO, HO (3 V to 9 V) CLOAD = 0.1 F 0.3 0.6 us ns MISCELLANEOUS Minimum input pulse width that changes the output Bootstrap diode turnoff time (1) (2) IF = 20 mA, IREV = 0.5 A (1) (2) 50 ns 20 ns Typical values for TA = 25C IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 7 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO TMON TMOFF Figure 1. Timing Diagram 6.6 Typical Characteristics 10.0 10.0 VDD = 12 V No Load on Outputs VDD = 12 V No Load on Outputs 150oC IDDO - Operating Current - mA IDDO - Operating Current - mA 25oC 150oC 125oC 1.0 25oC -40oC 0.1 125oC 1.0 -40oC 0.1 10 100 1000 100 10 Frequency - kHz Figure 2. UCC27200A IDD Operating Current vs Frequency 8 Submit Documentation Feedback 1000 Frequency - kHz Figure 3. UCC27201A IDD Operating Current vs Frequency Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Typical Characteristics (continued) 10.0 1.0 HB = 12 V No Load on Outputs IHBSO - Operating Current - mA IHBO - Operating Current - mA HB = 12 V No Load on Outputs 150oC 125oC 1.0 25oC o -40 C 0.1 150oC 0.01 25oC 125oC 0.1 -40oC 0.001 100 10 1000 100 10 Frequency - kHz Figure 4. Boot Voltage Operating Current vs Frequency Figure 5. HB to VSS Operating Current vs Frequency 2.0 T = 25oC T = 25oC HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 50 Rising 48 46 Falling 44 42 40 1.8 Rising Falling 1.6 1.4 1.2 1.0 8 10 12 14 16 18 8 20 10 12 16 14 18 20 VDD - Supply Voltage - V VDD - Supply Voltage - V Figure 6. UCC27200A Input Threshold vs Supply Voltage Figure 7. UCC27201A Input Threshold vs Supply Voltage 50 2.0 VDD = 12 V VDD = 12 V HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 1000 Frequency - kHz 48 Rising 46 Falling 44 42 40 1.8 Rising 1.6 Falling 1.4 1.2 1.0 -50 -25 0 25 50 75 100 125 150 -50 -25 TA - Temperature - oC Figure 8. UCC27200A Input Threshold vs Temperature 0 25 50 75 100 125 150 TA - Temperature - oC Figure 9. UCC27201A Input Threshold vs Temperature Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 9 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com Typical Characteristics (continued) 0.45 ILO = IHO = -100 mA 0.35 VDD = VHB = 12 V 0.30 VDD = VHB = 8 V 0.25 0.20 0.15 0.10 VDD = VHB = 20 V 0.35 VDD = VHB = 16 V 0.30 VDD = VHB = 12 V 0.25 VDD = VHB = 8 V 0.20 0.15 0.10 0.05 0.05 0.0 0.0 -50 -25 0 25 50 75 100 ILO = IHO = 100 mA 0.40 VOL - LO/HO Output Voltage - V VOH - LO/HO Output Voltage - V 0.40 0.45 VDD = VHB = 16 V 125 150 VDD = VHB = 20 V -50 -25 0 25 TA - Temperature - oC 50 75 100 125 150 TA - Temperature - oC Figure 10. Lo and Ho High Level Output Voltage vs Temperature Figure 11. Lo and Ho Low Level Output Voltage vs Temperature 7.8 0.8 7.6 0.7 7.4 Hysteresis - V Threshold - V 0.6 VDD Rising Threshold 7.2 7.0 6.8 6.6 VDD UVLO Hysteresis 0.5 0.4 HB UVLO Hysteresis 0.3 HB Rising Threshold 6.4 0.2 6.2 0.1 6.0 5.8 0 -50 -25 0 25 50 75 100 125 150 -50 -25 75 100 125 150 Figure 13. Undervoltage Lockout Threshold Hysteresis vs Temperature 36 36 VDD = VHD = 12 V 34 VDD = VHB = 12 V 34 TDHFF 32 TDHRR 28 26 24 22 20 TDLFF 18 Propagation Delay - ns 32 30 Propagation Delay - ns 50 TA - Temperature - oC Figure 12. Undervoltage Lockout Threshold vs Temperature 30 28 26 24 22 TDLFF TDLRR 20 18 16 TDHFF 16 TDHRR TDLRR 14 14 -50 -25 0 50 75 25 100 TA - Temperature - oC 125 150 Figure 14. UCC27200A Propagation Delays vs Temperature 10 25 0 TA - Temperature - oC Submit Documentation Feedback -50 -25 0 25 50 75 100 125 150 TA - Temperature - oC Figure 15. UCC27201A Propagation Delays vs Temperature Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Typical Characteristics (continued) 26 26 T = 25oC T = 25oC 24 Propagation Delay - ns Propagation Delay - ns 24 22 LI Falling 20 LI Rising HI Falling LI Falling 22 LI Rising 20 HI Rising HI Rising 18 HI Falling 16 18 8 10 12 14 16 18 20 8 12 10 VDD = VHB - Supply Voltage - V 14 16 18 20 VDD = VHB - Supply Voltage - V Figure 16. UCC27200A Propagation Delay vs Supply Voltage Figure 17. UCC27201A Propagation Delay vs Supply Voltage 7 3.5 V DD = VHB = 12 V VDD = VHB = 12 V 6 Delay Matching - ns 5 4 UCC27200ATMOFF 3 UCC27201ATMOFF UCC27201ATMON UCC27200ATMON 2 ILO, IHO - Output Current - A 3.0 2.5 Pull-Down Current Pull-Up Current 2.0 1.5 1.0 0.5 1 0 0 -50 -25 0 25 50 75 100 125 0 150 2 4 6 8 10 12 VLO, VHO - Output Voltage - V ? TA - Temperature - C Figure 18. Delay Matching vs Temperature Figure 19. Output Current vs Output Voltage 700 100.0 Inputs Low T = 25oC 600 IDD, IHB - Supply Current - mA Diode Current - mA 10.0 1.0 0.1 500 IHB 400 300 IDD 200 0.01 100 0.001 0 0.5 0.6 0.7 0.8 0.9 0 Diode Voltage - V 4 8 12 16 20 VDD, VHB - Supply Voltage - V Figure 20. Diode Current vs Diode Voltage Figure 21. Quiescent Current vs Supply Voltage Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 11 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 7 Detailed Description 7.1 Overview The UCC27200A and UCC27201A are high-side and low-side drivers. The high-side and low-side each have independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27200A and UCC27201A. The UCC27200A is the CMOS compatible input version and the UCC27201A is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS) which is typically the source pin of the high side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages. 7.2 Functional Block Diagram 2 HB 3 HO 4 HS 8 LO 7 VSS UVLO LEVEL SHIFT HI 5 VDD 1 UVLO LI 6 7.3 Feature Description 7.3.1 Input Stages The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200A is 200 k nominal and input capacitance is approximately 2 pF. The 200 k is a pulldown resistance to Vss (ground). The CMOS-compatible input of the UCC27200A provides a rising threshold of 48% of VDD and falling threshold of 45% of VDD. The inputs of the UCC27200A are intended to be driven from 0 to VDD levels. The input stages of the UCC27201A incorporate an open-drain configuration to provide the lower input thresholds. The input impedance is 200 k nominal and input capacitance is approximately 4 pF. The 200 k is a pulldown resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and a falling threshold of 1.6 V. 7.3.1.1 UVLO (Undervoltage Lockout) The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 6.7 V with 0.4-V hysteresis. 12 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Feature Description (continued) 7.3.1.2 Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. 7.3.1.3 Boot Diode The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation. 7.3.1.4 Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS. 7.4 Device Functional Modes The device operates in normal mode and VULO mode. See UVLO (Undervoltage Lockout) for more information on UVLO operation mode. In normal mode, the output stage is dependent on the sates of the HI and LI pins. Table 1. Device Logic Table LI PIN HO (1) L L L L L H L H H L H L H H H H HI PIN (1) (2) LO (2) HO is measured with respect to the HS. LO is measured with respect to the VSS. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 13 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation will be often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. 8.2 Typical Application An open loop half-bridge converter was used to calculate performance in an actual application. + + + Figure 22. Open Loop Half-Bridge Converter 14 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Typical Application (continued) 8.2.1 Design Requirements UCC27201A Design Requirements DESIGN PARAMETER EXAMPLE VALUE Supply Voltage, VDD 12 V Voltage on HS, VHS 0 V to 100 V Voltage on HB, VHB 12 V to 112 V Output 4 V, 20 A Frequency 200 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Switching the MOSFETs Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Take care at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and current flow paths during the turnon and turnoff of the MOSFET by charging and discharging its CGS capacitance. L bond wire L pin 1 VDD I SOURCE Rsource Driver Output Stage L trace Cvdd L pin L trace L bond wire 8 Rg LO I sink Rsink L pin L trace L bond wire 7 L trace Cgs Vss Figure 23. MOSFET Drive Paths and Circuit Parasitics Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 15 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time. Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actual switching process and limitations due to parasitic inductances. 12 12 11 11 10 10 9 8 9 7 8 7 5 4 LO Voltage, V LO Falling, V or A 6 3 2 1 0 5 4 3 2 1 2 1 3 4 5 6 0 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 3 t, ns 2 1 0 1 2 3 4 5 Voltage LO Current, A Current Figure 24. Turnoff Voltage and Current vs Time Figure 25. Turnoff Voltage and Current Switching Diagram Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA dc current implying 1.8- RDS(on). With 12-V drive voltage, no parasitic inductance and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver MOSFET'S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately 3.3 A as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads. The SON-8 package reduces the internal parasitic inductances by more than 50%. 16 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and fall time of 7 ns is conservatively rated. UCC27200A UCC27200A Figure 26. VLO and VHO Rise Time, 1-nf Load, 5 ns/div 8.2.2.2 Figure 27. VLO and VHO Fall Time, 1-nf Load, 5-ns/div Dynamic Switching of the MOSFETs The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turnoff case as the example, when the gate to source threshold voltage is reached the drain voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop, halfbridge power converter was utilized to evaluate performance in actual applications. The schematic of the halfbridge converter is shown in . The turn off waveforms of the UCC27200A driving two MOSFETs in parallel is shown in Figure 28 and Figure 29. UCC27200A UCC27200A Figure 28. VLO Fall Time in Half-Bridge Converter Figure 29. VHO Fall Time in Half-Bridge Converter Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 17 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 8.2.2.3 Delay Matching and Narrow Pulse Widths The total delays encountered in the PWM, driver and power stage need to be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and 2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the transformer if there is imbalance in the high and low side pulse widths in a steady-state condition. Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions. The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 30 and Figure 31. The UCC2720x driver narrow pulse performance is shown in Figure 32 and Figure 33. 18 Figure 30. VLO and VHO Rising Edge Delay Matching Figure 31. VLO and VHO Falling Edge Delay Matching Figure 32. 20-ns Input Pulse Delay Matching Figure 33. 10-ns Input Pulse Delay Matching Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 8.2.2.4 Boot Diode Performance The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high-side bias internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc characteristics to consider are VF and dynamic resistance. A low VF and high dynamic resistance results in a high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V VF and dynamic resistance of 0.6 for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than with forward current applied. The UCC2720x boot diode recovery is specified at 20ns at IF = 20 mA, IREV = 0.5 A. At 0 mA IF the reverse recovery time is 15 ns. Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often less than a comparable Schottky diode. 8.2.3 Application Curves UCC27200A UCC27200A Figure 34. VLO Fall Time in Half-Bridge Converter Figure 35. VHO Fall Time in Half-Bridge Converter Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 19 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 9 Power Supply Recommendations The bias supply voltage range for which the device is rated to operate is from 8 V to 17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys).Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above the V(ON) threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the HO pin a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends using a capacitor in the range 0.22 uF to 4.7 uF between VDD and GND. In a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-uF to 0.1-uF local decoupling capacitor is recommended between the HB and HS pins. 10 Layout 10.1 Layout Guidelines To * * * * * * * * improve the switching characteristics and efficiency of a design, the following layout rules should be followed. Locate the driver as close as possible to the MOSFETs. Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver. Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S) drain or source current. Use similar rules for the HS node as for GND for the high side driver. Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is preferable where possible. Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another. For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance. Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads. Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system. These references and links to additional information may be found at www.ti.com. 1. Additional layout guidelines for PCB land patterns may be found in Application Brief SLUA271 2. Additional thermal performance guidelines may be found in Application Reports SLMA002 and SLMA004 20 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A UCC27200A, UCC27201A www.ti.com SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 10.2 Layout Example Figure 36. Example Component Placement Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A Submit Documentation Feedback 21 UCC27200A, UCC27201A SLUSAF9B - FEBRUARY 2011 - REVISED JULY 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: * QFN/SON PCB Attachment, SLUA271 * PowerPAD Thermally Enhanced Package, SLMA002 * PowerPAD Made Easy, SLMA004 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY UCC27200A Click here Click here Click here Click here Click here UCC27201A Click here Click here Click here Click here Click here 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: UCC27200A UCC27201A PACKAGE OPTION ADDENDUM www.ti.com 3-Sep-2018 PACKAGING INFORMATION Orderable Device Status (1) UCC27200AD ACTIVE Package Type Package Pins Package Drawing Qty SOIC Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A UCC27200ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A UCC27200ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A UCC27200ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27200A UCC27200ADRCR ACTIVE VSON DRC 9 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 200A UCC27200ADRCT ACTIVE VSON DRC 9 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 200A UCC27200ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200A UCC27200ADRMT ACTIVE VSON DRM 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200A UCC27201AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27201A UCC27201ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201A UCC27201ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201A UCC27201ADPRR ACTIVE WSON DPR 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC 27201A UCC27201ADPRT ACTIVE WSON DPR 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC 27201A UCC27201ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 27201A UCC27201ADRCR ACTIVE VSON DRC 9 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 201A UCC27201ADRCT ACTIVE VSON DRC 9 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 140 201A UCC27201ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG | Call TI Level-2-260C-1 YEAR -40 to 140 27201A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 3-Sep-2018 Status (1) UCC27201ADRMT ACTIVE Package Type Package Pins Package Drawing Qty VSON DRM 8 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Green (RoHS CU NIPDAUAG | Call TI Level-1-260C-UNLIM & no Sb/Br) Device Marking (4/5) -40 to 140 27201A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27201A : * Automotive: UCC27201A-Q1 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 3-Sep-2018 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC27200ADDAR Package Package Pins Type Drawing SO Power PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200ADR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200ADRCR VSON DRC 9 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27200ADRCT VSON DRC 9 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27200ADRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27200ADRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201ADDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 UCC27201ADPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201ADPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201ADR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 UCC27201ADRCR VSON DRC 9 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27201ADRCT VSON DRC 9 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27201ADRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201ADRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27200ADDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0 UCC27200ADR SOIC D 8 2500 340.5 338.1 20.6 UCC27200ADRCR VSON DRC 9 3000 367.0 367.0 35.0 UCC27200ADRCT VSON DRC 9 250 210.0 185.0 35.0 UCC27200ADRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27200ADRMT VSON DRM 8 250 210.0 185.0 35.0 UCC27201ADDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0 UCC27201ADPRR WSON DPR 10 3000 367.0 367.0 35.0 UCC27201ADPRT WSON DPR 10 250 210.0 185.0 35.0 UCC27201ADR SOIC D 8 2500 340.5 338.1 20.6 UCC27201ADRCR VSON DRC 9 3000 367.0 367.0 35.0 UCC27201ADRCT VSON DRC 9 250 210.0 185.0 35.0 UCC27201ADRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27201ADRMT VSON DRM 8 250 210.0 185.0 35.0 Pack Materials-Page 2 www.ti.com GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. 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