Single/Dual, +15 V/±5 V, 256-Position,
I2C-Compatible Digital Potentiometer
AD5280/AD5282
Rev. C
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FEATURES
AD5280: 1 channel
AD5282: 2 channels
256 positions
+10 V to +15 V single supply; ±5.5 V dual-supply operation
Fixed terminal resistance: 20 kΩ, 50 kΩ, 200 kΩ
Low temperature coefficient: 30 ppm/°C
Power-on midscale preset1
Programmable reset
Operating temperature: −40oC to +85oC
I2C-compatible interface
APPLICATIONS
Multimedia, video, and audio
Communications
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage source
Programmable current source
Line impedance matching
GENERAL DESCRIPTION
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs)2.
The devices perform the same electronic adjustment function
as a potentiometer, trimmer, or variable resistor. Each VR offers
a completely programmable value of resistance between the
A terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has
a 1% channel-to-channel matching tolerance. The nominal
temperature coefficient of both parts is 30 parts per million/
degrees centigrade (ppm/°C). Another key feature is that the
parts can operate up to +15 V or ±5 V.
Wiper position programming defaults to midscale at system
power-on. When powered, the VR wiper position is programmed
by an I2C-compatible, 2-wire serial data interface. The AD5280/
AD5282 feature sleep mode programmability. This allows any
level of preset in power-up and is an alternative to a costly
EEPROM solution. Both parts have additional programmable
logic outputs that enable users to drive digital loads, logic gates,
LED drivers, and analog switches in their system.
1 Assert shutdown and program the device during power-up, then deassert
the shutdown to achieve the desired preset level.
2 The terms digital potentiometer, VR, and RDAC are used interchangeably.
The AD5280/AD5282 are available in thin, surface-mounted
14-lead TSSOP and 16-lead TSSOP. All parts are guaranteed to
operate over the extended industrial temperature range of
−40°C to +85°C. For 3-wire SPI-compatible interface applica-
tions, see the AD5260/AD5262 product information on
www.analog.com.
FUNCTIONAL BLOCK DIAGRAMS
A
WB O
1
O
2
RDAC REGISTER OUTPUT REGISTER
SERIAL INPUT REGISTER
AD5280
S
HDN
V
DD
V
SS
SDA
SCL
GND
AD0 AD1
ADDRESS
CODE PWR ON
RESET
V
L
8
02929-070
Figure 1. AD5280
A
1
W
1
B
1
O
1
RDAC1 REGISTER RDAC2 REGISTER
OUTPUT
REGISTER
SERIAL INPUT REGISTER
AD5282
SHDN
V
DD
SDA
SCL
GND
AD0 AD1
A
2
W
2
B
2
ADDRESS
CODE PWR ON
RESET
8
02929-001
V
DD
V
SS
V
L
Figure 2. AD5282
AD5280/AD5282
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 14
Rheostat Operation .................................................................... 14
Potentiometer Operation........................................................... 14
Digital Interface .............................................................................. 16
2-Wire Serial Bus ........................................................................ 16
Readback RDAC Value .............................................................. 17
Additional Programmable Logic Output ................................ 17
Self-Contained Shutdown Function and Programmable
Preset ............................................................................................ 17
Multiple Devices on One Bus ................................................... 17
Level Shift for Bidirectional Interface ...................................... 18
Level Shift for Negative Voltage Operation ............................ 18
ESD Protection ........................................................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
Layout and Power Supply Bypassing ....................................... 19
Applications Information .............................................................. 20
Bipolar DC or AC Operation from Dual Supplies ................. 20
Gain Control Compensation .................................................... 20
15 V, 8-Bit I2C DAC .................................................................... 20
8-Bit Bipolar DAC ...................................................................... 21
Bipolar Programmable Gain Amplifier ................................... 21
Programmable Voltage Source with Boosted Output ........... 21
Programmable Current Source ................................................ 22
Programmable Bidirectional Current Source ......................... 22
Programmable Low-Pass Filter ................................................ 23
Programmable Oscillator .......................................................... 23
RDAC Circuit Simulation Model ............................................. 24
Macro Model Net List for RDAC ............................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
7/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Updated Outline Dimensions, RU-14 ......................................... 25
Changes to Ordering Guide .......................................................... 26
8/07—Rev. A to Rev. B
Updated Operating Temperature Range Throughout ................... 1
Changes to the Features Section ....................................................... 1
Changes to the General Description Section .................................. 1
Changes to Table 2 .............................................................................. 3
Added the Thermal Resistance Section ........................................... 5
Changes to the Ordering Guide ...................................................... 26
11/05—Rev. 0 to Rev. A
Updated Format ................................................................... Universal
Updated Outline Dimensions ......................................................... 26
Changes to Ordering Guide ............................................................ 27
10/02—Revision 0: Initial Version
AD5280/AD5282
Rev. C | Page 3 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = −5 V; VLOGIC = 5 V, VA = +VDD, VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS–RHEOSTAT MODE
Resistor Differential NL2R-DNL RWB, VA = NC −1 ±1/4 +1 LSB
Resistor Nonlinearity2
R-INL RWB, VA = NC −1 ±1/4 +1 LSB
Nominal Resistor Tolerance3ΔRAB TA = 25°C −30 +30 %
Resistance Temperature
Coefficient
(∆RAB/RAB)/∆T x 106
VAB = VDD, wiper = no connect 30 ppm/°C
Wiper Resistance RW IW = VDD/R, VDD = 3 V or 5 V 60 150 Ω
DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs)
Resolution N
8 Bits
Integral Nonlinearity4INL −1 ±1/4 +1 LSB
Differential Nonlinearity4
DNL −1 ±1/4 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T x 106 Code = 0x80 5 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −2 −1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 +1 +2 LSB
RESISTOR TERMINALS
Voltage Range5VA, VB, VW VSS VDD V
Capacitance A, B6CA, CB f = 5 MHz, measured to GND,
Code = 0x80
25 pF
Capacitance W6
CW f = 1 MHz, measured to GND,
Code = 0x80
55 pF
Common-Mode Leakage ICM VA = VB = VW 1 nA
Shutdown Current ISHDN
5 μA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 0.7 × VL VL + 0.5 V
Input Logic Low VIL 0 0.3 × VL V
Output Logic High (O1, O2) VIH 4.9 V
Output Logic Low (O1, O2) VIL
0.4 V
Input Current IIL VIN = 0 V or 5 V ±1 μA
Input Capacitance6
CIL
5 pF
POWER SUPPLIES
Logic Supply VLOGIC 2.7 VDD V
Power Single-Supply Range VDD RANGE VSS = 0 V 4.5 16.5 V
Power Dual-Supply Range VDD/SS RANGE ±4.5 ±5.5 V
Logic Supply Current ILOGIC VLOGIC = 5 V 60 μA
Positive Supply Current IDD VIH = 5 V or VIL = 0 V 0.1 1 μA
Negative Supply Current ISS
0.1 1 μA
Power Dissipation7PDISS VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = −5
V
0.2 0.3 mW
Power Supply Sensitivity PSS
0.002 0.01 %/%
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth −3 dB BW_20K RAB = 20 kΩ, Code = 0x80 310 kHz
BW_50K RAB = 50 kΩ, Code = 0x80 150 kHz
BW_200K RAB = 200 kΩ, Code = 0x80 35 kHz
AD5280/AD5282
Rev. C | Page 4 of 28
Parameter Symbol Conditions Min Typ1Max Unit
Total Harmonic Distortion THDW VA = 1 V rms, RAB = 20 kΩ 0.014 %
VB = 0 V dc, f = 1 kHz
VW Settling Time tS VA = 5 V, VB = 5 V, ±1 LSB error band 5 μs
Crosstalk CT
VA = VDD, VB = 0 V, measure VW1 with
adjacent RDAC making full-scale
code change
15 nV-s
Analog Crosstalk CTA Measure VW1 with VW2 = 5 V p-p @ f =
10 kHz
−62 dB
Resistor Noise Voltage eN_WB RWB = 20 kΩ, f = 1 kHz 18 nV/√Hz
INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11
SCL Clock Frequency fSCL 0 400 kHz
tBUF Bus Free Time Between
Stop and Start
t1 1.3 μs
tHD:STA Hold Time (Repeated
Start)
t2 After this period, the first clock pulse
is generated
0.6 μs
tLOW Low Period of SCL Clock t3 1.3 μs
tHIGH High Period of SCL Clock t4 0.6 μs
tSU:STA Setup Time for Start
Condition
t5 0.6 μs
tHD:DAT Data Hold Time t6 0 0.9 μs
tSU:DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and
SCL Signals
t8
300 ns
tR Rise Time of Both SDA and
SCL Signals
t9
300 ns
tSU:STO Setup Time for STOP
Condition
t10 0.6 μs
02929-042
1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram (Figure 3) for location of measured values.
11 Standard I2C mode operation is guaranteed by design.
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 3. Detailed Timing Diagram
AD5280/AD5282
Rev. C | Page 5 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VDD to GND −0.3 V to +16.5 V
VSS to GND 0 V to −7 V
VDD to VSS 16.5 V
VA, VB, VW to GND VSS to VDD
AX to BX, AX to WX, BX to WX
Intermittent1±20 mA
Continuous ±5 mA
VLOGIC to GND 0 V to 7 V
Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
1 Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. Package
power dissipation = (TJMAX − TA)/ θJA .
Table 3. Thermal Resistance
Package Type θJA Unit
TSSOP-14 206 °C/W
TSSOP-16 150 °C/W
ESD CAUTION
AD5280/AD5282
Rev. C | Page 6 of 28
SDA
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
W
B
SHDN
SCL
V
DD
1
2
3
4
5
6
14
13
12
11
10
9
7 8
O
1
V
L
O
2
GND
AD1
V
SS
AD5280
TOP VIEW
AD0
02929-002
O
1
A
1
W
1
V
DD
SHDN
B
1
SCL
A
2
W
2
B
2
V
SS
GND
V
L
AD1
116
215
314
Figure 4. AD5280 Pin Configuration
413
512
6
7
SDA
8
11
10
9
AD0
AD5282
TOP VIEW
02929-003
Figure 5. AD5282 Pin Configuration
Table 4. AD5280 Pin Function Descriptions
Pin No. Mnemonic Description
1 A Resistor Terminal A.
2 W Wiper Terminal W.
3 B Resistor Terminal B.
4 VDD Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
5 SHDN Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can also be used as a
programmable preset in power-up.
6 SCL Serial Clock Input.
7 SDA Serial Data Input/Output.
8 AD0 Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
9 AD1 Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
10 GND Common Ground.
11 VSS Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
12 O2 Logic Output Terminal O2.
13 VL Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5280.
14 O1 Logic Output Terminal O1.
Table 5. AD5282 Pin Function Descriptions
Pin No. Mnemonic Description
1 O1 Logic Output Terminal O1.
2 A1 Resistor Terminal A1.
3 W1 Wiper Terminal W1.
4 B1 Resistor Terminal B1.
5 VDD Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
6 SHDN Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can be also used as a
programmable preset in power-up.
7 SCL Serial Clock Input.
8 SDA Serial Data Input/Output.
9 AD0 Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
10 AD1 Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
11 GND Common Ground.
12 VSS Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
13 VL Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5282.
14 B2 Resistor Terminal B2.
15 W2 Wiper Terminal W2.
16 A2 Resistor Terminal A2.
AD5280/AD5282
Rev. C | Page 7 of 28
–1.0
0 32 96 160 22464 128 192 256
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
RHEOSTAT MODE R-INL (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.6
–0.8
0
–0.4
02929-004
±5V
+15V
+5V
R
AB
= 20k
T
A
= 25°C
Figure 6. R-INL vs. Code vs. Supply Voltages
CODE (Decimal)
RHEOSTAT MODE R-DNL (LSB)
0.5
0.4
0.3
0.2
0.1
–0.1
–0.3
–0.8
0
–0.2
02929-005
CODE (Decimal)
POTENTIOMETER MODE DNL (LSB)
0.5
0.4
0.3
0.2
0.1
–0.1
–0.3
–0.4
0
–0.2
–0.5
0 32 96 160 22464 128 192 256
02929-007
R
AB
= 20k
T
A
= –40°C T
A
= +85°C
T
A
= +25°C
Figure 9. DNL vs. Code, VDD/VSS = ±5 V
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.6
–0.8
0
–0.4
–1.0
0 32 96 160 22464 128 192 256
02929-008
–0.5
0 32 96 160 22464 128 192 256
±5V +15V
+5V
R
AB
= 20k
T
A
= 25°C
Figure 7. R-DNL vs. Code vs. Supply Voltages
CODE (Decimal)
–1.0
0 32 96 160 22464 128 192 256
POTENTIOMETER MODE INL (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.6
–0.8
0
–0.4
02929-006
T
A
= +85°C
T
A
= –40°C
T
A
= +25°C
R
AB
= 20k
Figure 8. INL vs. Code, VDD/VSS = ±5 V
±5V
+5V
R
AB
= 20k
T
A
= 25°C
+15V
POTENTIOMETER MODE INL (LSB)
0.5
0.4
0.3
0.2
0.1
–0.1
–0.3
–0.4
0
–0.2
–0.5
0 32 96 160 22464 128 192 256
02929-009
Figure 10. INL vs. Code vs. Supply Voltages
CODE (Decimal)
R
AB
= 20k
T
A
= 25°C
±5V
+5V
+15V
Figure 11. DNL vs. Code vs. Supply Voltages
AD5280/AD5282
Rev. C | Page 8 of 28
929-010
|V
DD
– V
SS
| (V)
–1.0
0 5 10 15 20
02
INL (LSB)
1.0
0.5
–0.5
0
R
AB
= 20k
T
A
= 25°C
AVG +3
AVG
AVG –3
Figure 12. INL Over Supply Voltage
|V
DD
– V
SS
| (V)
–2.0
0 5 10 15 20
02
R-INL (LSB)
2.0
1.0
1.5
0.5
–1.0
–0.5
0
TEMPERATURE (°C)
ZERO-SCALE ERROR (LSB)
2.0
1.6
1.8
1.2
1.4
0.4
0.8
0.6
0.2
1.0
0
–40 0–20 20 40 60 80 100
02929-013
R
AB
= 20k
V
DD
/V
SS
= +5V/0V
V
DD
/V
SS
= +15V/0V
V
DD
/V
SS
= ±5V
TEMPERATURE (°C)
I
DD
/I
SS
SUPPLY CURRENT (nA)
1000
100
10
1
–40 –7 26 59 85
02929-014
Figure 15. Zero-Scale Error
–1.5
929-011
R
AB
= 20k
T
A
= 25°C
AVG +3
AVG
AVG –3
Figure 13. R-INL Over Supply Voltage
R
AB
= 20kV
LOGIC
= +5V
V
IH
= +5V
V
IL
= 0V
TEMPERATURE (°C)
–1.8
–2.0
–40 0–20 20 40 60 80 100
02929-012
FULL-SCALE ERROR (LSB)
0
–0.4
–0.2
–0.8
–0.6
–1.6
–1.2
–1.4
–1.0
R
AB
= 20k
V
DD
/V
SS
= +15V/0V
V
DD
/V
SS
= +5V/0V
V
DD
/V
SS
= ±5V
Figure 14. Full-Scale Error
|
DD
@V
DD
/V
SS
= ±5V
|
SS
@V
DD
/V
SS
= ±5V
|
SS
@V
DD
/V
SS
= +15V/0V
Figure 16. Supply Current vs. Temperature
TEMPERATURE (°C)
23.0
–40 –7 26 59 85
0292
I
LOGIC
(µA)
26.0
25.0
24.0
23.5
24.5
25.5
9-015
V
DD
/V
SS
= ±5V
V
DD
/V
SS
= +15V/0V
R
AB
= 20k
Figure 17. VLOGIC Supply Current vs. Temperature
AD5280/AD5282
Rev. C | Page 9 of 28
I
LOGIC
(µA)
1000
100
5
929-016
FREQUENCY (Hz)
GAIN (dB)
0
–30
–24
–12
–18
–6
–36
–48
–42
–54
–60
0 10k 100k 1M
02929-019
V
IH
(V)
10
01234
02
80H
R
AB
= 20k
T
A
= 25°C
20H
V
DD
/V
SS
= 5V/0V
V
LOGIC
= 3V
V
DD
/V
SS
= 5V/0V
V
LOGIC
= 5V
RHEOST
10H
08H
04H
02H
01H
T
A
= 25°C
V
A
= 50mV rms
V
DD
/V
SS
= ±5V
40H
FREQUENCY (Hz)
GAIN (dB)
0
–30
–24
–12
–18
–6
–36
–48
–42
–54
–60
0 10k 100k 1M
02929-020
Figure 18. VLOGIC Supply Current vs. Digital Input Voltage
CODE (Decimal)
AT MODE TEMPCO (ppm/°C)
700
300
400
500
600
200
100
0
–100
9-017
–200
0 32 64 19296 128 224 256
0292
T
A
= 25°C
20k
50k
200k
Figure 19. Rheostat Mode Tempco ΔRWB/ΔT vs. Code, VDD/VSS = ±5 V
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/°C)
120
40
60
80
100
20
0
–20
–40
0 32 64 19296 128 224 256
02929-018
T
A
= 25°C
20k
50k
200k
Figure 20. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code,
VDD/VSS = ±5 V
Figure 21. Gain vs. Frequency vs. Code, RAB = 20 kΩ
80H
20H
10H
08H
04H
02H
01H
T
A
= 25°C
V
A
= 50mV rms
V
DD
/V
SS
= ±5
40H
GAIN (dB)
0
–30
–24
–12
–18
–6
–36
–48
–42
–54
–60
02929-021
Figure 22. Gain vs. Frequency vs. Code, RAB = 50 kΩ
FREQUENCY (Hz)
0 10k 100k 1M
80H
40H
20H
10H
08H
04H
02H
01H
T
A
= 25°C
V
A
= 50mV rms
V
DD
/V
SS
= ±5V
Figure 23. Gain vs. Frequency vs. Code, RAB = 200 kΩ
AD5280/AD5282
Rev. C | Page 10 of 28
–54
9-022
FREQUENCY (Hz)
–60
0 10k 100k 1M
0292
GAIN (dB)
0
–30
–24
–12
–18
–6
–36
–48
–42
T = 25°C
FREQUENCY (MHz)
PSRR (dB)
80
40
60
20
0
100 1000 10k 100k 1M
02929-025
R = 20k
310kHz
CODE = 80
H
, V
A
= V
DD
, V
B
= 0V
A
V
DD
/V
SS
= ±5V
V
A
= 50mV rms
R = 50k
150kHz
R = 200k
35kHz
–PSRR @ V
DD
/V
SS
= ±5V
DC ±10% p-p AC
+PSRR @ V
DD
/V
SS
= ±5V
DC ±10% p-p AC
Figure 24. −3 dB Bandwidth
FREQUENCY (Hz)
NOMINALIZED GAIN FLATNESS (0.1dB/DIV)
–6dB
100 1k 10k 100k
02929-023
T
A
= 25°C
V
DD
/V
SS
= ±5V
R = 200k
R = 20k
R = 50k
Figure 25. Normalized Gain Flatness vs. Frequency
FREQUENCY (Hz)
I
LOGIC
(
m
A)
500
300
400
200
100
0
10k 100k 1M 10M
02929-024
T
A
= 25°C
V
DD
/V
SS
= ±5V
CODE = 55
H
CODE = 55
H
Figure 26. VLOGIC Supply Current vs. Frequency
Figure 27. PSRR vs. Frequency
02929-026
A2 1.2V 852.0µs
2.04µs
Figure 28. Midscale Glitch Energy Code 0x80 to 0x7F
02929-027
CH1 5.00V CH2 5.00V M100ns A CH1 0V
V
W
CS
2
1
+5V
–5V
T
Figure 29. Large Signal Settling Time
AD5280/AD5282
Rev. C | Page 11 of 28
02929-028
A2 1.0V 33.41µs
1.50µs
CODE (Decimal)
Figure 30. Digital Feedthrough vs. Time
THEORETICAL |
WB_MAX
(mA)
100
0.1
1.0
10
0.01
0 32 64 19296 128 224 256
02929-029
V
A
= V
B
= OPEN
T
A
= 25°C
R
AB
= 20k
R
AB
= 50k
R
AB
= 200k
Figure 31. IWB_MAX vs. Code
LONG TERM CHANNEL-TO-CHANNEL RAB MATCH (%)
FREQUENCY (MHz)
40
10
20
30
0
–0.5
–0.45
–0.4
–0.35
–0.3
–0.25
–0.2
–0.15
–0.1
0.2
0.15
0.1
0.05
0
–0.05
02929-030
CODES SET TO
MIDSCALE
3 LOTS
SAMPLE SIZE = 135
Figure 32. Channel-to-Channel Resistance Matching (AD5282)
AD5280/AD5282
Rev. C | Page 12 of 28
TEST CIRCUITS
Figure 33 to Figure 43 define the test conditions used in the product specification table.
AW
DUT
B
V+ = V
DD
1LSB = V+/2
N
V+
W
DUT
V
MS
02929-031
Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL)
AW
DUT I
W
NO CONNECT
B
V
MS
02929-032
Figure 34. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
AW
B
DUT
V
MS2
V
MS1
02929-033
V
W
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
–V
MS2
]/I
W
Figure 35. Wiper Resistance
AW
V
DD
V
A
B
V+
V
MS
02929-034
V+ = V
DD
±10%
PSRR (dB) = 20 LOG
( )
PSS (%/%) =
V
MS
V
DD
V
MS
%
V
DD
%
Figure 36. Power Supply Sensitivity (PSS, PSSR)
A
5V
V
OUT
OFFSET
GND
OFFSET
BIAS
V
IN
02929-035
B
OP279
Figure 37. Inverting Gain
W
V
OUT
OFFSET
GND
OFFSET
BIAS
V
IN
02929-036
DUT
OP279
5V
BA
Figure 38. Noninverting Gain
VOUT
OFFSET
GND
2.5V
V
IN
DUT
02929-037
A
W
AD8610
+15V
–15V
B
Figure 39. Gain vs. Frequency
W
B
V
SS
TO V
DD
DUT
I
SW
0.1V
R
SW
= 0.1V
I
SW
02929-038
Figure 40. Incremental On Resistance
AD5280/AD5282
Rev. C | Page 13 of 28
W
B
VCM
ICM
A
NC
GND
N/C
RDAC1
W1
B1VSS
VDD A2
RDAC2
W2
B2
VOUT
A1
NC
VSS
VDD
DUT
NC = NO CONNECT
02929-039
Figure 41. Common-Mode Leakage Current
SCL
I
LOGIC
V
LOGIC
SCA
DIGITAL INPUT
VOLTAGE
02929-040
Figure 42. VLOGIC Current vs. Digital Input Voltage
V
IN
CTA = 20 LOG [VOUT/VIN]
02929-041
Figure 43. Analog Crosstalk (AD5282 Only)
AD5280/AD5282
Rev. C | Page 14 of 28
THEORY OF OPERATION
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs). To
program the VR settings, see the Digital Interface section. Both
parts have an internal power-on preset that places the wiper at
midscale during power-on, which simplifies the fault condition
recovery at power-up. Operation of the power-on preset function
also depends on the state of the VL pin.
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
A
X
W
X
R
S
B
X
SHDN
0xFF
0x01 SW
B
SW
A
0x00
502929-04
()
Figure 44. AD5280/AD5282 Equivalent RDAC Circuit
RHEOSTAT OPERATION
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final
two or three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, and
200 kΩ = 200. The nominal resistance (RAB) of the VR has
256 contact points accessed by the wiper terminal, plus the B
terminal contact. The eight-bit data in the RDAC latch is
decoded to select one of the 256 possible settings. Assuming
that a 20 kΩ part is used, the wiper’s first connection starts at
the B terminal for data 0x00. Because there is a 60 Ω wiper
contact resistance, such a connection yields a minimum of 60 Ω
resistance between Terminal W and Terminal B.
The second connection is the first tap point that corresponds to
138 Ω (RWB = RAB/256 + RW = 78 Ω + 60 Ω) for data 0x01. The
third connection is the next tap point representing 216 Ω (78 ×
2 + 60) for data 0x02, and so on. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 19,982 Ω (RAB – 1 LSB + RW). Figure 46 shows a
simplified diagram of the equivalent RDAC circuit where the
last resistor string is not accessed; therefore, there is 1 LSB less
of the nominal resistance at full scale in addition to the wiper
resistance.
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR +×= 256
()
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8-
bit RDAC register.
RAB is the nominal end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
Note that in the zero-scale condition, a finite wiper resistance
of 60 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
As in the mechanical potentiometer, the resistance of the RDAC
between Wiper W and Terminal A also produces a digitally
controlled complementary resistance, RWA . When these terminals
are used, the B terminal can be opened. Setting the resistance
value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is
W
ABWA RR
D
DR +×
−
=256
256 (2)
The typical distribution of the nominal resistance, RAB, from
channel to channel matches within ±1%. Device-to-device
matching is process lot dependent, and it is possible to have a
±30% variation. Because the resistance element is processed in
thin film technology, the change in RAB with temperature is very
small (30 ppm/°C).
POTENTIOMETER OPERATION
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A to be proportional to the input voltage
at A to B. Unlike the polarity of VDD – VSS, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity, provided that VSS is powered by a negative supply.
If the effect of the wiper resistance for approximation is ignored,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across A to B divided by the 256 positions of the
potentiometer divider. Because the AD5280/AD5282 can be
supplied by dual supplies, the general equation defining the
output voltage at VW with respect to ground for any valid
AD5280/AD5282
Rev. C | Page 15 of 28
input voltage applied to Terminal A and Terminal B is
()
B
A
WVVDV 256256 += DD 256 −
() ()
(3)
For a more accurate calculation that includes the effect of wiper
resistance, VW can be found as
()
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV += (4)
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors RWA and RWB and not on the absolute
values; therefore, the temperature drift reduces to 5 ppm/°C.
191 199
SCL
SDA
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
ACK. BY
AD5280/5282
FRAME 2
INSTRUCTION BYTE
ACK. BY
AD5280/AD5282
FRAME 3
DATA BYTE
ACK. BY
AD5280/5282
STOP BY
MASTER
01011
AD1 R/W A/BRSSDO1O2 X X X D7D6D5D4D3D2D1D0AD0
02929-043
Figure 45. Writing to the RDAC Register
191 9
SCL
SDA
ACK. BY
AD5280/AD5282
NO ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
STOP BY
MASTER
0 1 0 1 1AD1AD0R/W D7D6D5D4D3D2D1D0 A
04402929-
Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode
Table 6. Serial Format of Data Accepted from the I2C Bus
S 0 1 0 1 1 AD1 AD
0
R/
W
A A/B RS S
D
O1 O
2 X X X A D7 D6 D
5
D
4
D
3
D
2
D
1
D
0
A
P
Slave Address Byte Instruction Byte Data Byte
where:
Abbreviation Equals
S Start condition
P Stop condition
A Acknowledge
X Don’t care
AD1, AD0 Package pin programmable address bits
R/WRead enable at high and write enable at low
A/B RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2
RS Midscale reset, active high (only affects selected channel)
SD Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel)
O, O
2 1 Output logic pin latched values; default Logic 0
D7, D6, D5, D4, D3, D2, D1, D0 Data bits
AD5280/AD5282
Rev. C | Page 16 of 28
DIGITAL INTERFACE
2-WIRE SERIAL BUS
The AD5280/AD5282 are controlled via an I2C-compatible serial
bus. The RDACs are connected to this bus as slave devices. As
shown in Figure 45, Figure 46, and Table 6, the first byte of the
AD5280/AD5282 is a slave address byte. It has a 7-bit slave
address and an R/W bit.
The 5 MSBs are 01011, and the two bits that follow are deter-
mined by the state of the AD0 pin and the AD1 pin of the
device. AD0 and AD1 allow the user to place up to four of the
I2C-compatible devices on one bus. The 2-wire I2C serial bus
protocol operates as follows.
The master initiates data transfer by establishing a start condi-
tion, which happens when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The following
byte is the slave address byte, which consists of the 7-bit slave
address followed by an R/W bit (this bit determines whether
data is read from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits for
data to be written to or read from its serial register. If the R/W bit
is high, the master reads from the slave device. On the other
hand, if the R/W bit is low, the master writes to the slave device.
A write operation contains one instruction byte more than a
read operation. Such an instruction byte in write mode follows
the slave address byte. The most significant bit (MSB) of the
instruction byte labeled A/B is the RDAC subaddress select. A
low selects RDAC1 and a high selects RDAC2 for the dual
channel AD5282. Set A/B low for the AD5280.
RS, the second MSB, is the midscale reset. A logic high on this
bit moves the wiper of a selected channel to the center tap
where RWA = RWB. This feature effectively writes over the
contents of the register and thus, when taken out of reset mode,
the RDAC remains at midscale.
SD, the third MSB, is a shutdown bit. A logic high causes the
selected channel to open circuit at Terminal A while shorting
the wiper to Terminal B. This operation yields almost 0 Ω in
rheostat mode or 0 V in potentiometer mode. This SD bit serves
the same function as the SHDN pin except that the SHDN pin
reacts to active low. Also, the SHDN pin affects both channels
(AD5282) as opposed to the SD bit, which affects only the
channel that is being written to. Note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to
the RDAC.
The following two bits are O1 and O2. They are extra program-
mable logic outputs that can be used to drive other digital loads,
logic gates, LED drivers, analog switches, and so on. The three
LSBs are don’t care bits (see Figure 45).
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 45).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46).
When all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 45). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master then
brings the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknow-
ledged its slave address and instruction bytes, the RDAC output
updates after these two bytes. If another byte is written to the
RDAC while it is still addressed to a specific slave device with the
same instruction, this byte updates the output of the selected slave
device. If different instructions are needed, the write mode has to
start with a new slave address, instruction, and data byte again.
Similarly, a repeated read function of RDAC is also allowed.
AD5280/AD5282
Rev. C | Page 17 of 28
READBACK RDAC VALUE
The AD5280/AD5282 allow the user to read back the RDAC
values in read mode. However, for the dual-channel AD5282,
the channel of interest is the one that is previously selected in
the write mode. When users need to read the RDAC values of
both channels in the AD5282, they can program the first
subaddress in write mode and then change to read mode to read
the first channel value. After that, they can change back to write
mode with the second subaddress and read the second channel
value in read mode again. It is not necessary for users to issue
the Frame 3 data byte in write mode for subsequent readback
operation. Users should refer to Figure 45 and Figure 46 for the
programming format.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5280/AD5282 feature additional programmable logic
outputs, O1 and O2, which can be used to drive a digital load,
analog switches, and logic gates. O1 and O2 default to Logic 0. The
logic states of O1 and O2 can be programmed in Frame 2 under
write mode (see Figure 45). These logic outputs have adequate
current driving capability to sink/source milliamperes of load.
Users can also activate O1 and O2 in three ways without
affecting the wiper settings by programming as follows:
• Perform start, slave address, acknowledge, and instruction
bytes with O1 and O2 specified, acknowledge, stop.
• Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, stop.
• Not complete the write cycle by not issuing the stop, then
start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, stop.
SELF-CONTAINED SHUTDOWN FUNCTION AND
PROGRAMMABLE PRESET
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte.
As shown in , when shutdown is asserted, the
AD5280/AD5282 open SWA to let the A terminal float and
short the W terminal to the B terminal. The AD5280/AD5282
consume negligible power during shutdown mode, resuming
the previous setting once the
Figure 44
SHDN pin is released.
In addition, shutdown can be implemented with the device
digital output as shown in Figure 47. In this configuration, the
device is shut down during power-up, but the user is allowed to
program the device at any preset levels. When it is done, the
user programs O1 high with the valid coding and the device
exits from shutdown and responds to the new setting. This self-
contained shutdown function allows absolute shutdown during
power-up, which is crucial in hazardous environments, without
adding extra components. Also, the sleep mode programming
feature during shutdown allows the AD5280/AD5282 to have a
programmable preset at any level, a solution that can be as
effective as using other high cost EEPROM devices. Because of
the extra power drawn on RPD, note that a high value should be
chosen for the RPD.
SDA
SHDN
SCL
RPD
O1
02929-046
Figure 47. Shutdown by Internal Logic Output
MULTIPLE DEVICES ON ONE BUS
Figure 48 shows four AD5282 devices on the same serial bus.
Each has a different slave address because the states of their Pin
AD0 and Pin AD1 are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain pull-
downs in a fully I2C-compatible interface.
SDA
SCL
R
P
R
P
5V 5V 5V
MASTER
5V
SDA
AD1
AD0
AD5282
SCL SDA
AD1
AD0
AD5282
SCL SDA
AD1
AD0
AD5282
SCL SDA
AD1
AD0
AD5282
SCL
02929-047
Figure 48. Multiple AD5282 Devices on One Bus
AD5280/AD5282
Rev. C | Page 18 of 28
LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE
V
While most old systems can be operated at one voltage, a new
component can be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, a 3.3 V EEPROM can interface
with a 5 V digital potentiometer. A level-shift scheme is needed
to enable a bidirectional communication so that the setting of
the digital potentiometer can be stored to and retrieved from
the EEPROM. Figure 49 shows one of the implementations.
M1 and M2 can be any N-channel signal FETs or low threshold
FDV301N if VDD falls below 2.5 V.
DD
R
P
R
P
R
P
R
P
G
M1
M2
5V
AD5282
SCL2
SDA2
SCL1
SDA1
3.3V
EEPROM
V
DD1
= 3.3V V
DD2
= 5V
SD
G
SD
02929-04
LEVEL SHIFTED
8
Figure 49. Level Shift for Different Potential Operation
LEVEL SHIFT FOR NEGATIVE VOLTAGE
OPERATION
The digital potentiometer is popular in laser diode driver
applications and certain telecommunications equipment level-
setting applications. These applications are sometimes
operated between ground and a negative supply voltage such
that the systems can be biased at ground to avoid large bypass
capacitors that may significantly impede the ac performance.
Like most digital potentiometers, the AD5280/AD5282 can be
configured with a negative supply (see Figure 50).
–5V
LEVEL SHIFTED
VDD
VSS
GND
SDA
SCL
02929-049
Figure 50. Biased at Negative Voltage
However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. Figure 51 shows one implementation with a
few transistors and a few resistors. When VIN is below the Q3
threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state,
VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on,
and Q2 is turned off. In this state, VOUT is pulled down to VSS.
Be aware that proper time shifting is also needed for successful
communication with the device.
+5V
0
Q3
R2
10k
R3
10k
V
SS
= –5V
V
OUT
–5V
0
Q1
Q2
V
IN
0
0
02929-050
Figure 51. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures, as shown in Figure 52. The
protection applies to digital inputs SDA, SCL, and SHDN.
LOGIC
340
V
SS
02929-051
Figure 52. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on
Re s istor Te r minal A , Res istor Te r minal B, and Wip e r Termin a l
W that exceed VDD or VSS are clamped by the internal forward-
biased diodes (see Figure 53).
V
DD
A
W
B
V
SS
02929-053
Figure 53. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
Figure 53), it is important to power VDD/VSS before applying any
voltage to the A, B, and W terminals. Otherwise, the diode is
forward biased such that VDD/VSS is unintentionally powered,
which may affect the rest of the user’s circuit. The ideal power-
up sequence is the following: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA/VB/VW and digital inputs
is not important as long as they are powered after VDD/VSS.
AD5280/AD5282
Rev. C | Page 19 of 28
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to design a layout with compact, minimum
lead lengths. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
AD5280/
AD5282
V
DD
V
SS
V
DD
V
SS
GND
C3
10µF
C1
0.1µF
C4
10µF
C2
0.1µF
+
+
02929-054
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple (see Figure 54). Notice that the digital ground should also
be joined remotely to the analog ground at one point to
minimize digital ground bounce.
Figure 54. Power Supply Bypassing
AD5280/AD5282
Rev. C | Page 20 of 28
APPLICATIONS INFORMATION
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option unless C2 is scaled as if R2 were at its maximum
value. Doing so may overcompensate and compromise the
performance slightly when R2 is set at low values. However, it
avoids the gain peaking, ringing, or oscillation at the worst case.
For critical applications, C2 should be found empirically to suit
the need. In general, C2 in the range of a few picofarads (pF) to
no more than a few tenths of a picofarad is usually adequate for
the compensation.
BIPOLAR DC OR AC OPERATION FROM DUAL
SUPPLIES
The AD5280/AD5282 can be operated from dual supplies
enabling control of ground-referenced ac signals or bipolar
operation. The ac signal, as high as VDD/VSS, can be applied
directly across Terminal A to Terminal B with the output taken
from Terminal W. See Figure 55 for a typical circuit connection.
AD5282
V
DD
V
SS
SCLK SCL
SDA ±2.5V p-p ±5V p-p
D–80
H
+5.0V
–5.0V
A
1
B
1
W
1
GND
MOSI
GND
MICROCONTROLLER
A
2
W
2
B
2
Similarly, there are W and A terminal capacitances connected to
the output (not shown); fortunately, their effect at this node is less
significant and the compensation can be avoided in most cases.
15 V, 8-BIT I2C DAC
02929-055
Figure 55. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION
The digital potentiometer is commonly used in gain control
applications such as the noninverting gain amplifier shown in
Figure 56.
BA
W
C2
4.7pF
V
O
R
1
C
1
25pF
V
I
47k
200k
02929-056
U1
Figure 56. Typical Noninverting Gain Amplifier
Notice that the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node. It introduces a 0
for the 1/βO term with 20 dB/decade (dec), whereas a typical op
amp GBP has −20 dB/dec characteristics. A large R2 and finite
C1 can cause the 0 frequency to fall well below the crossover
frequency. Thus the rate of closure becomes 40 dB/dec, and the
system has a 0° phase margin at the crossover frequency. The
output may ring or oscillate if the input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values because this is equivalent to a step
change at the input.
02929-057
AD5280
U2
AD8512
V+
V–
AD8512
V
DD
R
BIAS
V
O
V
DD
U1B
ADR512
D1
R2
R1
B
200k
U1A
Figure 57. 8-Bit I2C DAC
AD5280/AD5282 can be configured as a high voltage DAC, as
high as 15 V. The output is
)]1(V2.1[
256
)(
1
2
OR
RD
DV +×= (5)
AD5280/AD5282
Rev. C | Page 21 of 28
8-BIT BIPOLAR DAC
02929-058
V
IN
V
OUT
U
1
A
1
+5V
REF
U
2
V
O
A
2
U
2
–
W
–15V
–5V
REF
–15V
+
–
OP2177
+
–
OP2177
B
RR
A
V
1
TRIM
ADR425
GND
AD5280
+15V
+15V
Figure 58. 8-Bit Bipolar DAC
Figure 58 shows a low cost, 8-bit, bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at
low value codes, are skewed by the effects of the digital potenti-
ometer wiper resistance. The output of this circuit is
REF
OVV ×
⎟
⎠
⎜
⎝−= 1
256
D⎞⎛ 2 (6)
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
02929-059
U
2
U
1
A
2
V
1
A
1
B
1
W
2
A
2
A
2
W
1
V
DD
A
1
V
DD
V
S8
B
2
V
V
S8
O
R2
R1
C1
–kVI
V+
V–
+
–
OP2177
V+
V–
+
–
OP2177
AD5282
AD5282
Figure 59. Bipolar Programmable Gain Amplifier
For applications that require bipolar gain, Figure 59 shows one
implementation similar to the previous circuit. The digital
potentiometer, U1, sets the adjustment range. The wiper voltage
at W2 can therefore be programmed between Vi and –KVi at a
given U2 setting. Configuring A2 in noninverting mode allows
linear gain and attenuation. The transfer function is
()
⎟
⎠
⎜
⎝−+××
⎟
⎠
⎜
⎝+= KK
R1Vi
O1
256
1⎞⎛⎞⎛ D2R2
V (7)
where K is the ratio of RWB1/RWA 1 set by U1.
As in the previous example, in the simpler and more common
case where K = 1, a single digital AD5280 potentiometer is
used. U1 is replaced by a matched pair of resistors to apply
Vi and −Vi at the ends of the digital potentiometer. The
relationship becomes
iO V
D2
R1
R2
V×
⎟
⎠
⎞
⎜
⎝
⎛−
⎟
⎠
⎞
⎜
⎝
⎛+= 1
256
2
1 (7)
If R2 is large, a compensation capacitor having a few pF may be
needed to avoid any gain peaking.
Table 7 shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and a 256-step
resolution.
Table 7. Result of Bipolar Gain Amplifier
D R1 = ∞, R2 = 0 R1 = R2 R2 = 9R1
0 −1 −2 −10
64 −0.5 −1 −5
128 0 0 0
192 0.5 1 5
255 0.968 1.937 9.680
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustments, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 60).
02929-060
C
C
V
I
5V
U
1
= AD5280
A
1
= AD8501, AD8605, AD8541
N
1
= FDV301N, 2N7002
U
1
R
BIAS
I
L
N1
V
O
V+
V–
+
–
A1
A
B
WSIGNAL
LD
Figure 60. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the
VBIAS to be equal to the wiper voltage set by the digital potenti-
ometer. The load current is then delivered by the supply via the
N-channel FET N1. The N1 power handling must be adequate
to dissipate (Vi – VO) × IL power. This circuit can source a
maximum of 100 mA with a 5 V supply. A1 needs to be a rail-
to-rail input type. For precision applications, a voltage reference
such as ADR423, ADR292, or AD1584 can be applied at the
input of the digital potentiometer.
AD5280/AD5282
Rev. C | Page 22 of 28
PROGRAMMABLE CURRENT SOURCE
+5V
+5V
R
S
102
V+
REF191
GND
AD5280
2
36
B
A
W
C1
1µF
4
U
1
0 TO (2.048 + V
L
)
V
OUT
V
IN
5V
R
L
100
V–
OP8510
U2 V
L
–2.048V TO V
L
I
L
SLEEP
OP8510
U2
02929-061
Figure 61. Programmable Current Source
A programmable current source can be implemented with the
circuit shown in Figure 61. REF191 is a unique, low supply
headroom and high current handling precision reference that
can deliver 20 mA at 2.048 V. The load current is simply the
voltage across Terminal B to Terminal W of the digital
potentiometer divided by RS.
N
S
REF
LR
DV
I2×
×
= (8)
The circuit is simple, but attention must be paid to two things.
First, dual-supply op amps are ideal because the ground
potential of REF191 can swing from −2.048 V at zero scale to VL
at full scale of the potentiometer setting. Although the circuit
works under single supply, the programmable resolution of the
system is reduced.
For applications that demand higher current capabilities, a
few changes to the circuit in Figure 61 produce an adjustable
current in the range of hundreds of milliamps. First, the voltage
reference needs to be replaced with a high current, low dropout
regulator, such as the ADP3333, and the op amp needs to be
swapped with a high current dual-supply model, such as the
AD8532. Depending on the desired range of current, an
appropriate value for RS must be calculated. Because of the high
current flowing to the load, the user must pay attention to the
load impedance so as not to drive the op amp beyond the
positive rail.
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
AD5280
+5V
R1
150k
R2
A
14.95k
|
L
R2
B
50k
R2
I
15k
C1
10pF
R1
I
150k
V
L
R
L
500k
A
2
+15V
+15V
A
WV+
OP2177
OP2177
V–
V+
V–
A
1
–5V
–15V
–15V
02929-062
Figure 62. Programmable Bidirectional Current Source
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 62). If the resistors are matched, the load
current is
( )
W
B
BA
V
R1R2R2
LR2
I×
+
= (9)
In theory, R2B can be made as small as needed to achieve the
current needed within the A2 output current driving capability.
In this circuit, the OP2177 can deliver ±5 mA in either direction,
and the voltage compliance approaches 15 V. It can be shown
that the output impedance is
( )
()
B
A
A
B
OR2R2R1'R2'R1
R2R1R2'R1
Z+−×
×+
= (10)
This output impedance can be infinite if Resistor R1' and
Resistor R2' match precisely with R1 and R2A + R2B,
respectively. On the other hand, it can be negative if the
resistors are not matched. As a result, C1 must be in the range
of 1 pF to 10 pF to prevent the oscillation.
AD5280/AD5282
Rev. C | Page 23 of 28
PROGRAMMABLE LOW-PASS FILTER
At resonance, setting the following balances the bridge:
In analog-to-digital conversion applications, it is common to
include an antialiasing filter to band-limit the sampling signal.
Dual-channel digital potentiometers can be used to construct
a second-order Sallen key low-pass filter (see Figure 63). The
design equations are
2
2
OO
Vω
=
2
O
O
iS
Q
S
Vω+
ω
+ (11)
R1R2C1C2
O
1
=ω (12)
R2C2R1C1
Q11 += (13)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can be
adjusted to the same settings to achieve the desirable bandwidth.
V
I
U
1
V
O
R1
A
R
W
B
R2
A
R
W
B
C2 C
C1
C
+2.5V
V+
V–
–2.5V
AD8601
ADJUSTED TO
SAME SETTING
02929-063
Figure 63. Sallen Key Low-Pass Filter
PROGRAMMABLE OSCILLATOR
In a classic Wien-bridge oscillator (Figure 64), the Wien
network (R, R', C, C') provides positive feedback, while R1
and R2 provide negative feedback. At the resonant frequency, fO,
the overall phase shift is 0, and the positive feedback causes the
circuit to oscillate. With R = R', C = C', and R2 = R2A//(R2B +
Rdiode), the oscillation frequency is
RC
for
RC oO
π
ω
11 == 2
(14)
where R is equal to RWA such that
AB
R
D
R256
256
=− (15)
2=
R1
R2 (16)
In practice, R2/R1 should be set slightly larger than 2 to ensure
that oscillation can start. On the other hand, the alternate turn-
on of Diode D1 and Diode D2 ensures that R2/R1 are smaller
than 2 momentarily and, therefore, stabilizes the oscillation.
Once the frequency is set, the oscillation amplitude can be
tuned by R2B because
DBDO VR2IV +=
3
2 (17)
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VO
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be
too large to prevent saturation of the output.
FREQUENCY
ADJUSTMENT
C
2.2nF
C
I
2.2nF
R
I
10k
R
10k
BA
A
W
V+
V–
B
B
W
W
D1
D2
V
O
U
1
VP
A
VN
–2.5V
+2.5V
R1
1k
R2
B
10k
R2
A
2.1k
R1 = R1
I
= R2B = AD5282
D1 = D2 = 1N4148
AMPLITUDE
ADJUSTMENT
02929-064
OP1177
Figure 64. Programmable Oscillator with Amplitude Control
AD5280/AD5282
Rev. C | Page 24 of 28
02929-068
C
W
85pF
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5280
(20 kΩ resistor) measures 310 kHz at half scale. Figure 24
provides the Bode plot characteristics of the three available
resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic
simulation model is shown in Figure 65. A macro model net list
for the 20 kΩ RDAC is provided.
C
A
25pF
C
A
25pF
RDAC
20k
A B
Figure 65. RDAC Circuit Simulation Model for RDAC = 20 kΩ
MACRO MODEL NET LIST FOR RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/256)*RDAC+60}
CW W 0 55E-12
RWB W B {D/256*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
AD5280/AD5282
Rev. C | Page 25 of 28
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
OUTLINE DIMENSIONS
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
SEATING
PLANE
COPLANARITY
0.10
Figure 66. 14-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-14)
Dimensions shown in millimeters
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.15
0.05
0.65
BSC
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 67. 16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
AD5280/AD5282
Rev. C | Page 26 of 28
ORDERING GUIDE
Model1
No. of
Channels RAB (kΩ)
Temperature
Range Package Description
Package
Option Ordering Quantity
AD5280BRU20 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD5280BRU20-REEL7 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5280BRU50 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD5280BRU50-REEL7 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5280BRU200-REEL7 1 200 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5280BRUZ2021 20 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD5280BRUZ20-REEL72
1 20 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5280BRUZ502
1 50 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD5280BRUZ50-REEL72
1 50 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5280BRUZ2002
1 200 −40°C to +85°C 14-Lead TSSOP RU-14 96
AD5280BRUZ200-R72
1 200 −40°C to +85°C 14-Lead TSSOP RU-14 1,000
AD5282BRU20 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRU20-REEL7 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282BRU50 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRU50-REEL7 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282BRU200 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRU200-REEL7 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282BRUZ202
2 20 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRUZ20-REEL72 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282BRUZ502
2 50 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRUZ50-REEL72 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282BRUZ2002
2 200 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5282BRUZ200-R72 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 1,000
AD5282-EVAL 2 20 Evaluation Board
1 Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and Line 3 contains date code YYWW.
2 Z = RoHS Compliant Part.
AD5280/AD5282
Rev. C | Page 27 of 28
NOTES
AD5280/AD5282
Rev. C | Page 28 of 28
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02929-0-7/09(C)
