TESDD5V0HC
Bi-directional ESD Protection Diode
Small Signal Diode
Meet IEC61000-4-4 (EFT) rating. 40A (5/50ήs)
Protects one birectional I/O line
Working Voltage : 5V
Case : SOD-523F flat lead small outline plastic package Min Max Min Max
0.70 0.90 0.028 0.035
1.50 1.70 0.059 0.067
0.25 0.35 0.010 0.014
1.10 1.30 0.043 0.051
0.60 0.70 0.024 0.028
0.10 0.14 0.004 0.006
Pin Configutation
Microprocessor based equipment
Personal Digital Assistants (PDA’s)
Portable Instrumentation Suggested PAD Layout
Peripherals
Part No. Package Packing Marking
TESDD5V0HC SOD-523F 3K / 7" Reel TB
Maximum Ratings and Electrical Characteristics
Maximum Ratings
Electrical Characteristics
1mA
5V
1A
5A
6
100
±15
±8
Mechanical Data
-15
10
1
pF
W
°C
V
V
KV
Units
V
uA
Applications
Cell Phone Handsets and Accessories
Weight :2 mg (approximately)
-
Symbol
Value
.-55 to + 150.
Min
Symbol
VESD
PPP
-
Max
Terminal: Matte tin plated, lead free., solderable
per MIL-STD-202, Method 208 guaranteed
Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
Marking Code : TB
Mounting position: Any
Pb free version, RoHS compliant, and Halogen free
Junction and Storage Temperature Range
Type Number Units
Packing Code
RKG
Rating at 25°C ambient temperature unless otherwise specified.
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
SOD-523F
5VRWM
TJ, TSTG
Type Number
Reverse Stand-Off Voltage
IPP=
VR=0V, f=1.0MHz
Reverse Leakage Current
Features
Clamping Voltage
-
CJ
IR
V(BR)IR=Reverse Breakdown Voltag
Peak Pulse Power (tp=8/20μs waveform)
High temperature soldering guaranteed: 260°C/10s C
D
E
Unit (inch)
Dimensions Unit (mm)
A
B
may vary despending on application.
F
Ordering Information
35 (Typ.)
Notes: 1. The suggested land pattern dimensions have been provided for reference only, as actual pad layouts
-
Vc
Junction Capacitance
IPP=
VR=
0.40
0.40
1.80
1.00
Unit : mm
Version : A11
TESDD5V0HC
Bi-directional ESD Protection Diode
Small Signal Diode
Rating and Characteristic Curves
0.01
0.1
1
10
0.1 1 10 100 1000
Peak Pulse Power Ppp (KW)
Pulse Duration (us)
FIG 2 Pulse Waveform
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Percent of IPP
Time (us)
Ambient Tempeatature (oC) Reverse Voltage (V)
0
5
10
15
20
25
012345
Clamping Voltage (V)
FIG 5 Clamping Voltage vs. Peak Pulse Current)
Peak Pulse Current (A)
Waveform Parameters:
tr = 8μs, td = 20μs
FIG 1 Non-Repetitive Peak Pulse Power vs. Pulse Time
Waveform Parameters:
tr = 8μs, td = 20μs
FIG 4 Typical Junction Capacitance
0
5
10
15
20
25
30
35
40
012345
Normalized Capacitance
FIG 3 Admissible Power Dissipation Curve
0
20
40
60
80
100
120
0 20 40 60 80 100 120 140 160 180
Power Rating (%)
f = 1.0MHz
1000
td=Ipp/2
e-1
Version : A11
TESDD5V0HC
Bi-directional ESD Protection Diode
Small Signal Diode
Applications Information
Designed to protect sensitive electronics from damage or latch-up due to ESD
Designed to replace multilayer varistors (MLVs) in portable applications
Offers superior electrical characteristics such as lower clamping voltage and no device degradation when compared to MLVs
Circuit Board Layout Recommendations
Tape & Reel specification
Note 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be
within 0.05 mm min. to 0.5 mm max. The component cannot rote more than 10o within the determined cavity.
Note 2: If B1 exceeds 4.2 mm(0.165'') for 8 mm embossed tape, the tape may not feed through all tape feeders.
Overall tape thickness T 0.6 Max.
Tape width W 8.30 Max.
Reel width W1 14.4 Max.
Sprocke hole pitch P0 4.00 ±0.10
Embossment center P1 2.00 ±0.10
Sprocke hole position E 1.75 ±0.10
Punch hole position F 3.50 ±0.05
Reel inner diameter D1 50 Min.
Feed hole width D2 13.0 ± 0.5
Sprocket hole D 1.50 +0.10
Reel outside diameter A 178 ± 1
Item Symbol Dimension
(mm)
Minimize the path length between the ESD Protection Diode and the protected line.
Minimize all conductive loops including power and ground loops.
Designed to protect one data, I/O, or power supply line.
The combination of small size and high ESD surge capability makes them ideal for use in portable applications.
Good circuit board layout is critical for the suppression of ESD induced transients.
Place the ESD Protection Diode near the input terminals or connectors to restrict transient coupling.
Carrier depth K 2.40 Max.
The ESD transient return path to ground should be kept as short as possible.
Top Cover Tape
Carieer Tape
Any Additional Label (If Required)
TSC label
Direction of Feed
W1
D1D2
A
Version : A11
For Machine Reference
Only
Including Draft and RADLL
Concentric Around B0
T
Top
Cover Tape
See Note1
B0
K Center Lines
of Cavity
F
E
W
For Components
2.0mm X 1.2mm
and Larger
D'
DP1
10 Pitches Cumulative
Tolerance on Tape
±2.0mm ( ±0.008")
B0
Embossment
A0
K0
B1
P0
