Document Number: MMA1211D
Rev 4, 03/2006
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Surface Mount
Micromachined Accelerometer
The MMA series of silicon capacitive, micromachined accelerometers feature
signal conditioning, a 4-pole low pass filter and temperature compensation.
Zero-g offset full scale span and filter cut-off are factory set and require no
external devices. A full system self-test capability verifies system functionality.
Features
• Integral Signal Conditioning
• Linear Output
• Ratiometric Performance
•4
th Order Bessel Filter Preserves Pulse Shape Integrity
• Calibrated Self-test
• Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status
• Transducer Hermetically Sealed at Wafer Level for Superior Reliability
• Robust Design, High Shocks Survivability
Typical Applications
• Vibration Monitoring and Recording
• Impact Monitoring
ORDERING INFORMATION
Device Name Temperature Range Case No. Package
MMA1211D –40° to 125°C475-01 SOIC-16
MMA1211DR2 –40° to 125°C475-01 SOIC16, Tape & Reel
MMA1211EG –40° to 125°C475-01 SOIC-16
MMA1211EGR2 –40° to 125°C475-01 SOIC16, Tape & Reel
MMA1211
MMA1211D: Z AXIS SENSITIVITY
MICROMACHINED
ACCELEROMETER
±150g
D SUFFIX
EG SUFFIX (Pb-FREE)
16-LEAD SOIC
CASE 475-01
G-Cell
Sensor Integrator Gain Filter Temp
Comp
Self-test Control Logic &
EPROM Trim Circuits Clock
Generator
Oscillator
VDD
VOUT
VSS
ST
STATUS
Figure 1. Simplified Accelerometer Functional Block Diagram
N/C
N/C
N/C
ST
VOUT
STATUS
VSS
VDD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 2. Pin Connections
MMA1211D
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2Freescale Semiconductor
ELECTRO STATIC DISCHARGE (ESD)
WARNING: This device is sensitive to electrostatic
discharge.
Although the Freescale accelerometers contain internal
2kV ESD protection circuitry, extra precaution must be taken
by the user to protect the chip from ESD. A charge of over
2000 volts can accumulate on the human body or associated
test equipment. A charge of this magnitude can alter the
performance or cause failure of the chip. When handling the
accelerometer, proper ESD precautions should be followed
to avoid exposing the device to discharges which may be
detrimental to its performance.
Table 1. Maximum Ratings
(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)
Rating Symbol Value Unit
Powered Acceleration (all axes) Gpd 1500 g
Unpowered Acceleration (all axes) Gupd 2000 g
Supply Voltage VDD –0.3 to +7.0 V
Drop Test (1)
1. Dropped onto concrete surface from any axis.
Ddrop 1.2 m
Storage Temperature Range Tstg –40 to +125 °C
MMA1211D
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Freescale Semiconductor 3
Table 2. Operating Characteristics
(Unless otherwise noted: –40°C ≤ TA ≤ +105°C, 4.75 ≤ VDD ≤ 5.25, Acceleration = 0g, Loaded output.(1))
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 µF capacitor to ground.
Characteristic Symbol Min Typ Max Unit
Operating Range (2)
Supply Voltage(3)
Supply Current
Operating Temperature Range
Acceleration Range
2. These limits define the range of operation for which the part will meet specification.
3. Within the supply range of 4.75 and 5.25 V, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the
device may operate as a linear device but is not guaranteed to be in calibration.
VDD
IDD
TA
gFS
4.75
3.0
–40
—
5.00
—
—
169
5.25
6.0
+125
—
V
mA
°C
g
Output Signal
Zero g (TA = 25°C, VDD = 5.0 V)(4)
Zero g
Sensitivity (TA = 25°C, VDD = 5.0 V)(5)
Sensitivity
Bandwidth Response
Nonlinearity
4. The device can measure both + and – acceleration. With no input acceleration the output is at mid supply. For positive acceleration the
output will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.
5. The device is calibrated at 35g.
VOFF
VOFF,V
S
SV
f–3dB
NLOUT
2.35
0.46 VDD
12.66
2.480
360
–2.0
2.5
0.50 VDD
13.33
2.667
400
—
2.65
0.54 VDD
14.00
2.853
440
2.0
V
V
mV/g
mV/g/V
Hz
% FSO
Noise
RMS (0.1-1 kHz)
Power Spectral Density
Clock Noise (without RC load on output)(6)
6. At clock frequency ≅70 kHz.
nRMS
nPSD
nCLK
—
—
—
—
110
2.0
2.8
—
—
mVrms
µV/(Hz1/2)
mVpk
Self-Test
Output Response
Input Low
Input High
Input Loading(7)
Response Time(8)
7. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages.
8. Time for the output to reach 90% of its final value after a self-test is initiated.
gST
VIL
VIH
IIN
tST
55
VSS
0.7 × VDD
-30
—
75
—
—
–100
2.0
95
0.3 × VDD
VDD
–260
10
g
V
V
µA
ms
Status(9), (10)
Output Low (Iload = 100 µA)
Output High (Iload = 100 µA)
9. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is
high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application.
10. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The
Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 µs, unless a fault condition continues to exist.
VOL
VOH
—
VDD –0.8
—
—
0.4
—
V
V
Minimum Supply Voltage (LVD Trip) VLVD 2.7 3.25 4.0 V
Clock Monitor Fail Detection Frequency fmin 50 —260 kHz
Output Stage Performance
Electrical Saturation Recovery Time(11)
Full Scale Output Range (IOUT = 200 µA)
Capacitive Load Drive(12)
Output Impedance
11. Time for amplifiers to recover after an acceleration signal causes them to saturate.
12. Preserves phase margin (60°) to guarantee output amplifier stability.
tDELAY
VFSO
CL
ZO
—
0.25
—
—
0.2
—
—
300
—
VDD–0.25
100
—
ms
V
pF
W
Mechanical Characteristics
Transverse Sensitivity(13)
Package Resonance
13. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity.
VXZ,YZ
fPKG
—
—
—
10
5.0
—
% FSO
kHz
MMA1211D
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4Freescale Semiconductor
PRINCIPLE OF OPERATION
The Freescale accelerometer is a surface-micromachined
integrated-circuit accelerometer.
The device consists of a surface micromachined
capacitive sensing cell (g-cell) and a CMOS signal
conditioning ASIC contained in a single integrated circuit
package. The sensing element is sealed hermetically at the
wafer level using a bulk micromachined “cap'' wafer.
The g-cell is a mechanical structure formed from
semiconductor materials (poly silicon) using semiconductor
processes (masking and etching). It can be modeled as two
stationary plates with a moveable plate in-between. The
center plate can be deflected from its rest position by
subjecting the system to an acceleration (Figure 3).
When the center plate deflects, the distance from it to one
fixed plate will increase by the same amount that the distance
to the other plate decreases. The change in distance is a
measure of acceleration.
The g-cell plates form two back-to-back capacitors
(Figure 4). As the center plate moves with acceleration, the
distance between the plates changes and each capacitor's
value will change, (C = Aε/D). Where A is the area of the
plate, ε is the dielectric constant, and D is the distance
between the plates.
The CMOS ASIC uses switched capacitor techniques to
measure the g-cell capacitors and extract the acceleration
data from the difference between the two capacitors. The
ASIC also signal conditions and filters (switched capacitor)
the signal, providing a high level output voltage that is
ratiometric and proportional to acceleration.
SPECIAL FEATURES
Filtering
The Freescale accelerometers contain an on board 4-pole
switched capacitor filter. A Bessel implementation is used
because it provides a maximally flat delay response (linear
phase) thus preserving pulse shape integrity. Because the
filter is realized using switched capacitor techniques, there is
no requirement for external passive components (resistors
and capacitors) to set the cut-off frequency.
Self-Test
The sensor provides a self-test feature that allows the
verification of the mechanical and electrical integrity of the
accelerometer at any time before or after installation. This
feature is critical in applications such as automotive air bag
systems where system integrity must be ensured over the life
of the vehicle. A fourth “plate'' is used in the g-cell as a self-
test plate. When the user applies a logic high input to the self-
test pin, a calibrated potential is applied across the self-test
plate and the moveable plate. The resulting electrostatic
force (Fe = 1/2AV2/d2) causes the center plate to deflect. The
resultant deflection is measured by the accelerometer's
control ASIC and a proportional output voltage results. This
procedure assures that both the mechanical (g-cell) and
electronic sections of the accelerometer are functioning.
Ratiometricity
Ratiometricity simply means that the output offset voltage
and sensitivity will scale linearly with applied supply voltage.
That is, as you increase supply voltage the sensitivity and
offset increase linearly; as supply voltage decreases, offset
and sensitivity decrease linearly. This is a key feature when
interfacing to a microcontroller or an A/D converter because
it provides system level cancellation of supply induced errors
in the analog to digital conversion process.
Status
Freescale accelerometers include fault detection circuitry
and a fault latch. The Status pin is an output from the fault
latch, OR'd with self-test, and is set high whenever one (or
more) of the following events occur:
• Supply voltage falls below the Low Voltage Detect (LVD)
voltage threshold
• Clock oscillator falls below the clock monitor
minimum frequency
• Parity of the EPROM bits becomes odd in number.
The fault latch can be reset by a rising edge on the self-test
input pin, unless one (or more) of the fault conditions
continues to exist.
Acceleration
Figure 3. Transducer
Physical Model
Figure 4. Equivalent
Circuit Model
MMA1211D
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Freescale Semiconductor 5
BASIC CONNECTIONS
Pinout Description
Figure 5. SOIC Accelerometer with Recommended
Connection Diagram
PCB Layout
Figure 6. Recommended PCB Layout for Interfacing
Accelerometer to Microcontroller
NOTES:
1. Use a 0.1 µF capacitor on VDD to decouple the power
source.
2. Physical coupling distance of the accelerometer to the
microcontroller should be minimal.
3. Place a ground plane beneath the accelerometer to
reduce noise, the ground plane should be attached to
all of the open ended terminals shown in Figure 6.
4. Use an RC filter of 1 kΩ and 0.01 µF on the output of
the accelerometer to minimize clock noise (from the
switched capacitor filter circuit).
5. PCB layout of power and ground should not couple
power supply noise.
6. Accelerometer and microcontroller should not be a
high current path.
7. A/D sampling rate and any external power supply
switching frequency should be selected such that they
do not interfere with the internal accelerometer
sampling frequency. This will prevent aliasing errors.
Table 3. Pin Descriptions
Pin No. Pin Name Description
1 thru 3 —Leave unconnected
4ST Logic input pin used to initiate self-test
5 VOUT Output voltage of the accelerometer
6STATUS Logic output pin to indicate fault
7 VSS The power supply ground
8 VDD The power supply input
9 thru 13 Trim pins Used for factory trim. Leave
unconnected
14 thru 16 —No internal connection. Leave
unconnected
N/C
N/C
N/C
ST
VOUT
STATUS
VSS
VDD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MMA1211D
ST
VOUT Output
Signal
R1
1 kΩ
5
C2
0.01 µF
4
7
Logic
Input
VDD
C1
0.1 µF
6STATUS
8VDD
VSS
P0
A/D In
VRH
VSS
VDD
ST
VOUT
VSS
VDD
0.01 µF1 kΩ
0.1 µF
0.1 µF
Power Supply
0.1 µF
P1
STATUS
Microcontroller
Accelerometer
C
C
C
C
R
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6Freescale Semiconductor
Acceleration of the package in the
+Z direction (center plate moves in
the −Z direction) will result in an
increase in the output.
+Z
−Z
Side View
Activation of Self test moves the
center plate in the −Z direction,
resulting in an increase in the output.
1. When positioned as shown, the Earth's gravity will result in a positive 1g output.
Direction of Earth's gravity field(1)
Side View
Dynamic Acceleration Sensing Direction
Static Acceleration Sensing Direction
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Freescale Semiconductor 7
MMA1211D
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the surface mount packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct
footprint, the packages will self-align when subjected to a
solder reflow process. It is always recommended to design
boards with a solder mask layer to avoid bridging and
shorting between solder pads.
Figure 7. Footprint SOIC-16 (Case 475-01)
0.380 in.
9.65 mm
0.050 in.
1.27 mm
0.024 in.
0.610 mm
0.080 in.
2.03 mm
MMA1211D
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8Freescale Semiconductor
PACKAGE DIMENSIONS
CASE 475-01
ISSUE C
16-LEAD SOIC
PAGE 1 OF 2
MMA1211D
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Freescale Semiconductor 9
PACKAGE DIMENSIONS
CASE 475-01
ISSUE C
16-LEAD SOIC
PAGE 2 OF 2
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MMA1211D
Rev. 4
03/2006
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