HDLG-3416 - Agilent / Hewlett-Packard

Four Character 6.9 mm

(0.27 inch) Smart 5 x 7

Alphanumeric Displays

Technical Data

HDLX-3416 Series

Features

• Smart Alphanumeric Display

Built-in RAM, ASCII Decoder,

and LED Drive Circuitry

• Software Controlled

Dimming and Blanking

• 128 ASCII Character Set

• End-Stackable

• Categorized for Luminous

Intensity

Yellow and Green Categories

for Color

Use of Like Categories Yields a

Uniform Display

• Wide Operating

Temperature Range

-40°C to +85°C

• Wave Solderable

• Wide Viewing Angle

(50° Typical)

Description

These are 5 x 7 dot matrix

displays with four 0.27" tall

characters, driven by an on-board

CMOS IC. The IC stores and

decodes 7 bit ASCII data and

displays it with an easy to read

5 x 7 font. Multiplexing circuitry

and drivers are included in the IC

to allow the display to interface

simply with bus-based micro-

processor systems.

The address and data inputs of

the display can be directly con-

nected to the microprocessor

address and data buses.

These displays are related to

the HDLX-2416 family, and thus

share the same enhancements

over the HPDL-2416 segmented

displays. These features include

support for the full 128 character

ESD Warning: Standard CMOS handling precautions should be observed with the HDLX-3416.

US ASCII character set, 8 level

dimming control, external

hardware dimming capability,

and digit blanking.

An extended function disable

exists for those designers who

desire compatibility with

competitive displays. This

function disables the dimming

and digit blanking controls.

Devices:

High Efficiency Red Orange Yellow Green

HDLO-3416 HDLA-3416 HDLY-3416 HDLG-3416

Absolute Maximum Ratings

Supply Voltage, VDD to Ground[1] ...................................... -0.5 V to 7.0 V

Input Voltage, Any Pin to Ground .......................... -0.5 V to VDD + 0.5 V

Free Air Operating Temperature Range, TA..................... -40°C to +85°C

Storage Temperature, TS................................................. -40°C to +85°C

CMOS IC Junction Temperature, TJ (IC) .................................... +150°C

Relative Humidity (non-condensing) at 65°C.................................... 85%

Maximum Solder Temperature, 1.59 mm

(0.063 in.) below Seating Plane, t < 5 sec. ................................... 260°C

ESD Protection, R = 1.5 kΩ, C = 100 pF .............. VZ = 1 kV (each pin)

Note:

1. Maximum Voltage is with no LEDs illuminated.

Package Dimensions

32.77

(1.290)

8.26

(0.325)

10.03

(0.395)

20.07

(0.790)

6.86

(0.270)

4.45

(0.175)

0.51

(0.020)TYP.

8.64

(0.340)

2.54

(0.100)TYP.

4.06

(0.160)

10.16

(0.400)

2.41

(0.095)TYP.

0.38

(0.015)

15.24

(0.600)

0.25

(0.010)TYP.

NOTES:

1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL

DIMENSIONS IS ± 0.254 mm (± 0.010).

2. ALL DIMENSIONS ARE IN MILLIMETERS (INCHES).

PIN 1 IDENTIFIER

PIN NO. FUNCTION PIN NO. FUNCTION

1

2

3

4

5

6

7

8

9

10

NO CONNECT

CE1

CE2

CLR



A0

A1

WR

CU

CUE

12

13

14

15

16

17

18

19

20

21

GROUND

NO CONNECT

BL

NO CONNECT

D0

D1

D2

D3

D4

D5

Character Set

ASCII

CODE

D0

D1

D2

D3

HEX

0

D6 D5 D4

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

000 0

001 1

010 2

011 3

100 4

101 5

110 6

111 7

NOTES: 1 = HIGH LEVEL

0 = LOW LEVEL

Electrical/Optical Characteristics over Operating Temperature Range

4.5 < VDD < 5.5 V (unless otherwise specified)

All Devices

25°C[1]

Parameter Symbol Min. Typ. Max. Max. Units Test Conditions

IDD Blank IDD (blnk) 1.0 4.0 mA All Digits Blanked

Input Current II-40 10 µAV

IN = 0 V to VDD

VDD = 5.0 V

Input Voltage High VIH 2.0 VDD V

Input Voltage Low VIL GND 0.8 V

IDD 4 Digits 20 dots/ IDD (#) 110 130 160 mA “#” ON in all four

character[2,3] locations

IDD Cursor all dots IDD (CU) 92 110 135 mA Cursor ON in all

ON @ 50% four locations

Notes:

1. VDD = 5.0 V

2. Average IDD measured at full brightness. Peak IDD = 28/15 x Average IDD (#).

3. IDD (#) max. = 130 mA, 150°C IC junction temperature and VDD = 5.5 V.

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Units

Supply Voltage VDD 4.5 5.0 5.5 V

Optical Characteristics at 25°C[1]

VDD = 5.0 V at Full Brightness

High Efficiency Red HDLO-3416

Parameter Symbol Min. Typ. Units Test Conditions

Average Luminous Intensity IV1.2 3.5 mcd “*” illuminated in all four digits.

per digit, Character Average 19 dots ON per digit.

Peak Wavelength λPEAK 635 nm

Dominant Wavelength[2] λD626 nm

Orange HDLA-3416

Parameter Symbol Min. Typ. Units Test Conditions

Average Luminous Intensity IV1.2 3.5 mcd “*” illuminated in all four digits.

per digit, Character Average 19 dots ON per digit.

Peak Wavelength λPEAK 600 nm

Dominant Wavelength[2] λD602 nm

Yellow HDLY-3416

Parameter Symbol Min. Typ. Units Test Conditions

Average Luminous Intensity IV1.2 3.7 mcd “*” illuminated in all four digits.

per digit, Character Average 19 dots ON per digit.

Peak Wavelength λPEAK 583 nm

Dominant Wavelength[2] λD585 nm

Green HDLG-3416

Parameter Symbol Min. Typ. Units Test Conditions

Average Luminous Intensity IV1.2 5.6 mcd “*” illuminated in all four digits.

per digit, Character Average 19 dots ON per digit.

Peak Wavelength λPEAK 568 nm

Dominant Wavelength[2] λD574 nm

Notes:

1. Refers to the initial case temperature of the device immediately prior to the light measurement.

2. Dominant wavelength, λD, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color

of the device.

AC Timing Characteristics over Operating

Temperature Range at VDD = 4.5 V

Parameter Symbol Min. Units

Address Setup tAS 10 ns

Address Hold tAH 40 ns

Data Setup tDS 50 ns

Data Hold tDH 40 ns

Chip Enable Setup tCES 0ns

Chip Enable Hold tCEH 0ns

Write Time tW75 ns

Clear tCLR 10 µs

Clear Disable tCLRD 1µs

Timing Diagram Enlarged Character Font

CES

CEH

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

CLRD

CLR

2.0 V

0.8 V

– A

, CU

– D

CLR

1.05 (0.041)

TYP.

6.9 (0.27)

TYP.

1.09 (0.043)

TYP.

0.25 (0.010)

TYP.

4.4 (0.175)

TYP.

NOTES:

1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE

ON ALL DIMENSIONS IS ± 0.254 mm (0.010").

2. DIMENSIONS ARE IN MILLIMETERS (INCHES).

Electrical Description

Pin Function Description

Chip Enable (CE1CE1 and CE2 must be a logic 0 to write to the

and CE2, pins display.

3 and 4)

Clear When CLR is a logic 0 the ASCII RAM is reset

(CLR, pin 5) to 20hex (space) and the Control Register/

Attribute RAM is reset to 00hex.

Cursor Enable CUE determines whether the IC displays the

(CUE pin 11) ASCII or the Cursor memory. (1 = Cursor,

0 = ASCII.)

Cursor Select CU determines whether data is stored in the

(CU, pin 10) ASCII RAM or the Attribute RAM/Control

Control Register.)

Write WR must be a logic 0 to store data in the

(WR, pin 9) display.

Address Inputs A0-A1 selects a specific location in the display

(A1 and A0, pins memory. Address 00 accesses the far right

7 and 8) display location. Address 11 accesses the far

left location.

Data Inputs (D0-D6,D

-D6 are used to specify the input data for

pins 16 – 22) the display.

VDD (pin 6) VDD is the positive power supply input.

GND (pin 12) GND is the display ground.

Blanking Input BL is used to flash the display, blank the

(BL, pin 14) display or to dim the display.

Display Internal Block

Diagram

Figure 1 shows the HDLX-3416

display internal block diagram.

The CMOS IC consists of a 4 x 7

Character RAM, a 2 x 4 Attribute

RAM, a 5 bit Control Register, a

128 character ASCII decoder and

the refresh circuitry necessary

to synchronize the decoding and

driving of four 5 x 7 dot matrix

displays.

Four 7 bit ASCII words are stored

in the Character RAM. The IC

reads the ASCII data and decodes

it via the 128 character ASCII

decoder. The ASCII decoder

includes the 64 character set of

the HPDL-2416, 32 lower case

ASCII symbols, and 32 foreign

language symbols.

A 5 bit word is stored in the

Control Register. Three fields

within the Control Register

provide an 8 level brightness

control, master blank, and

extended functions disable.

For each display digit location,

two bits are stored in the Attribute

RAM. One bit is used to enable

a cursor character at each digit

location. A second bit is used to

individually disable the blanking

features at each digit location.

The display is blanked and

dimmed through an internal

blanking input on the row drivers.

Logic within the IC allows the user

to dim the display either through

the BL input or through the

brightness control in the control

be blanked through the BL input,

the Master Blank in the Control

Disable in the Attribute RAM.

Figure 1. Internal Block Diagram.

CHARACTER RAM ASCII DECODER CHARACTER/CURSOR

MULTIPLEXER

WRITE

ADDRESS

– A

– D

7DATA IN

DATA

OUT 7CHARACTER

SELECT COLUMN

DATA 50

3ROW

SELECT

OSC + 32 + 7

DIGITAL

DUTY

CONTROL

ROW

DRIVERS

DISPLAY

COLUMN

DRIVERS

ROW

SELECT

BLANK

CLR

ATTRIBUTE RAM

DIGIT CURSORD

DIGIT BLANK

DISABLE

CLR

CONTROL REGISTER

MASTER

BLANK

– D

3BRIGHTNESS

LEVELS

CLR

EXTENDED

FUNCTIONS

DISPLAY

WRITE

CLR

WRITE

2READ

ADDRESS 51

CURSOR

CHARACTER

CHARACTER/

CURSOR

MULTIPLEXER

SELECT

CUE DC

(4 x 7)

WRITE

WRITE ADDRESSA

– A

READ ADDRESS

(2 x 4)

1 x 5

4 (LSBs)

2 (MSBs)

EFD

DBD

Display Clear

Data stored in the Character

RAM, Control Register, and

Attribute RAM will be cleared if

the clear (CLR) is held low for a

minimum of 10 µs. Note that the

display will be cleared regardless

of the state of the chip enables

(CE1, CE2). After the display is

cleared, the ASCII code for a

space (20hex) is loaded into all

character RAM locations and

00hex is loaded into all Attribute

RAM/Control Register memory

locations.

Data Entry

Figure 2 shows a truth table for

the HDLX-3416 display. Setting

the chip enables (CE1, CE2) to

logic 0 and the cursor select (CU)

to logic 1 will enable ASCII data

loading. When cursor select (CU)

is set to logic 0, data will be

loaded into the Control Register

and Attribute RAM. Address

inputs A0-A1 are used to select the

digit location in the display. Data

inputs D0-D6 are used to load

information into the display. Data

will be latched into the display on

the rising edge of the WR signal.

D0-D6, A0-A1, CE1, CE2, and CU

must be held stable during the

write cycle to ensure that correct

data is stored into the display.

Data can be loaded into the

display in any order. Note that

when A0 and A1 are logic 0, data

is stored in the right most display

location.

Cursor

When cursor enable (CUE) is a

logic 1, a cursor will be displayed

in all digit locations where a logic

1 has been stored in the Digit

Cursor memory in the Attribute

RAM. The cursor consists of all

35 dots ON at half brightness. A

flashing cursor can be displayed

by pulsing CUE. When CUE is a

logic 0, the ASCII data stored in

the Character RAM will be dis-

played regardless of the Digit

Cursor bits.

Blanking

Blanking of the display is con-

trolled through the BL input, the

Control Register, and Attribute

RAM. The user can achieve a

variety of functions by using these

controls in different combinations,

such as full hardware display

blank, software blank, blanking of

individual characters, and syn-

chronized flashing of individual

characters or entire display (by

CUE BL CLR CE1CE2WR CU A1A0D6D5D4D3D2D1D0Function

011 Display ASCII

111 Display Stored Cursor

XX0

XXXXXXX XXXX X X

Reset RAMs

X01 Blank Display but do not reset

RAMs and Control Register

Extended Intensity Master Digit Digit Write to Attribute RAM

0 0 0 Functions Control Blank Blank Cursor and Control Register

Disable Disable 0 0

0 = 000 = 100% 0 = Digit Digit DBDn = 0, Allows Digit n to be

0 0 1 Enable 001 = 060% Display Blank Cursor blanked

D1-D5010 = 040% ON Disable 1 1

011 = 027% DBDn = 1 Prevents Digit n

X X 1 0 0 0 1 = 100 = 017% 1 = Digit Digit from being blanked.

0 1 0 Disable 101 = 010% Display Blank Cursor

D1-D5110 = 007% Blanked Disable 2 2 DCn = 0 Removes cursor from

111 = 003% Digit n

D0Digit Digit

0 1 1 Always Blank Cursor DCn = 1 Stores cursor at

Enabled Disable 3 3 Digit n

1 0 0 Digit 0 ASCII Data (Right Most Character)

X X 1 0 0 0 1 0 1 Digit 1 ASCII Data Write to Character RAM

1 1 0 Digit 2 ASCII Data

1 1 1 Digit 3 ASCII Data (Left Most Character)

1XX

X X 1 X 1 X X X X X X X X X X X No Change

XX1

0 = Logic 0; 1 = Logic 1; X = Do Not Care

Figure 2. Display Truth Table.

strobing the blank input). All of

these blanking modes affect only

the output drivers, maintaining

the contents and write capability

of the internal RAMs and Control

of RAMs and Control Register can

take place even with the display

blanked.

Figure 3 shows how the Extended

Function Disable (bit D6 of the

Control Register), Master Blank

(bit D2 of the Control Register),

Digit Blank Disable (bit D1 of the

Attribute RAM), and BL input can

be used to blank the display.

When the Extended Function

Disable is a logic 1, the display

can be blanked only with the

BL input. When the Extended

Function Disable is a logic 0, the

display can be blanked through

the BL input, the Master Blank,

and the Digit Blank Disable. The

entire display will be blanked if

either the BL input is logic 0 or

the Master Blank is logic 1, pro-

viding all Digit Blank Disable

bits are logic 0. Those digits with

Digit Blank Disable bits a logic 1

will ignore both blank signals

and remain ON. The Digit Blank

Disable bits allow individual

characters to be blanked or

flashed in synchronization with

the BL input.

Table 1. Current Requirements at Different Brightness Levels

Symbol D5D4D3Brightness 25°C Typ. 25°C Max. Max. over Temp. Units

IDD(#) 0 0 0 100% 110 130 160 mA

0 0 1 60% 66 79 98 mA

0 1 0 40% 45 53 66 mA

0 1 1 27% 30 37 46 mA

1 0 0 17% 20 24 31 mA

1 0 1 10% 12 15 20 mA

110 7% 9 11 15 mA

111 3% 4 6 9 mA

EFD MB DBDnBL

00 00

00 X1

0X 10

01 0X

01 11

1X X0

1X X1

–Display Blanked by BL

–Display ON

–Display Blanked by BL.

Individual Characters “ON”

based on “1” being stored in DBDn

–Display Blanked by MB

–Display Blanked by MB.

Individual characters “ON”

based on “1” being stored in DBDn

–Display Blanked by BL

–Display ON

Dimming

Dimming of the display is con-

trolled through either the BL

input or the Control Register. A

pulse width modulated signal can

be applied to the BL input to dim

the display. A three bit word in

the Control Register generates an

internal pulse width modulated

signal to dim the display. The

internal dimming feature is

enabled only if the Extended

Function Disable is a logic 0.

Figure 3. Display Blanking Truth Table.

Bits 3–5 in the Control Register

provide internal brightness

control. These bits are interpreted

as a three bit binary code, with

code (000) corresponding to the

maximum brightness and code

(111) to the minimum brightness.

In addition to varying the display

brightness, bits 3–5 also vary the

average value of IDD. IDD can be

specified at any brightness level

as shown in Table 1.

Figure 4 shows a circuit designed

to dim the display from 98% to

2% by pulse width modulating

the BL input. A logarithmic or a

linear potentiometer may be used

to adjust the display intensity.

However, a logarithmic potentio-

meter matches the response of

the human eye and therefore

provides better resolution at low

intensities. The circuit frequency

should be designed to operate

at 10 kHz or higher. Lower fre-

quencies may cause the display

to flicker.

Extended Function

Disable

Extended Function Disable (bit

D6 of the Control Register)

disables the extended blanking

and dimming functions in the

HDLX-3416. If the Extended

Function Disable is a logic 1, the

internal brightness control,

Master Blank, and Digit Blank

Disable bits are ignored.

However, the BL input and

Cursor control are still active.

Mechanical and Electrical

Considerations

The HDLX-3416 is a 22 pin DIP

package that can be stacked

horizontally and vertically to

create arrays of any size. The

display is designed to operate

continuously from -40°C to

+85°C for all possible input

conditions.

The HDLX-3416 is assembled by

die attaching and wire bonding

140 LEDs and a CMOS IC to a

high temperature printed circuit

board. A polycarbonate lens is

placed over the PC board creating

an air gap environment for the

LED wire bonds. Backfill epoxy

environmentally seals the display

package. This package construc-

tion makes the display highly

tolerant to temperature cycling

and allows wave soldering.

The inputs to the CMOS IC are

protected against static discharge

and input current latchup. How-

ever, for best results standard

CMOS handling precautions

should be used. Prior to use, the

HDLX-3416 should be stored in

anti-static tubes or conductive

material. During assembly a

grounded conductive work area

should be used, and assembly

personnel should wear conductive

wrist straps. Lab coats made

of synthetic material should be

avoided since they are prone to

static charge build-up.

Input current latchup is caused

when the CMOS inputs are sub-

jected either to a voltage below

ground (Vin < ground) or to a

voltage higher than VDD (Vin >

VDD) and when a high current is

forced into the input. To prevent

input current latchup and ESD

damage, unused inputs should

be connected either to ground or

to VDD. Voltages should not be

applied to the inputs until VDD

has been applied to the display.

Transient input voltages should

be eliminated.

Soldering and Post Solder

Cleaning Instructions for

the HDLX-3416

The HDLX-3416 may be hand

soldered or wave soldered with

SN63 solder. When hand solder-

ing it is recommended that an

electronically temperature con-

trolled and securely grounded

soldering iron be used. For best

results, the iron tip temperature

should be set at 315°C (600°F).

For wave soldering, a rosin-based

RMA flux can be used. The solder

wave temperature should be set at

245°C ± 5°C (473°F ± 9°F), and

dwell in the wave should be set

between 11/2 to 3 seconds for

optimum soldering. The preheat

temperature should not exceed

110°C (230°F) as measured on

the solder side of the PC board.

For further information on solder-

ing and post solder cleaning, see

Application Note 1027, Soldering

LED Components.

Contrast Enhancement

The objective of contrast enhance-

ment is to provide good readabil-

ity in the end user’s ambient

lighting conditions. The concept

is to employ both luminance and

chrominance contrast techniques.

These enhance readability by

having the OFF-dots blend into

the display background and the

ON-dots vividly stand out against

the same background. For addi-

tional information on contrast

enhancement, see Application

Note 1015.

Figure 4. Intensity Modulation Control

Using an Astable Multivibrator

(reprinted with permission from

Electronics magazine, Sept. 19, 1974,

VNU Business pub. Inc.).

+ V

555

BL

(PIN 18)

10 kHz

OUTPUT

1 k

250 k

LOG

400 pF

1 k

1N914

7843

Color Range (nm)

Color Bin Min. Max.

Green 1 576.0 580.0

2 573.0 577.0

3 570.0 574.0

4 567.0 571.5

Yellow 3 581.5 585.0

4 584.0 587.5

5 586.5 590.0

6 589.0 592.5

www.semiconductor.agilent.com

Data subject to change.

July 11, 2001

Obsoletes 5966-0002E

5988-3268EN

Intensity Range (mcd)

Bin Min. Max.

A 1.20 1.77

B 1.45 2.47

C 2.02 3.46

D 2.83 4.85

E 3.97 6.79

F 5.55 9.50

G 7.78 13.30

Note:

Test conditions as specified in Optical Characteristic table.

Intensity Bin Limits

Note:

Test conditions as specified in Optical Characteristic table.

Color Bin Limits