VCC1-B3C-32M0000000 - VECTRON INTERNATIONAL

General Description

The 85408I is a low skew, high performance 1-to-8

Differential-to-LVDS Clock Distribution Chip. The 85408I CLK, nCLK

pair can accept most differential input levels and translates them to

3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling

(LVDS), the 85408I provides a low power, low noise, low skew,

point-to-point solution for distributing LVDS clock signals.

Guaranteed output and part-to-part skew specifications make the

85408I ideal for those applications demanding well defined

performance and repeatability.

Features

•Eight differential LVDS output pairs

•One differential clock input pair

•CLK, nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

•Maximum output frequency: 700MHz

•Translates any differential input signal (LVPECL, LVHSTL, SSTL,

HCSL) to LVDS levels without external bias networks

•Translates any single-ended input signal to LVDS with resistor

bias on nCLK input

•Multiple output enable inputs for disabling unused outputs

in reduced fanout applications

•Additive phase jitter, RMS: 167fs (typical)

•Output skew: 50ps (maximum)

•Part-to-part skew: 550ps (maximum)

•Propagation delay: 2.4ns (maximum)

•3.3V operating supply

•-40°C to 85°C ambient operating temperature

•Available in lead-free (RoHS 6) package

nQ6

nQ5

nQ4

nQ3

nQ2

nQ1

nQ7

GND

CLK

nCL

nQ0

CLK

nCLK

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

Pin Assignment

85408I

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

Block Diagram

Low Skew, 1-to-8, Differential-to-LVDS Clock 85408I

Datasheet

85408I D atasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2 nQ6, Q6 Output Differential output pair. LVDS interface levels.

3, 4 nQ5, Q5 Output Differential output pair. LVDS interface levels.

5, 6 nQ4, Q4 Output Differential output pair. LVDS interface levels.

7, 8 nQ3, Q3 Output Differential output pair. LVDS interface levels.

9, 10 nQ2, Q2 Output Differential output pair. LVDS interface levels.

11, 12 nQ1, Q1 Output Differential output pair. LVDS interface levels.

13, 14 nQ0, Q0 Output Differential output pair. LVDS interface levels.

15 nCLK Input Pullup Inverting differential clock input.

16 CLK Input Pulldown Non-inverting differential clock input.

17, 19, 20 VDD Power Positive supply pins.

18, 21 GND Power Power supply ground.

22 OE Input Pullup

Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH,

the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS /

LVTTL interface levels.

23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

CPD

Power Dissipation Capacitance

(per output) 4pF

RPULLUP Input Pullup Resistor 51 k

RPULLDOWN Input Pulldown Resistor 51 k

85408I D atasheet

Function Tables

Table 3A. Output Enable Function Table

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs Outputs

OE Q[0:7], nQ[0:7]

0 High-Impedance

1 Active (default)

Inputs Outputs

Input to Output Mode PolarityCLK nCLK Q[0:7] nQ[0:7]

0 1 LOW HIGH Differential to Differential Non-Inverting

1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

85408I D atasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V ± 5%, TA = -40°C to 85°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as VIH.

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, IO (LVDS)

Continuos Current

Surge Current

10mA

15mA

Package Thermal Impedance, JA 70°C/W (0 mps)

Storage Temperature, TSTG -65C to 150C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 90 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIH Input High Current VDD = VIN = 3.465V 5 µA

IIL Input Low Current VDD = 3.465V, VIN = 0V -150 µA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current CLK VDD = VIN = 3.465V 150 µA

nCLK VDD = VIN = 3.465V 5

IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA

nCLK VDD = 3.465V, VIN = 0V -150 µA

VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V

VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V

85408I D atasheet

Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crossing

point of the input to the differential output crossing point.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage RL = 100250 400 600 mV

VOD VOD Magnitude Change RL = 10050 mV

VOS Offset Voltage RL = 1001.125 1.4 1.6 V

VOS VOS Magnitude Change RL = 10050 mV

IOz High Impedance Leakage -10 +10 µA

IOFF Power Off Leakage -1 +1 µA

IOSD

Differential Output Short

Circuit Current -5.5 mA

IOS/IOSB Output Short Circuit Current -12 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 700 MHz

tPD Propagation Delay; NOTE 1 1.6 2.4 ns

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section

156.25MHz,

Integration Range: (12kHz – 20MHz) 167 fs

tsk(o) Output Skew; NOTE 2, 4 50 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 550 ps

tR / tFOutput Rise/Fall Time 20% to 80% 50 600 ps

odc Output Duty Cycle 45 55 %

tPZL, tPZH Output Enable Time; NOTE 5 5ns

tPLZ, tPHZ Output Disable Time; NOTE 5 5ns

85408I D atasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

Additive Phase Jitter @156.25MHz

12kHz – 20MHz = 167fs (typical)

85408I D atasheet

Parameter Measurement Information

3.3V LVDS Output Load AC Test Circuit

Propagation Delay

Output Skew

Differential Input Level

Part-to-Part Skew

Output Duty Cycle/Pulse Width/Period

GND

VDD

Q[0:7]

nQ[0:7]

nCLK

CLK

nQx

nQy

VDD

nCLK

CLK

GND

CMR

Cross Points

tsk(pp)

Part 1

Part 2

nQx

nQy

Q[0:7]

nQ[0:7]

85408I D atasheet

Parameter Measurement Information, continued

Output Rise/Fall Time

Differential Output Voltage Setup

Differential Output Short Circuit Setup

Offset Voltage Setup

Power Off Leakage Setup

Output Short Circuit Current Setup

20%

80% 80%

20%

Q[0:7]

nQ[0:7]

out

LVDS

DC Input

➤

OSD

LVDS

➤

OFF

out

LVDS

DC Input

➤

OSB

out

85408I D atasheet

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how the differential input can be wired to accept

single-ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

Figure 1. Single-Ended Signal Driving Differential Input

Recommendations for Unused Output Pins

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated

with 100 across. If they are left floating, there should be no trace

attached.

V_REF

Single Ended Clock Input

VDD

CLK

nCLK

0.1u R2

85408I D atasheet

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both signals must meet the VPP and

VCMR input requirements. Figures 2A to 2F show interface

examples for the CLK/nCLK input driven by the most common

driver types. The input interfaces suggested here are examples

only. Please consult with the vendor of the driver component to

confirm the driver termination requirements. For example, in Figure

2A, the input termination applies for IDT open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor,

use their termination recommendation.

2A. CLK/nCLK Input Driven by an IDT

Open Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. CLK/nCLK Input

Driven by a 2.5V SSTL Driver

50Ω

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

CSL

Diff

nti

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120Ω

85408I D atasheet

3.3V LVDS Driver Termination

A general LVDS interface is shown in Figure 3. In a 100 differential

transmission line environment, LVDS drivers require a matched load

termination of 100 across near the receiver input. For a multiple

LVDS outputs buffer, if only partial outputs are used, it is

recommended to terminate the unused outputs.

Figure 3. Typical LVDS Driver Termination

3.3V

LVDS Driver

100Ω

–

3.3V 50Ω

50Ω

100Ω Differential Transmission Line

85408I D atasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 85408I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 85408I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The

following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for devices is 125°C.

The equation for Tj is as follows: Tj = JA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 70°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.312W * 70°C/W = 106.8°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection

JA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65.0°C/W 62°C/W

85408I D atasheet

Reliability Information

Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP

Transistor Count

The transistor count for 85408I is: 1821

Pin compatible with SN65LVDS104

Package Outline and Package Dimensions

Package Outline - G Suffix for 24 Lead TSSOP Table 8. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

JA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65.0°C/W 62°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N16

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D7.70 7.90

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

0° 8°

aaa 0.10

85408I D atasheet

Ordering Information

Table 9. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

85408BGILF ICS85408BGILF “Lead-Free” 24 Lead TSSOP Tube -40C to 85C

85408BGILFT ICS85408BGILF “Lead-Free” 24 Lead TSSOP Tape & Reel -40C to 85C

85408I D atasheet

Revision History Sheet

Rev Table Page Description of Change Date

A 1 Pin Assignment - corrected package information from 300-MIL to 173-MIL. 8/25/04

AT8

Features Section - added Lead-Free bullet. Corrected Block Diagram.

Ordering Information Table - added Lead-Free information. 4/25/05

T5 5

AC Characteristics Table - added Additive Phase Jitter spec.

Added Additive Phase Jitter Plot.

Added Power Considerations section.

Converted datasheet format.

6/25/09

T9 1

Features section - removed reference to leaded devices.

Removed ICS Chip logo from General description.

Ordering Information - removed leaded devices.

Updated datasheet format.

3/5/15

T9 14 Ordering Information - removed Tape & Reel count and table note.

Deleted "HiperClockS" reference throughout the datasheet.

Updated datasheet header/footer.

2/23/16

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