85408I Low Skew, 1-to-8, Differential-to-LVDS Clock Datasheet General Description Features The 85408I is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip. The 85408I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the 85408I provides a low power, low noise, low skew, point-to-point solution for distributing LVDS clock signals. * * * Eight differential LVDS output pairs * * Maximum output frequency: 700MHz * Translates any single-ended input signal to LVDS with resistor bias on nCLK input * Multiple output enable inputs for disabling unused outputs in reduced fanout applications * * * * * * * Additive phase jitter, RMS: 167fs (typical) Guaranteed output and part-to-part skew specifications make the 85408I ideal for those applications demanding well defined performance and repeatability. Block Diagram CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks Output skew: 50ps (maximum) Part-to-part skew: 550ps (maximum) Propagation delay: 2.4ns (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment OE nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 Q0 nQ0 Q1 nQ1 Q2 nQ2 CLK nCLK One differential clock input pair Q3 nQ3 Q4 nQ4 24 23 22 21 20 19 18 17 16 15 14 13 Q7 nQ7 OE GND VDD VDD GND VDD CLK nCLK Q0 nQ0 85408I Q5 nQ5 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View Q6 nQ6 Q7 nQ7 (c)2016 Integrated Device Technology, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 1 Revision C, February 23, 2016 85408I Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 nQ6, Q6 Output Differential output pair. LVDS interface levels. 3, 4 nQ5, Q5 Output Differential output pair. LVDS interface levels. 5, 6 nQ4, Q4 Output Differential output pair. LVDS interface levels. 7, 8 nQ3, Q3 Output Differential output pair. LVDS interface levels. 9, 10 nQ2, Q2 Output Differential output pair. LVDS interface levels. 11, 12 nQ1, Q1 Output Differential output pair. LVDS interface levels. 13, 14 nQ0, Q0 Output Differential output pair. LVDS interface levels. 15 nCLK Input Pullup Pulldown Inverting differential clock input. 16 CLK Input 17, 19, 20 VDD Power Positive supply pins. 18, 21 GND Power Power supply ground. 22 OE Input 23, 24 nQ7, Q7 Output Pullup Non-inverting differential clock input. Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH, the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS / LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per output) 4 pF RPULLUP Input Pullup Resistor 51 k 51 k RPULLDOWN Input Pulldown Resistor (c)2016 Integrated Device Technology, Inc. 2 Minimum Typical Maximum Units Revision C, February 23, 2016 85408I Datasheet Function Tables Table 3A. Output Enable Function Table Inputs Outputs OE Q[0:7], nQ[0:7] 0 High-Impedance 1 Active (default) Table 3B. Clock Input Function Table Inputs Outputs CLK nCLK Q[0:7] nQ[0:7] Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. (c)2016 Integrated Device Technology, Inc. 3 Revision C, February 23, 2016 85408I Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 90 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 A -150 A Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units A CLK VDD = VIN = 3.465V 150 nCLK VDD = VIN = 3.465V 5 CLK VDD = 3.465V, VIN = 0V -5 A nCLK VDD = 3.465V, VIN = 0V -150 A 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. (c)2016 Integrated Device Technology, Inc. 4 Revision C, February 23, 2016 85408I Datasheet Table 4D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage RL = 100 250 400 600 mV VOD VOD Magnitude Change RL = 100 50 mV VOS Offset Voltage RL = 100 1.6 V VOS VOS Magnitude Change RL = 100 50 mV IOz High Impedance Leakage -10 +10 A IOFF Power Off Leakage -1 +1 A IOSD Differential Output Short Circuit Current -5.5 mA IOS/IOSB Output Short Circuit Current -12 mA 1.125 1.4 Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 50 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 550 ps tR / tF Output Rise/Fall Time 50 600 ps 45 1.6 156.25MHz, Integration Range: (12kHz - 20MHz) 20% to 80% Maximum Units 700 MHz 2.4 ns 167 fs odc Output Duty Cycle 55 % tPZL, tPZH Output Enable Time; NOTE 5 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crossing point of the input to the differential output crossing point. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. (c)2016 Integrated Device Technology, Inc. 5 Revision C, February 23, 2016 85408I Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @156.25MHz 12kHz - 20MHz = 167fs (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This (c)2016 Integrated Device Technology, Inc. is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 Revision C, February 23, 2016 85408I Datasheet Parameter Measurement Information VDD nCLK V VDD Cross Points PP V CMR CLK GND GND Differential Input Level 3.3V LVDS Output Load AC Test Circuit Par t 1 nCLK nQx CLK Qx nQ[0:7] nQy Par t 2 Qy Q[0:7] tPD tsk(pp) Part-to-Part Skew Propagation Delay nQx nQ[0:7] Qx Q[0:7] nQy Qy Output Duty Cycle/Pulse Width/Period Output Skew (c)2016 Integrated Device Technology, Inc. 7 Revision C, February 23, 2016 85408I Datasheet Parameter Measurement Information, continued nQ[0:7] 80% 80% VOD Q[0:7] 20% 20% tR tF Output Rise/Fall Time Offset Voltage Setup LVDS VDD IOFF Differential Output Voltage Setup Power Off Leakage Setup VDD VDD out IOS out DC Input LVDS DC Input LVDS IOSD IOSB out out Differential Output Short Circuit Setup (c)2016 Integrated Device Technology, Inc. Output Short Circuit Current Setup 8 Revision C, February 23, 2016 85408I Datasheet Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input Recommendations for Unused Output Pins Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. (c)2016 Integrated Device Technology, Inc. 9 Revision C, February 23, 2016 85408I Datasheet Differential Clock Input Interface only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples 3.3V 1.8V Zo = 50 CLK Zo = 50 nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50 R2 50 Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 R4 120 Zo = 60 *R3 CLK CLK Zo = 60 nCLK nCLK HCSL *R4 SSTL Differential Input R1 120 Differential Input Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver (c)2016 Integrated Device Technology, Inc. R2 120 10 Revision C, February 23, 2016 85408I Datasheet 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50 3.3V LVDS Driver + R1 100 - 50 100 Differential Transmission Line Figure 3. Typical LVDS Driver Termination (c)2016 Integrated Device Technology, Inc. 11 Revision C, February 23, 2016 85408I Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 85408I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 85408I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 70C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.312W * 70C/W = 106.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards (c)2016 Integrated Device Technology, Inc. 0 1 2.5 70C/W 65.0C/W 62C/W 12 Revision C, February 23, 2016 85408I Datasheet Reliability Information Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70C/W 65.0C/W 62C/W Transistor Count The transistor count for 85408I is: 1821 Pin compatible with SN65LVDS104 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 (c)2016 Integrated Device Technology, Inc. 13 Revision C, February 23, 2016 85408I Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 85408BGILF ICS85408BGILF "Lead-Free" 24 Lead TSSOP Tube -40C to 85C 85408BGILFT ICS85408BGILF "Lead-Free" 24 Lead TSSOP Tape & Reel -40C to 85C (c)2016 Integrated Device Technology, Inc. 14 Revision C, February 23, 2016 85408I Datasheet Revision History Sheet Rev Table A A T8 T5 B T9 B T9 C Page Description of Change Date 1 Pin Assignment - corrected package information from 300-MIL to 173-MIL. 8/25/04 1 11 Features Section - added Lead-Free bullet. Corrected Block Diagram. Ordering Information Table - added Lead-Free information. 4/25/05 5 6 12 AC Characteristics Table - added Additive Phase Jitter spec. Added Additive Phase Jitter Plot. Added Power Considerations section. Converted datasheet format. 6/25/09 1 1 14 15 Features section - removed reference to leaded devices. Removed ICS Chip logo from General description. Ordering Information - removed leaded devices. Updated datasheet format. 3/5/15 14 Ordering Information - removed Tape & Reel count and table note. Deleted "HiperClockS" reference throughout the datasheet. Updated datasheet header/footer. 2/23/16 (c)2016 Integrated Device Technology, Inc. 15 Revision C, February 23, 2016 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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