SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DHigh-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 13 ns
D±6-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DEight High-Current Latches in a Single
Package
DFull Parallel Access for Loading
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D V
8Q
4Q
GND
LE
SN54HC373 ...FK PACKAGE
(TOP VIEW)
CC
SN54HC373 ...J OR W PACKAGE
SN74HC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that
were set up at the D inputs.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 20 SN74HC373N SN74HC373N
SOIC − DW
Tube of 25 SN74HC373DW
HC373
SOIC − DW Reel of 2000 SN74HC373DWR HC373
−40°C to 85°C
SOP − NS Reel of 2000 SN74HC373NSR HC373
−40°C to 85°CSSOP − DB Reel of 2000 SN74HC373DBR HC373
Tube of 70 SN74HC373PW
TSSOP − PW Reel of 2000 SN74HC373PWR HC373
TSSOP − PW
Reel of 250 SN74HC373PWT
HC373
CDIP − J Tube of 20 SNJ54HC373J SNJ54HC373J
−55°C to 125°CCFP − W Tube of 85 SNJ54HC373W SNJ54HC373W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC373FK SNJ54HC373FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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#- && $##(
$'"! !$& ./0 && $## # ##'
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$!#- '# #!#&, !&"'# #- && $##(
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
32
LE
1D
C1
1D 1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC373 SN74HC373
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆vInput transition rise/fall time VCC = 4.5 V 500 500 ns
∆t/∆v
Input transition rise/fall time
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9 V
VOH
VI = VIH or VIL
IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84
V
IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
V
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V to 6 V 3 10 10 10 pF
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 80 120 100
t
w
Pulse duration, LE high 4.5 V 16 24 20 ns
tw
Pulse duration, LE high
6 V 14 20 17
ns
2 V 50 75 63
t
su
Setup time, data before LE↓4.5 V 10 15 13 ns
tsu
Setup time, data before LE↓
6 V 9 13 11
ns
2 V 20 26 24
t
h
Hold time, data after LE↓4.5 V 10 13 12 ns
th
Hold time, data after LE↓
6 V 10 13 12
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 58 150 225 190
D Q 4.5 V 15 30 45 38
tpd
D
Q
6 V 13 26 38 32
ns
tpd 2 V 73 175 265 220 ns
LE Any Q 4.5 V 18 35 53 44
LE
Any Q
6 V 15 30 45 38
2 V 65 150 225 190
t
en
OE Any Q 4.5 V 17 30 45 38 ns
ten
OE
Any Q
6 V 14 26 38 32
ns
2 V 50 150 225 190
t
dis
OE Any Q 4.5 V 15 30 45 38 ns
tdis
OE
Any Q
6 V 13 26 38 32
ns
2 V 28 60 90 75
t
t
Any Q 4.5 V 8 12 18 15 ns
tt
Any Q
6 V 6 10 15 13
ns
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 82 200 300 250
D Q 4.5 V 22 40 60 50
tpd
D
Q
6 V 19 34 51 43
ns
tpd 2 V 100 225 335 285 ns
LE Any Q 4.5 V 24 45 67 57
LE
Any Q
6 V 20 38 57 48
2 V 90 200 300 250
t
en
OE Any Q 4.5 V 23 40 60 50 ns
ten
OE
Any Q
6 V 19 34 51 43
ns
2 V 45 210 315 265
t
t
Any Q 4.5 V 17 42 63 53 ns
tt
Any Q
6 V 13 36 53 45
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per latch No load 100 pF
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
50%
10%
90%
VCC
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
50%
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
50%
50%
tPZH tPHZ
Output
Waveform 2
(See Note B)
≈VCC
Test
Point
From Output
Under Test
RL
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open−−
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. t
PLH
and t
PHL
are the same as t
pd
.
CL
(see Note A)
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8407201VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8407201VR
A
SNV54HC373J
5962-8407201VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8407201VS
A
SNV54HC373W
84072012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84072012A
SNJ54HC
373FK
8407201RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8407201RA
SNJ54HC373J
8407201SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201SA
SNJ54HC373W
JM38510/65403B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65403B2A
JM38510/65403BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65403BRA
M38510/65403B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65403B2A
M38510/65403BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65403BRA
SN54HC373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC373J
SN74HC373DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85
SN74HC373DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC373DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N
SN74HC373N3 OBSOLETE PDIP N 20 TBD Call TI Call TI -40 to 85
SN74HC373NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N
SN74HC373NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85
SN74HC373PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWT ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SN74HC373PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC373PWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC373
SNJ54HC373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84072012A
SNJ54HC
373FK
SNJ54HC373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8407201RA
SNJ54HC373J
SNJ54HC373W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201SA
SNJ54HC373W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC373, SN54HC373-SP, SN74HC373 :
•Catalog: SN74HC373, SN54HC373
•Military: SN54HC373
•Space: SN54HC373-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74HC373NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74HC373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74HC373PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC373DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74HC373DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74HC373NSR SO NS 20 2000 367.0 367.0 45.0
SN74HC373PWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74HC373PWT TSSOP PW 20 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 1-Jul-2013
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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