Description Features Pin-to-Pin Compatible w ith ML4800 and FAN4800 and CM6800 and CM6800A PWM Configurable for Current Mode or Feedforw ard Voltage-Mode Operation Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in One IC Low Operating Current Innovative Sw itching-Charge Multiplier Divider Average-Current Mode for Input-Current Shaping PFC Over-Voltage and Under-Voltage Protections PFC Feedback Open-Loop Protection Cycle-by-Cycle Current Limiting for PFC/PWM Pow er-on Sequence Control and Soft-Start The highly integrated FAN4800AS/CS/01S/02S parts are specially designed for pow er supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections / compensation. They are available in 16-pin DIP and SOP packages. The PWM can be used in either current or voltage mode. In voltage mode, feed-forw ard from the PFC output bus can reduce the secondary output ripple. Compared w ith older productions, ML4800 and FAN4800, FAN4800AS/CS/01S/02S have low er operation current that saves pow er consumption in external devices. FAN4800AS/CS/01S/02S have accurate 49.9% maximum duty of PWM that makes the hold-up time longer. Brow nout protection and PFC soft-start functions available in this series are not available in ML4800 and FAN4800. Interleaved PFC/PWM Sw itching To evaluate FAN4800AS/CS/01S/02S for replacing existing FAN4800 and ML4800 boards, five things must be completed before the fine-tuning procedure: Improved Efficiency at Light Load 1. Change RAC resister from the old value to a higher resister: betw een 6 M to 8 M. 2. Change RT/CT pin from the existing values to RT =6.8k and CT =1000 pF to have f PFC=64 kHz and f PWM=64 kHz. 3. The VRMS pin needs to be 1.224 V at V IN=85 V AC for universal input application from line input from 85 V AC to 270 V AC. 4. At full load, the average V VEA needs to be ~4.5 V and the ripple of V VEA needs to be less than 400 mV. 5. For the Soft-Start pin, the soft-start current has been reduced to half the FAN4800 capacitor. Brow nout Protection f RT CT =4*f PFC=4*f PWM for FAN4800AS/01S f RT CT =4*f PFC=2*f PWM for FAN4800CS/02S Applications Desktop PC Pow er Supply Internet Server Pow er Supply LCD TV, Monitor Pow er Supply UPS Battery Charger DC Motor Pow er Supply Monitor Pow er Supply Telecom System Pow er Supply Distributed Pow er Related Resources There are tw o differences from FAN4800A/C/01/02 to FAN4800AS/CS/01S/02S: 1. Under-voltage protection debounce time is extended to one second. 2. PWM gate clamp voltage is raised to 19 V. AN-8027 - FAN480X PFC+PWM Combination Controller Application (c) 2010 Semiconductor Components Industries, LLC Nov ember-2017, Rev . 2 Publication Order Number: FAN4800AS/D FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination FAN4800AS/CS/01S/2S PFC/PWM Controller Combination Part Number Operating Temperature Range FAN4800ASNY -40C to +105C 16-Pin Dual Inline Package (DIP) FAN4800ASMY -40C to +105C 16-Pin Small Outline Package (SOP) FAN4800CSNY -40C to +105C 16-Pin Dual Inline Package (DIP) FAN4800CSMY -40C to +105C 16-Pin Small Outline Package (SOP) FAN4801SNY -40C to +105C 16-Pin Dual Inline Package (DIP) FAN4801SMY -40C to +105C 16-Pin Small Outline Package (SOP) FAN4802SNY -40C to +105C 16-Pin Dual Inline Package (DIP) FAN4802SMY -40C to +105C 16-Pin Small Outline Package (SOP) Package Application Diagram IEA VEA IAC FBPFC ISENSE VRMS SS FBPWM VREF Figure 1. VREF VDD VDD OPFC OPWM RT/CT GND RAMP ILIMIT Typical Application, Current Mode www.onsemi.com 2 Packing Method Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Ordering Information IEA VEA IAC FBPFC VREF ISENSE VRMS SS FBPWM VREF VDD VDD OPFC OPWM RT/CT GND RAMP ILIMIT VREF Figure 2. Typical Application, Voltage Mode www.onsemi.com 3 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Application Diagram VEA IEA 16 VDD 1 VREF 0.5V 7.5V REFERENCE PFC UVP VDD 27V/28V VDD OVP S 0.3V Low Power Detect Comparator gmv FBPFC 15 2.5V/2.75V PFC OVP R VRMS 2 gmi Q Q OPFC 12 S SET CLR Q VGATE-CLAMP Q 1.05V/1.9V VRMS AC UVP Gain Modulator 4 14 PFC ILIMIT R IAC SET CLR -1.15V Rmul 2.5V 13 Rmul ISENSE 3 RT/CT 7 OSCILLATOR 300 RAMP DUTY CYCLE LIMIT 8 1.5V OPWM S FBPWM 1.15V/2.4V FBPFC 6 VDD 10A R SET CLR Q 11 Q VGATE-CLAMP VIN OK 300 SS 5 1V VREF ILIMIT 9 GND 10 VDD Figure 3. VEA FAN4800AS/CS Function Block Diagram IEA 16 UVLO VDD 1 7.5V REFERENCE PFC UVP VDD 27V/28V VDD OVP S 0.3V gmv Low Power Detect Comparator FBPFC 15 2.5V/2.75V PFC OVP R VRMS Range 2 4 14 Q Q OPFC 12 PFC ILIMIT gmi S R IAC SET CLR -1.15V Rmul 2.5V 13 VREF 0.5V SET CLR Q VGATE-CLAMP Q 1.05V/1.9V VRMS AC UVP Gain Modulator Rmul ISENSE 3 RT/CT 7 OSCILLATOR 300 RAMP DUTY CYCLE LIMIT 8 1.5V OPWM S FBPWM 1.15V/2.4V FBPFC 6 VDD 10A R SS 5 1V VREF ILIMIT 9 GND 10 VDD Figure 4. UVLO FAN4801S/02S Function Block Diagram www.onsemi.com 4 CLR Q 11 Q VGATE-CLAMP VIN OK 300 SET FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Block Diagram - ON Semiconductor Logo Z - Plant Code X - 1-Digit Year Code YY - 2-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (N:DIP) P - Y: Green Package M - Manufacture Flow Code Figure 5. DIP Top Mark - ON Semiconductor Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (M:SOP) P - Y: Green Package M - Manufacture Flow Code Figure 6. SOP Top Mark Pin Configuration 1 IEA 2 IAC 3 ISENSE 4 VRMS 5 SS 6 FBPWM 7 RT/CT GND 10 8 RAMP ILIMIT 9 Figure 7. VEA 16 FBPFC 15 VREF 14 VDD 13 OPFC 12 OPWM 11 Pin Configuration (Top View ) www.onsemi.com 5 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Marking Information Pin # Name Description 1 IEA Output of PFC Current Am plifier . The signal from this pin is compared w ith an internal saw tooth to determine the pulse w idth for PFC gate drive. 2 IAC Input AC Current. For normal operation, this input provides current reference for the multiplier. The suggested maximum IAC is 100 A. 3 ISENSE PFC Current Sense . The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. 4 VRMS Line-Voltage Detection. The pin is used for the PFC multiplier. 5 SS 6 FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. 7 RT/CT Oscillator RC Tim ing Connection. Oscillator timing node; timing set by RT and CT . 8 RAMP PWM RAMP Input. In current mode, this pin functions as the current-sense input; w hen in voltage mode, it is the feedforw ard sense input from PFC output 380 V (feedforw ard ramp). 9 ILIMIT Peak Current Lim it Setting for PWM . The peak current limits setting for PWM. 10 GND Ground. 11 OPWM PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally clamped under 19 V to protect the MOSFET. 12 OPFC PFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped under 15 V to protect the MOSFET. 13 VDD Supply. The pow er supply pin. The threshold voltages for startup and turn-off are 11 V and 9.3 V, respectively. The operating current is low er than 10 mA. 14 VREF Reference Voltage . Buffered output for the internal 7.5 V reference. 15 FBPFC Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider netw ork. 16 VEA PWM Soft-Start. During startup, the SS pin charges an external capacitor w ith a 10 A constant current source. The voltage on FBPWM is clamped by SS during startup. If a protection condition occurs and/or PWM is disabled, the SS pin is quickly discharged. Output of PFC Voltage Am plifier . The error amplifier output for PFC voltage feedback loop. A compensation netw ork is connected betw een this pin and ground. Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit 30 V V DD DC Supply Voltage VH SS, FBPWM, RAMP, OPWM, OPFC, VREF -0.3 30.0 V VL IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA -0.3 7.0 V 0 V VREF+0.3 V -5.0 0.7 V 1 mA V IEA IEA VN ISENSE IAC Input AC Current www.onsemi.com 6 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Pin Definitions V REF Output Current 5 mA IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A PD Pow er Dissipation TA < 50C 800 mW JA Thermal Resistance (Junction-to-Air) JC Thermal Resistance (Junction-to-Case) TJ DIP 80.80 SOP 104.10 DIP 35.38 SOP 40.41 C/W C/W Operating Junction Temperature -40 +125 C TST G Storage Temperature Range -55 +150 C TL Lead Temperature(Soldering) +260 C ESD Electrostatic Discharge Capability Human Body Model 5.0 Charged Device Model 1.5 kV Notes: 1. All voltage values, except differential voltage, are given w ith respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Min. Operating Ambient Temperature -40 www.onsemi.com 7 Typ. Max. Unit +105 C FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination IREF Unless otherw ise noted, V DD=15 V, TA = 25C, TA =TJ , RT =6.8 k, and CT =1000 pF. Symbol Parameter Conditions Min. Typ. Max. Unit 26 V 30 80 A 2.0 2.6 5.0 mA 11 12 V 1.9 V 29 V V DD Section V DD-OP Continuously Operating Voltage IDD ST Startup Current V DD=V T H-ON-0.1 V; OPFC OPWM Open IDD-OP Operating Current V DD=13 V; OPFC OPWM Open V T H-ON Turn-on Threshold Voltage 10 V T H Hysteresis 1.3 V DD OVP 27 V DD-OVP V DD-OVP V DD OVP Hysteresis 28 1 V Oscillator f OSC-RT /CT f OSC RT/CT Frequency RT =6.8 k, CT =1000 pF 240 256 268 kHz PFC & PWM Frequency RT =6.8 k, CT =1000 pF 60 64 67 kHz 120 128 134 PWM Frequency (3) f DV Voltage Stability f DT Temperature Stability (3) (3) 11 V V DD 22 V 2 % -40C ~ +105C 2 % 70 kHz f TV Total Variation (PFC & PWM) f RV Ramp Voltage Valley to Peak IOSC-DIS Discharge Current V RAMP =0V, V RT /CT =2.5 V f RANGE Frequency Range tPFC-DEAD Line, Temperature 58 2.8 V 6.5 15.0 mA 50 75 kHz PFC Dead Time RT =6.8 k, CT =1000 pF 400 600 800 ns Reference Voltage IREF=0 mA, CREF=0.1 F 7.4 7.5 7.6 V V VREF1 Load Regulation of Reference Voltage CREF=0.1 F, IREF=0 mA to 3.5 mA V VDD=14 V, Rise/Fall Time > 20 s 30 50 mV V VREF2 Line Regulation of Reference Voltage CREF=0.1 F, V VDD=11 V to 22 V 25 mV Temperature Stability (3) -40C ~ +105C 0.5 % 7.35 7.65 V 25 mV V REF V VREF V VREF-DT 0.4 V VREF-T V Total Variation V VREF-LS Long-Term Stability (3) TJ =125C, 0 ~ 1000 HRs 5 Maximum Current V VREF > 7.35 V 5 IREF-MAX (3) Line, Load, Temp mA PFC OVP Com parator V PFC-OVP V PFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V PFC OVP Hysteresis 200 250 300 mV 0.2 0.3 0.4 V 2.3 2.4 2.5 V Low -Pow er Detect Com parator V VEAOFF VEA Voltage OFF OPFC V IN OK Com parator V RD-FBPFC Voltage Level on FBPFC to Enable www.onsemi.com 8 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Electrical Characteristics V RD-FBPFC Hysteresis 1.15 1.25 1.35 V Min. Typ. Max. Unit 2.45 2.50 2.55 V 35 42 Electrical Characteristics (Continued) Unless otherw ise noted, V DD=15 V, TA = 25C, TA =TJ , RT =6.8 k, and CT =1000 pF. Symbol Parameter Conditions Voltage Error Am plifier V REF Reference Voltage (3) AV Open-Loop Gain Gmv Transconductance V NONINV =V INV , V VEA =3.75 V 50 70 IFBPFC-L Maximum Source Current V FBPFC=2 V, V VEA =1.5 V 40 50 IFBPFC-H Maximum Sink Current V FBPFC=3 V, V VEA =6 V IBS -50 Input Bias Current -1 V VEA-H Output High Voltage on V VEA 5.8 V VEA-L Output Low Voltage on V VEA dB 90 umho A -40 A 1 A 6.0 V 0.1 0.4 V 88 100 umho 10 mV 7.4 8.0 V 0.1 0.4 V Current Error Am plifier GmI Transconductance V NONINV =V INV , V IEA =3.75 V 78 V OFFSET Input Offset Voltage V VEA =0 V, IAC Open -10 V IEA-H Output High Voltage V IEA-L Output Low Voltage 6.8 IL Source Current V ISENSE =-0.6 V, V IEA =1.5 V IH Sink Current V ISENSE =+0.6 V, V IEA =4.0 V AI (3) Open-Loop Gain 35 50 -50 40 A -35 50 A dB TriFault DetectTM tFBPFC_OPEN V PFC-UVP Time to FBPFC Open V FBPFC=V PFC-UVP to FBPFC OPEN, 470 pF from FBPFC to GND PFC Feedback Under-Voltage Protection 0.4 2 4 ms 0.5 0.6 V 100 A Gain Modulator IAC GAIN BW V O(gm) Input for AC Current(3) GAIN Modulator (4) Multiplier Linear Range 0 IAC=17.67A, V RMS =1.080V V FBPFC=2.25V 7.500 9.000 10.500 IAC=20.00 A, V RMS =1.224 V V FBPFC=2.25 V 6.367 7.004 7.704 IAC=25.69 A, V RMS =1.585 V V FBPFC=2.25 V 3.801 4.182 4.600 IAC=51.62 A, V RMS =3.169 V V FBPFC=2.25 V 0.950 1.045 1.149 IAC=62.23 A, V RMS =3.803 V V FBPFC=2.25 V 0.660 0.726 0.798 Bandw idth(3) IAC=40 A Output Voltage=5.7 k x (ISENSE IOFFSET ) IAC=20 A, V RMS =1.224 V V FBPFC=2.25 V www.onsemi.com 9 2 0.710 0.798 kHz 0.885 V FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination OPWM During Startup V PFC-ILIMIT V PK Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit PFC ILIMIT -Gain Modulator Output -1.35 IAC=17.67 A, V RMS =1.08 V V FBPFC=2.25 V -1.20 -1.05 200 V mV Electrical Characteristics (Continued) Unless otherw ise noted, V DD=15 V, TA = 25C, TA =TJ , RT =6.8 k, and CT =1000 pF. Symbol Parameter Conditions Min. Typ. Max. Unit 13 15 17 V 1.5 V PFC Output Driver V GAT E-CLAMP Gate Output Clamping Voltage V DD=22 V V GAT E-L Gate Low Voltage V DD=15 V, IO=100 mA V GAT E-H Gate High Voltage V DD=13 V, IO=100 mA 8 tR Gate Rising Time V DD=15 V, CL=4. 7nF, O/P= 2 V to 9 V 40 70 120 ns tF Gate Falling Time V DD=15 V; CL=4.7 nF, O/P= 9 V to 2 V 40 60 110 ns DPFC-MAX Maximum Duty Cycle V IEA <1.2 V 94 97 DPFC-MIN Minimum Duty Cycle V IEA >4.5 V V RMS-UVL V RMS Threshold Low When V RMS =1.05 V at 75 V RMS 1.03 V RMS-UVH V RMS Threshold High When V RMS =1.9 V at 85*1.414 V % 0 % 1.05 1.08 V 1.88 1.90 1.94 V Hysteresis 750 850 950 mV Under Voltage Protection Debounce Time 850 1000 1150 ms 9.5 10.0 10.5 V Brow nout V RMS-UVP tUVP Soft Start V SS-MAX Maximum Voltage ISS Soft-Start Current V DD=15 V 10 A PWM ILIMIT Com parator V PWM-ILIMIT Threshold Voltage tPD Propagation Delay to Output tPWM-BNK Leading-Edge Blanking Time 0.95 1.00 1.05 250 V ns 170 250 350 ns Range (FAN4801S/02S) V VRMS-L RMS AC Voltage Low When V VRMS =1.95 V at 132 V RMS 1.90 1.95 2.00 V V VRMS-H RMS AC Voltage High When V VRMS =2.45 V at 150 V RMS 2.40 2.45 2.50 V V VEA-L VEA LOW When V VEA =1.95 V at 30% Loading 1.90 1.95 2.00 V V VEA-H VEA HIGH When V VEA =2.45 V at 40% Loading 2.40 2.45 2.50 V 18 20 22 A 18 19 20 V 1.5 V IT C Source Current from FBPFC PWM Output Driver V GAT E-CLAMP Gate Output Clamping Voltage V DD=22 V V GAT E-L Gate Low Voltage V DD=15 V, IO=100 mA V GAT E-H Gate High Voltage V DD=13 V, IO=100 mA www.onsemi.com 10 8 V FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination PFC ILIMIT Com parator Gate Rising Time V DD=15 V, CL=4.7 nF 30 60 120 ns tF Gate Falling Time V DD=15 V, CL=4.7 nF 30 50 110 ns DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 % V PWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This GAIN is the maximum gain of modulation w ith a given V RMS voltage w hen V VEA is saturated to HIGH. www.onsemi.com 11 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination tR 28.04 18.0 28.02 16.0 28.00 14.0 VDD-OVP(V) IDD-ST(uA) 20.0 12.0 10.0 8.0 6.0 27.94 27.92 27.90 2.0 27.88 27.86 -40 -25 -10 5 Figure 8. 20 35 50 65 80 95 110 125 -40 -25 -10 IDD-ST vs. Tem perature 5 Figure 9. 65.0 7.520 64.9 7.515 64.8 7.510 VVREF(V) FOSC(kHz) 27.96 4.0 0.0 64.7 64.6 64.5 20 35 50 65 80 95 110 125 V DD-OVP vs. Tem perature 7.505 7.500 7.495 7.490 64.4 7.485 64.3 7.480 64.2 7.475 -40 -25 -10 5 Figure 10. 20 35 50 65 80 95 110 125 -40 -25 -10 f OSC vs. Tem perature 5 Figure 11. 2.742 2.502 2.740 2.500 20 35 50 65 80 95 110 125 V VREF vs. Tem perature 2.498 2.738 VREF(V) VPFC-OVP(V) 27.98 2.736 2.734 2.496 2.494 2.492 2.732 2.490 2.730 2.488 -40 -25 -10 5 Figure 12. 20 35 50 65 80 95 110 125 -40 -25 -10 V PFC-OVP vs. Tem perature 5 Figure 13. 74 20 35 50 65 80 95 110 125 V REF vs. Tem perature 94 92 90 GmI(umho) GmV(umho) 73 73 72 88 86 84 82 72 80 71 78 -40 -25 -10 5 Figure 14. 20 35 50 65 80 95 110 125 -40 Gm V vs. Tem perature -10 5 Figure 15. -1.177 20 35 50 65 80 95 110 125 Gm I vs. Tem perature 1.010 1.009 VPWM-ILIMIT(V) -1.178 VPFC-ILIMIT(V) -25 -1.179 -1.180 -1.181 1.008 1.007 1.006 1.005 1.004 -1.182 1.003 1.002 -1.183 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 www.onsemi.com 12 5 20 35 50 65 80 95 110 125 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Typical Characteristics V PFC-ILIMIT vs. Tem perature Figure 17. 1.048 867.5 1.047 867.0 1.046 866.5 VRMS-UVP(mV) VRMS-UVP(V) Figure 16. 1.045 1.044 1.043 1.042 1.041 865.5 865.0 864.5 864.0 863.5 863.0 1.039 862.5 862.0 -40 -25 -10 5 Figure 18. 20 35 50 65 80 95 110 125 -40 -25 -10 V RMS-UVP vs. Tem perature 5 14.7 19.00 14.6 18.95 14.5 14.4 14.3 14.2 14.1 14.0 20 35 50 65 80 95 110 125 V RMS-UVP vs. Tem perature Figure 19. VGATE-CLAMP-PWM(V) VGATE-CLAMP-PFC(V) 866.0 1.040 1.038 V PWM-ILIMIT vs. Tem perature 18.90 18.85 18.80 18.75 18.70 18.65 18.60 18.55 18.50 13.9 -40 -25 -10 5 Figure 20. 20 35 50 65 80 95 -40 -25 -10 110 125 V GATE-CLAMP-PFC vs. Tem perature Figure 21. 96.06 5 20 35 50 65 80 95 110 125 V GATE-CLAMP-PWM vs. Tem perature 49.80 96.04 49.75 DPWM-MAX(%) DPFC-MAX(%) 96.02 96.00 95.98 95.96 95.94 49.70 49.65 49.60 95.92 49.55 95.90 95.88 49.50 -40 -25 -10 5 Figure 22. 20 35 50 65 80 95 110 125 -40 -25 DPFC-MAX vs. Tem perature 5 Figure 23. 10.1 21.0 10.0 20.8 9.9 20 35 50 65 80 95 110 125 DPWM-MAX vs. Tem perature 20.6 ITC(uA) 9.8 ISS(uA) -10 9.7 9.6 9.5 9.4 20.4 20.2 20.0 19.8 9.3 19.6 9.2 9.1 19.4 -40 -25 -10 5 Figure 24. 20 35 50 65 80 95 110 125 -40 -25 -10 ISS vs. Tem perature 5 Figure 25. www.onsemi.com 13 20 35 50 65 80 95 ITC vs. Tem perature 110 125 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Typical Characteristics The FAN4800AS/CS/01S/02S consist of an average current controlled, continuous-boost, Pow er Factor Correction (PFC) front-end and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in current or voltage mode. In voltage mode, feedforw ard from the PFC output bus can help improve the line regulation of PWM. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This proprietary leading / trailing edge modulation results in a higher usable PFC error amplifier bandw idth and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM w ith the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). In addition to pow er factor correction, a number of protection features are built into this series. They include soft-start, PFC over-voltage protection, peak current limiting, brow nout protection, duty cycle limiting, and under-voltage lockout (UVLO). Gain Modulator The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage w aveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: 1. A current representing the instantaneous input voltage (amplitude and w ave shape) to the PFC. The rectified AC input sine w ave is converted to a proportional current via a resistor and is fed into the gain modulator at IAC. Sampling current in this w ay minimizes ground noise, required in high-pow er, sw itching-pow er conversion environments. The gain modulator responds linearly to this current. form of the output of the gain modulator is: IGAINMOD I AC VEA 0.7 K (1) VRMS 2 Note that the output current of the gain modulator is limited around 159 A and the maximum output voltage of the gain modulator is limited to 159 A x 5.7 k=0.906 V. This 0.906 V also determines the maximum input pow er. How ever, IGAINMOD cannot be measured directly from ISENSE. ISENSE =IGAINMOD - IOFFSET and IOFFSET can only be measured w hen V VEA is less than 0.5 V and IGAINMOD is 0 A. Typical IOFFSET is around 31 A ~ 48 A. Selecting RAC for the IAC Pin The IAC pin is the input of the gain modulator and also a current mirror input that requires current input. Selecting a proper resistor, RAC, provides a good sine w ave current derived from the line voltage and helps program the maximum input pow er and minimum input line voltage. RAC=V IN peak x 56 k. For example, if the minimum line voltage is 75 V AC, the RAC=75 x 1.414 x 56 k=6 M. Current Amplifier Error, IEA The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed w ith a current, w hich results in a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flow ing in the PFC circuit and is typically derived from a current-sense resistor in series w ith the negative terminal of the input bridge rectifier. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to V RMS (except at unusually low values of V RMS , w here special gain contouring takes over to limit pow er dissipation of the circuit components under brow nout conditions). The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin. 3. The output of the voltage error amplifier, V EA. The gain modulator responds linearly to variations in V VEA . PFC Cycle-By-Cycle Current Limiter The output of the gain modulator is a current signal, in the form of a full w ave rectified sinusoid at tw ice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this w ay, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the pow er line. The general In addition to being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is less than -1.15 V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC pow er cycle. www.onsemi.com 14 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Functional Description Error Amplifier Compensation To improve pow er supply reliability, reduce system component count, and simplify compliance to UL1950 safety standards; the FAN4800AS/CS/01S/02S includes TriFault DetectTM technology. This feature monitors FBPFC for certain PFC fault conditions. The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the tw o transconductance error amplifiers. Figure 26 show s the types of compensation netw orks most commonly used for In a feedback path failure, the output of the PFC could the voltage and current error amplifiers, along w ith their exceed safe operating limits. With such a failure, FBPFC respective return points. The current-loop compensation is exceeds its normal operating area. Should FBPFC go too returned to VREF to produce a soft-start characteristic on low , too high, or open; TriFault DetectTM senses the error the PFC. As the reference voltage increases from 0V, it and terminates the PFC output drive. creates a differentiated voltage on IEA, w hich prevents the TriFault Detect is an entirely internal circuit. It requires no PFC from immediately demanding a full duty cycle on its boost converter. Complete design is discussed in external components to serve its protective function. application note AN-6078SC. PFC Over-Voltage Protection There is an RC filter betw een Rsense and ISENSE pin. There In the FAN4800AS/CS/01S/02S, the PFC OVP comparator are tw o reasons to add a filter at the ISENSE pin: serves to protect the pow er circuit from being subjected to excessive voltages if the load changes suddenly. A 1. Protection: During startup or inrush current conditions, there is a large voltage across Rsense, the sensing resistor divider from the high-voltage DC output of the PFC resistor of the PFC boost converter. It requires the ISENSE is fed to FBPFC. When the voltage on FBPFC exceeds filter to attenuate the energy. 2.75 V, the PFC output driver is shut dow n. The PWM section continues to operate. The OVP comparator has 2. To reduce inductance, L, the boost inductor. The I SENSE 250 mV of hysteresis and the PFC does not restart until the filter also can reduce the boost inductor value since the voltage at FBPFC drops below 2.5 V. V DD OVP can also ISENSE filter behaves like an integrator before the ISENSE serve as a redundant PFC OVP protection. V DD OVP pin, w hich is the input of the current error amplifier, IEA. threshold is 28 V w ith 1 V hysteresis. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is betw een 100 and 50 because IOFFSET x Selecting PFC Rsense RFILT ER can generate a negative offset voltage of IEA. Rsense is the sensing resistor of the PFC boost converter. Selecting an R FILT ER equal to 50 keeps the offset of the During the steady state, line input current x Rsense equals IEA less than 3 mV. Design the pole of the I SENSE filter at IGAINMOD x 5.7 k. f PFC/6, one sixth of the PFC sw itching frequency, so the At full load, the average V VEA needs to around 4.5 V and boost inductor can be reduced six times w ithout disturbing ripple on the VEA pin needs to be less than 400 mV. the stability. The capacitor of the ISENSE filter, CFILT ER, is approximately 100 nF. Choose the resistance of the sensing resistor: RSENSE 4.5 0.7 5.7K IAC Gain VIN 2 5.6 0.7 Line _ Input _ Power 2 VREF (2) CV2 CI2 w here 5.6 is V VEA maximum output voltage. CV1 CI1 RV1 PFC Output PFC Soft-Start PFC startup is controlled by V VEA level. Before the FBPFC voltage reaches 2.4 V, the V VEA level is around 2.8 V. At 90 V AC, the PFC soft-start time is 90 ms. PFC Brownout VEA The AC UVP comparator monitors the AC input voltage. The PFC is disabled as AC input low ers, causing V RMS to be less than 1.05 V. GMv Rmul 1 GMi 15 2.5V RF2 RSENSE IEA 16 RF1 FBPFC RI1 IAC 2 VRMS 4 RFILTER ISENSE 3 Gain Modulator IMO V(t) Rmul CFILTER Figure 26. Com pensation Netw ork Connection for the Voltage and Current Error Am plifiers www.onsemi.com 15 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination TriFault DetectTM To improve the efficiency, the system can reduce PFC sw itching loss at low line and light load by reducing the PFC output voltage. The tw o-level PFC output of the FAN4801S/02S can be programmable. As Figure 27 show s, FAN4801S/02S detect the voltage of VEA and VRMS pins to determine if the system operates low line and light load. At the second-level PFC, there is a current of 20 A through RF2 from the FBPFC pin. The second-level PFC output voltage can be calculated as. Output RF1 RF 2 2.5V 20 A RF 2 RF 2 (3) For example, if the second-level PFC output voltage is expected as 300 V and normal voltage is 387 V, according to the equation, RF2 is 28 k RF1 is 4.3 M. The programmable range of second level PFC output voltage is 340 V ~ 300 V. VEA PFC Output 16 VDD RF1 20A FBPFC gmv 15 2.5V RF2 Pulse Width Modulator (PWM) The operation of the PWM section is straightforw ard, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM w ith the PFC section of the device, from w hich it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In current-mode applications, the PWM ramp (RAMP) is usually derived directly from a current-sensing resistor or current transformer in the primary side of the output stage. It is thereby representative of the current flow ing in the converter's output stage. ILIMIT , w hich provides cycle-by-cycle current limiting, is typically connected to RAMP in such applications. For voltage-mode operation and certain specialized applications, RAMP can be connected to a separate RC timing netw ork to generate a voltage ramp against w hich FBPWM is compared. Under these conditions, the use of voltage feedforw ard from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the ILIMIT input is used for output stage over-current protection. No voltage error amplifier is included in the PWM stage, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM's RAMP input that allow s FBPWM to command a 0% duty cycle for input voltages below typical 1.5 V. Range Figure 27. PWM Cycle-by-Cycle Current Limiter 4 VRMS Tw o-Level PFC Schem e Oscillator (RT/CT) The oscillator frequency is determined by the values of RT and CT , w hich determine the ramp and off-time of the oscillator output clock: fRT / CT 1 tRT / CT tDEAD (4) The dead time of the oscillator is derived from the follow ing equation: VREF 1 tRT / CT CT RT ln VREF 3.8 at V REF=7.5 V and tRT /CT =CT x RT x 0.56. (5) 2.8V tDEAD CT 360 CT (6) 7.78mA The dead time is so small (tRT /CT >>tDEAD) that the operating frequency can typically be approximated by: 1 tRT / CT VIN OK Comparator The V IN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on FBPFC is less than its nominal 2.4 V. Once the voltage reaches 2.4 V, w hich corresponds to the PFC output capacitor being charged to its rated boost voltage, soft-start begins. PWM Soft-Start (SS) The dead time of the oscillator is determined using: fRT / CT The ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin exceed 1 V, the output flip-flop is reset by the clock pulse at the start of the next PWM pow er cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle current, it limits the PWM duty cycle mode and the pow er dissipation is reduced during the dead-short condition. PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 10 A supplies the charging current for the capacitor and startup of the PWM begins at 1.5 V. (7) www.onsemi.com 16 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Two-Level PFC Function Leading/Trailing Edge Modulation When the PWM section is used in current mode, RAMP is generally used as the sampling point for a voltage, representing the current in the primary of the PWM's output transformer. The voltage is derived either from a current-sensing resistor or a current transformer. In voltage mode, RAMP is the input for a ramp voltage generated by a second set of timing components (RRAMP , CRAMP ) that have a minimum value of 0V and a peak value of approximately 6 V. In voltage mode, feedforw ard from the PFC output bus is an excellent w ay to derive the timing ramp for the PWM stage. Conventional PWM techniques employ trailing-edge modulation, in w hich the sw itch turns on right after the trailing edge of the system clock. The error amplifier output is then compared w ith the modulating ramp up. The effective duty cycle of the trailing-edge modulation is determined during the on-time of the sw itch. Generating VDD In the case of leading-edge modulation, the sw itch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the sw itch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off -time of the sw itch. After turning on the FAN4800AS/CS/01S/02S at 11 V, the operating voltage can vary from 9.3 V to 28 V. The threshold voltage of the V DD OVP comparator is 28 V and its hysteresis is 1 V. When V DD reaches 28 V, OPFC is LOW and the PWM section is not disturbed. There are tw o w ays to generate V DD: use auxiliary pow er supply around 15 V or use bootstrap w inding to self -bias the FAN4800AS/CS/01S/02S system. The bootstrap w inding can be taped from the PFC boost choke or the transformer of the DC-to-DC stage. www.onsemi.com 17 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination PWM Control (RAMP) 19.69 18.67 9 16 7.11 6.10 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 8.25 7.62 1.78 1.14 0.28 0.20 4.95 2.92 3.81 2.92 2.54 0.56 0.36 10.92 0.25 C SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV2 Figure 28. 16-Pin, Dual In-Line Package (DIP), JEDEC MS-001, .300" Wide Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 18 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Physical Dimensions FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination Physical Dimensions Figure 29. 16-Pin Sm all Outline Package (SOIC), JEDEC MS-012, .150", Narrow Body Package drawings are provided as a service to customers considering ON Semiconductor components. Draw ings may change in any manner without notice. Please note the revision and /or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 19 FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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