NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Speed Bins -BE* -CG/CGI* -DI/DII* -EJ* -FK* DDR3/L-1066-CL7 DDR3/L-1333-CL9 DDR3/L-1600-CL11 DDR3-1866-CL12 DDR3-2133-CL13 Units tCK Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Clock Frequency 300 533 300 667 300 800 300 933 300 1066 MHz 13.125 - 13.125 - 13.125 - 12.84 - 12.155 - ns 13.125 - 13.125 - 13.125 - 12.84 - 12.155 - ns 50.625 - 49.5 - 48.75 - 47.08 - 45.155 - ns 37.5 70K 36 70K 35 70K 34 70K 33 70K ns tCK(Avg.)@CL5 3.0 3.3 3.0 3.3 3.0 3.3 tCK(Avg.)@CL6 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns tCK(Avg.)@CL7 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 ns tCK(Avg.)@CL8 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 ns tCK(Avg.)@CL9 1.5 1.875 1.5 1.875 1.5 1.875 1.5 1.875 ns tCK(Avg.)@CL10 1.5 1.875 1.5 1.875 1.5 1.875 1.5 1.875 ns 1.25 1.5 1.25 1.5 1.25 1.5 ns tCK(Avg.)@CL12 1.07 1.25 1.07 1.25 ns tCK(Avg.)@CL13 1.07 1.25 0.935 1.25 ns 0.935 1.07 ns tCK(Avg.)@CL11 (Avg) ns tCK(Avg.)@CL14 *The timing specification of high speed bin is backward compatible with low speed bin REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Dynamic ODT (Rtt_Nom & Rtt_WR) 1.35V -0.0675V/+0.1V & 1.5V 0.075V 8 Internal memory banks (BA0- BA2) Differential clock input (CK, Programmable Automatic Self Refresh (ASR) ) Latency: 5, 6, 7, 8, 9, 10, 11, 12, Self refresh mode and Partial array self refresh Thermal sensor on die using MPR and 13 WRITE Latency (CWL): 5,6,7,8 and 9 POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock T case=95 (with 2X refresh); T case=85 (with 1X refresh) Programmable Sequential / Interleave Burst Type SSTL_15 JEDEC standard compatible Programmable Burst Length: 8, 4with Burst Chop inputs/outputs interface 8n-bit prefetch architecture RoHS compliance and Halogen free Output Driver Impedance Control Packages: Differential bidirectional data strobe 78-Balls BGA for x8 components Internal(self) calibration:Internal self calibration 96-Balls BGA for x16 components OCD Calibration Through ZQ pin (RZQ: 240 ohm1%) REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP The 4Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA packages. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP - ! "" # $%!& < TOP View> See the balls through the package x 8 1 2 3 8 9 VSS VDD NC A NU/ VSS VDD VSS VSSQ DQ0 B DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS C DQ1 DQ3 VSSQ VSSQ DQ6 D VDD VSS VSSQ VREFDQ VDDQ E DQ7 DQ5 VDDQ NC VSS F CK VSS NC ODT VDD G VDD CKE DQ4 NC 07/ 2012 H A10/AP ZQ NC A15 VREFCA VSS BA1 VDD VSS BA0 BA2 J VDD A3 A0 K A12/ VSS A5 A2 L A1 A4 VSS VDD A7 A9 M A11 A6 VDD A13 N A14 A8 VSS VSS REV 1.1 7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ' () "" # $*+)& < TOP View> See the balls through the package x 16 1 2 3 7 8 9 VDDQ DQU5 DQU7 A DQU4 VDDQ VSS VSSQ VDD VSS B DQU6 VSSQ VDDQ DQU3 DQU1 C DQSU DQU2 VDDQ VSSQ VDDQ DMU D DQU0 VSSQ VDD VSS VSSQ DQL0 E DML VSSQ VDDQ VDDQ DQL2 DQSL F DQL1 DQL3 VSSQ VSSQ DQL6 G VDD VSS VSSQ VREFDQ VDDQ H DQL7 DQL5 VDDQ NC VSS J CK VSS NC ODT VDD K VDD CKE DQL4 NC 07/ 2012 A10/AP ZQ NC NC VREFCA VSS BA1 VDD VSS BA0 BA2 M VDD A3 A0 N A12/ VSS A5 A2 P A1 A4 VSS VDD A7 A9 R A11 A6 VDD A13 T A14 A8 VSS VSS REV 1.1 L CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , -. " Symbol Type CK, Input Function Clock: CK and are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of . Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for CKE Input Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when Input is registered high. external rank selection on systems with multiple memory ranks. provides for is considered part of the command code. , , Input Command Inputs: , and (along with ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM (DMU, DML) Input DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS / is enabled by Mode Register A11 setting in MR1 Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, BA[2:0] Input Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Auto-Precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write A10 / AP Input operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Address Inputs: Provide the row address for Activate commands and the column A[15:0] Input address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/ have additional function as below.) The address inputs also provide the op-code during Mode Register Set commands. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Symbol Type A12/ Input Function Burst Chop: A12/ is sampled during Read and Write commands to determine if burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, ODT Input DM/TDQS, NU/ and (when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. Active Low Asynchronous Reset: Reset is active when Input when is HIGH. is LOW, and inactive must be HIGH during normal operation. is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V Input / Output Data Input/ Output: Bi-directional data bus. DQ Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQU, DQL, DQS, , DQSU, , Input / Output DQSU corresponds to the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential signals , , and , respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM DQSL, supports differential data strobe only and does not support single-ended. is applicable for 8 configuration only. When enabled via mode TDQS and TDQS, Output register A11 = 1 in MR1, DRAM will enable the same termination resistance function on TDQS, as is applied to DQS, . When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and is not used. NC - No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.35V -0.0675V/+0.1V or & 1.5V 0.075V VDD Supply Power Supply: 1.35V -0.0675V/+0.1V or & 1.5V 0.075V VSSQ Supply DQ Ground Vss Supply Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. Note: Input only pins (BA0-BA2, A0-A15, REV 1.1 07/ 2012 , , , , CKE, ODT, and ) do not supply termination. CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP // Configuration NT5CB512M8BN/NT5CC512M8BN NT5CB256M16BP/NT5CC256M16BP # of Bank 8 8 Bank Address BA0 - BA2 BA0 - BA2 Auto precharge A10 / AP A10 / AP A12 / A12 / Row Address A0 - A15 A0 - A14 Column Address A0 - A9 A0 - A9 Page size 1KB 2KB BL switch on the fly Note: Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: Page size = 2 COLBITS * ORG / 8 COLBITS = the number of column address bits ORG = the number of I/O (DQ) bits REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . / , Organization 0 Part Number Package Speed Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP 1.5V 512M x 8 256M x 16 Organization NT5CB512M8BN-CG 78-Ball WBGA 667 DDR3-1333 9-9-9 NT5CB512M8BN-DI 0.8mmx0.8mm Pitch 800 DDR3-1600 11-11-11 NT5CB256M16BP-CG 96-Ball WBGA 667 DDR3-1333 9-9-9 NT5CB256M16BP-DI 0.8mmx0.8mm Pitch 800 DDR3-1600 11-11-11 Part Number Package Speed Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP 1.35V 512M x 8 256M x 16 Organization NT5CC512M8BN-CG 78-Ball WBGA 667 DDR3L-1333 9-9-9 NT5CC512M8BN-DI 0.8mmx0.8mm Pitch 800 DDR3L-1600 11-11-11 NT5CC256M16BP-CG 96-Ball WBGA 667 DDR3L-1333 9-9-9 NT5CC256M16BP-DI 0.8mmx0.8mm Pitch 800 DDR3L-1600 11-11-11 Part Number Package Speed Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP 1.5V I-Temp 512M x 8 256M x 16 REV 1.1 07/ 2012 NT5CB512M8BN-CGI 78-Ball WBGA 667 DDR3-1333 9-9-9 NT5CB512M8BN-DII 0.8mmx0.8mm Pitch 800 DDR3-1600 11-11-11 NT5CB256M16BP-CGI 96-Ball WBGA 667 DDR3-1333 9-9-9 NT5CB256M16BP-DII 0.8mmx0.8mm Pitch 800 DDR3-1600 11-11-11 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 0 " / Power Applied 0 Power ON Reset Procedure From any State MRS, MPR, Write Levelizing Initialization ZQCL Self Refresh SRE MRS SRX RESET ZQ Calibration ZQCL ZQCS Idle REF Refreshing PDX ACT PDE Precharge Power Down Activating Active Power Down PDE PDX Bank Active Write Read Read Write Read Writing Reading Write Write A Automatic Sequence Read A Write A Read A Read A Write A Command Sequence PRE, PREA Writing PRE, PREA Reading PRE, PREA Precharging 0 Abbreviation ACT PRE PREA MRS REF ZQCL REV 1.1 07/ 2012 00 / Function Abbreviation Function Abbreviation Function Active Read RD, RDS4, RDS8 PDE Enter Power-down Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down Precharge All Write WR, WRS4, WRS8 SRE Self-Refresh entry Mode Register Set Write A WRA, WRAS4, WRAS8 SRX Self-Refresh exit Refresh Start RESET Procedure MPR Multi-Purpose Register ZQ Calibration Long ZQCS ZQ Calibration Short - CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " The DDR3(L) SDRAM B-Die is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a `chopped' burst of four in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A15 select the row). The address bit registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode `on the fly' (via A12) if enabled in the mode register. Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation. 1 12 4 /, , "3 / "3 The Following sequence is required for POWER UP and Initialization 1. Apply power ( is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). needs to be maintained for minimum 200 s with stable power. CKE is pulled "Low" anytime before being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts. - VDD and VDDQ are driven from a single power converter output, AND - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND - Vref tracks VDDQ/2. OR - Apply VDD without any slope reversal before or at the same time as VDDQ. - Apply VDDQ without any slope reversal before or at the same time as VTT & Vref. - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered "High" after Reset, CKE needs to be continuously registered "High" until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3(L) DRAM will keep its on-die termination in high impedance state as long as is asserted. Further, the DRAM keeps its on-die termination in high impedance state after de-assertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load mode register. [tXPR=max (tXS, 5tCK)] 6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide "Low" to BA0 and BA2, "High" to BA1) 7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide "Low" to BA2, "High" to BA0 and BA1) 8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and BA2) 9. Issue MRS Command to load MR0 with all application settings and "DLL reset". (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-BA2) 10. Issue ZQCL command to starting ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3(L) SDRAM is now ready for normal operation. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP /, "3 Ta Tb 4 Tc Td tCKSRX Te Tf 0 Tg Th $ 5/& Ti Tj Tk CK CK RESET 10ns tIS Valid CKE Static LOW in case RTT_Nom is enabled at time Tg , otherwise static HIGH or LOW ODT NOP* Command BA0-BA2 MRS MRS MRS MRS MR2 MR3 MR1 MR0 ZQCL Valid NOP* Valid Valid VDD, VDDQ tDLLK T=200us Do Not Care Time break / tMRD tXPR T=500us tMRD tMRD tMOD tZQinit. * From time point Td until Tk . NOP or DES commands must be applied between MRS and ZQcal commnads . " 4 $ 5/& The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled "Low" before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3(L) SDRAM is ready for normal operation. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / Ta 4 Tb " Tc Td tCKSRX / Te Tf Tg Th Ti Tj Tk CK CK RESET 10ns tIS Valid CKE Static LOW in case RTT _Nom is enabled at time Tg , otherwise static HIGH or LOW ODT NOP* Command BA0-BA2 MRS MRS MRS MRS MR2 MR3 MR1 MR0 ZQCL Valid NOP* Valid Valid VDD, VDDQ tDLLK T=100ns Do Not Care 00 tXPR T=500us Time break 6 tMRD tMRD tMRD tMOD tZQinit. * From time point Td until Tk . NOP or DES commands must be applied between MRS and ZQcal commnads . / For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3(L) SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers ( ) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean these commands can be executed any time after power-up without affecting the array contents. The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 20 CK CK CMD MRS NOP NOP NOP NOP MRS tMRD ADDR VAL VAL CKE Do not Care Time break The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following figure. . 20 CK CK CMD MRS NOP NOP NOP NOP Non MRS tMOD ADDR VAL VAL CKE VAL Old Setting 00 Updating Setting 6 / $ New Setting 5/& The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the functionality and/or modes. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / 7 The mode-register MR0 stores data for controlling various operating modes of DDR3(L) SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by asserting low on , , , , BA0, BA1, and BA2, while controlling the states of address pins according to the following figure. 7 Address Field * BA2 BA1 BA0 * A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length MRS mode BA 1 BA0 MRS mode 0 0 MR 0 0 1 MR 1 1 0 MR 2 1 1 MR 3 A1 A0 BL 0 0 8 ( Fixed) 0 1 BC 4 or 8 (on the fly) 1 0 BC 4 (Fixed) 1 1 Reserved Burst Type Precharge Power Down DLL Control for Precharge PD A 12 A3 Burst Type 0 Nibble Sequential 1 Interleave Slow Exit ( Low Power ) 0 Fast Exit( Normal) 1 CAS Latency Write recovery for autoprecharge A11 A10 A9 0 0 0 ** WR( cycles) Reserved 0 0 1 5 0 1 0 6 0 1 1 7 1 0 0 8 1 0 1 10 1 1 0 12 1 1 1 14 A6 A5 A4 A2 CAS Latency 0 0 0 0 Reserved 0 0 1 0 5 0 1 0 0 6 0 1 1 0 7 1 0 0 0 8 1 0 1 0 9 1 1 0 0 10 1 1 1 0 11 0 0 0 1 12 0 0 1 1 13 0 1 0 1 14 Mode DLL Reset A8 DLL Reset 0 NO 1 YES REV 1.1 07/ 2012 * BA 2 and A 14 are reserved for future use and must be set to 0 when programming the MR . ** WR(write recovery for autoprecharge )min in clock cycles is calculated by dividing tWR (ns ) by tCK (ns) and rounding up to the next integer : Wrmin[ cycles] =Roundup( tWR/ tCK).The value in the mode register must be programmed to be equal or larger than WRmin . The programmed WR value is used with tRP to determine tDAL. A7 Mode 0 Normal 1 TEST CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 682 8 /. / Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/ 2 Burst Length 4 Chop . / Read Write Read Write 8 Read . / Starting Column Address (A2,A1,A0) Burst type: Sequential (decimal) A3 = 0 Burst type: Interleaved (decimal) A3 = 1 Note 0 , 0 , 0 0,1,2,3,T,T,T,T 0,1,2,3,T,T,T,T 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 V 1,2,3,0,T,T,T,T 2,3,0,1,T,T,T,T 3,0,1,2,T,T,T,T 4,5,6,7,T,T,T,T 5,6,7,4,T,T,T,T 6,7,4,5,T,T,T,T 7,4,5,6,T,T,T,T 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 1,0,3,2,T,T,T,T 2,3,0,1,T,T,T,T 3,2,1,0,T,T,T,T 4,5,6,7,T,T,T,T 5,4,7,6,T,T,T,T 6,7,4,5,T,T,T,T 7,6,5,4,T,T,T,T 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7 , , , , , , , , , , , , , , , , , , 0 1 1 0 0 1 1 V V 0 0 1 1 0 0 1 1 V , , , , , , , , , , , , , , , , , , 1 0 1 0 1 0 1 V V 0 1 0 1 0 1 0 1 V 1,2,3 1,2,4,5 2 Write 2,4 Note: 1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/ , the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. 2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst. 3. T: Output driver for data and strobes are in high impedance. 4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. X: Do not Care. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. 2 / The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0 definition figure. Programming bit A7 to a `1' places the DDR3(L) SDRAM into a test mode that is only used by the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1. The DLL Reset bit is self-clearing, meaning it returns back to the value of `0' after the DLL reset function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous operations.) 9 : The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger than tWR (min). 6 MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or `slow-exit', the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12=1), or `fast-exit', the DLL is maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to the next valid command. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / + The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , , , high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure. + Address Field * BA 2 BA1 BA 0 * A14 A13 A12 A11 * A10 A9 * A8 A7 A6 A5 * A4 A3 A2 A1 A0 DLL Mode Register BA1 BA 0 MR 0 0 MR 0 0 1 MR 1 1 0 MR 2 1 1 MR 3 Output buffer enabled 1 Output buffer disabled 0 Enable 1 Disable A5 A1 D.I. C. 0 0 RZQ/ 6 0 1 RZQ/7 1 0 Reserved 1 1 Reserved Qoff ** 0 DLL Enable Output Driver Impedance Control Qoff A12 A0 Note: RZQ= 240 ohms TDQS A11 ODT value TDQS enable 0 Disabled 1 Enabled Rtt _ Nom*** A9 A 6 A 2 0 0 0 0 0 1 RZQ / 4 0 1 0 RZQ / 2 0 1 1 RZQ / 6 1 0 0 RZQ /12 1 0 1 RZQ / 8 1 1 0 Reserved 1 1 1 Reserved ODT Disable Write Levelization A7 Write leveling enable 0 Disabled 1 Enabled Additive Latency A4 A 3 0 0 0 1 CL - 1 1 0 CL - 2 1 1 Reserved REV 1.1 07/ 2012 AL 0 (AL disabled) **** **** * BA2 , A 5 , A 8 , A10 ,and A13 are reserved for future use and must be set to 0 when programming the MR . ** Outputs disabled DQs, DQSs, DQSs. *** In Write leveling Mode (MR1[bit 7]= 1) with MR1[ bit 12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode ( MR1 [ bit 7 ]= 1 ) with MR1[ bit 12]= 0, only RTT_ Nom settin gof RZQ /2 ,RZQ /4,and RZQ / 6 are allowed. **** If RTT_ Nom is used during Writes , only the values RZQ/ 2 ,RZQ/4,RZQ/6 are allowed. CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1 "- " The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3(L) SDRAM does not require DLL for any Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation in DLL-off Mode. The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0, 0}, to disable Dynamic ODT externally. . : ,0 / " The output driver impedance of the DDR3(L) SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1 definition figure. . 2 ; " DDR3(L) SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. // : $ & Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L) SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register options are shown as the following table. // : REV 1.1 07/ 2012 $ & A4 A3 AL 0 0 0, (AL Disable) 0 1 CL-1 1 0 CL-2 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1 9 1 Reserved ": " For better signal integrity, DDR3(L) memory module adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support `write leveling' in DDR3(L) SDRAM to compensate for skew. . " The DDR3(L) SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is enabled (A12=1) all output pins (DQs, DQS, , etc.) are disconnected from the device removing any loading of the output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should be set to `0'. TDQS, TDQS (Termination Data Strobe) is a feature of x8 DDR3(L) SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. When enabled via the mode register, the same termination resistance function is applied to be TDQS/ applied to the DQS/ pins that are pins. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided and the pin is not used. The TDQS function is available in x8 DDR3(L) SDRAM only. TDQS, * MR1 (A11) DM / TDQS NU / TDQS 0 (TDQS Disabled) DM Hi-Z 1 (TDQS Enabled) TDQS Note: 1. If TDQS is enabled, the DM function is disabled. 2. When not used, TDQS function can be disabled to save termination power. 3. TDQS function is only available for x8 DRAM. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / < The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on , , , high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the table below. < Address Field * BA 2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 PASR MRS mode BA1 BA0 0 A0 A2 A1 A0 PAS R 0 0 0 Full Array 0 0 1 Half Array (000 ,001,010 ,011 ) 0 1 0 Quarter Array (000 , 001) 0 1 1 1/ 8 Array (000 ) 1 0 0 3 / 4 array ( 010 , 011 ,100 ,101 , 110, 111) 1 0 1 Half array ( 100 , 101 , 110 , 111 ) 1 1 0 Quarter array ( 110 ,111 ) 1 1 1 1/8th array ( 111 ) MRS mode 0 MR 0 0 1 MR 1 1 0 MR 2 1 1 MR3 ** Rtt _ WR A10 A9 0 0 0 1 RZQ / 4 1 0 RZQ / 2 1 1 Reserve d Rtt _ WR Dynamic ODT off (Write does not affect RTT value) th CAS WriteLatency Sel f - Refresh Temperature Range A5 A4 A3 0 0 0 0 0 1 6 ( 2 . 5n s>tCK( avg)>=1. 875ns) 0 1 0 7 (1. 875ns> tCK(avg)>=1. 5ns) 0 1 1 8 (1. 5ns > tCK(avg)>=1. 25ns) 1 0 0 9 (1 .25ns > tCK(avg)>=1.07ns) ASR 1 0 1 0 Manual Self Refresh Reference 1 1 0 Reserved 1 ASR Enable 1 1 1 Reserved A7 0 Normal Operating temperature range 1 Extended operating temperature range Auto SelfRefresh A6 CAS Write Latency SRT 5 (tCK(avg) >=2.5 ns ) 10(1.07ns>tCK(avg)>=0.935ns) * BA 2 , A5 , A8 , A 11- A 14 are reserved for future use and must be set to0 when programming the MR. _ * * The Rtt_WR value can be applied during writes even when Rtt Nom is disabled . During write leveling,Dynamic ODT is not available . REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 9 $9 & The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3(L) DRAM does not support any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL. For more information on the supported CWL and AL settings based on the operating clock frequency, refer to "Standard Speed Bins" on page112. For detailed Write operation refer to "WRITE Operation" on page 40. " 6$ & / " 62 0 $ 2& DDR3(L) SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately. Optional in DDR3(L) SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3(L) SDRAM devices support the following options or requirements referred to in this material. For more details refer to "Extended Temperature Usage" on page 40. DDR3(L) SDRAMs must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional ASR function or program the SRT bit appropriately. 0 . 2$ =9 & DDR3(L) SDRAM introduces a new feature "Dynamic ODT". In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. DDR3(L) SDRAM introduces a new feature "Dynamic ODT". In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to "Dynamic ODT" on page 68. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , , , high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below. Address Field BA 2 B A1 BA 0 A14 A13 A12 A 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 MPR Location MRS mode BA1 B A 0 MRS mode 0 0 MR 0 0 1 MR1 1 0 MR2 1 1 MR3 A0 A1 A0 0 0 Predefined Pattern 0 1 RFU 1 0 RFU 1 1 RFU MPR Location MPR A2 MPR 0 Normal Operation 1 Dataflow fromMPR REV 1.1 07/ 2012 Note : BA2, A3- A 15 are reserved for future use and mustbe set to 0 when programming theMRS . CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " $ & The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. " # 0 To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, as following Table 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown on page 27. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP MR3 A[2] MR3 A[1:0] MPR MPR-Loc Function Normal operation, no MPR transaction. 0b don't care (0b or 1b) All subsequent Reads will come from DRAM array. All subsequent Write will go to DRAM array. 1b See the page 27 Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. MPR Functional Description *One bit wide logical interface via all DQ pins during READ operation. *Register Read on x8: *DQL[0] and DQU[0] drive information from MPR. *DQL[7:1] either drive the same information as DQ[0], or they drive 0b.. *Addressing during for Multi Purpose Register reads for all MPR agents: *BA [2:0]: don't care *A[1:0]: A[1:0] must be equal to `00'b. Data read burst order in nibble is fixed *A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *) *A[9:3]: don't care *A10/AP: don't care *A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0. *A11, A13... (if available): don't care *Regular interface functionality during register reads: *Support two Burst Ordering which are switched with A2 and A[1:0]=00b. *Support of read burst chop (MRS and on-the-fly via A12/BC) *All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3(L) SDRAM. *Regular read latencies and AC timings apply. *DLL must be locked prior to MPR Reads. NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP MR3 A[2] 1b MR3 A[1:0] 00b Function Read Predefined Read Address Burst Order A[2:0] and Data Pattern Burst Length BL8 000b Pattern for System Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Calibration BC4 000b Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] BC4 100b Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] 1b 1b 1b 01b 10b 11b RFU RFU RFU BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP $& 00 00 /2 62 / /. " CKE Function BA0- A13- A12- A10- A0-9, NOTES Abbreviation Previous Current Cycle Cycle Mode Register Set MRS H H L L L L BA Refresh REF H H L L L H V V V V V Self Refresh Entry SRE H L L L L H V V V V V Self Refresh Exit SRX L H H X X X X X X X X L H H H V V V V V Single Bank Precharge PRE H H L L H L BA V V L V PREA H H L L H L V V V H V Bank Activate ACT H H L L H H BA Write (Fixed BL8 or BC4) WR H H L H L L BA RFU V L CA Write (BC4, on the Fly) WRS4 H H L H L L BA RFU L L CA Write (BL8, on the Fly) WRS8 H H L H L L BA RFU H L CA Write with Auto Precharge (Fixed BL8 or BC4) WRA H H L H L L BA RFU V H CA Write with Auto Precharge (BC4, on the Fly) WRAS4 H H L H L L BA RFU L H CA Write with Auto Precharge (BL8, on the Fly) WRAS8 H H L H L L BA RFU H H CA RD H H L H L H BA RFU V L CA Read (BC4, on the Fly RDS4 H H L H L H BA RFU L L CA Read (BL8, on the Fly) RDS8 H H L H L H BA RFU H L CA Read with Auto Precharge (Fixed BL8 or BC4) RDA H H L H L H BA RFU V H CA Read with Auto Precharge (BC4, on the Fly) RDAS4 H H L H L H BA RFU L H CA Read with Auto Precharge (BL8, on the Fly) RDAS8 H H L H L H BA RFU H H CA No Operation NOP H H L H H H V V V V V 10 Device Deselected DES H H H X X X X X X X X 11 Power Down Entry PDE H L L H H H V V V V V H X X X X X X X X Power Down Exit PDX L H L H H H V V V V V H X X X X X X X X ZQ Calibration Long ZQCL H H L H H L X X X H X ZQ Calibration Short ZQCS H H L H H L X X X L X Precharge all Banks Read (Fixed BL8 or BC4) REV 1.1 07/ 2012 OP Code 7,9,12 7,8,9,12 Row Address (RA) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved 6,12 6,12 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Command Truth Table (Conti.) NOTE1. All DDR3(L) SDRAM commands are defined by states of , , , and CKE at the rising edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant. NOTE2. is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function. NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. NOTE4. "V" means "H or L (but a defined logic level)" and "X" means either "defined or undefined (like floating) logic level". NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS. NOTE6. The Power-Down Mode does not perform any refresh operation. NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. NOTE8. Self Refresh Exit is asynchronous. NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. NOTE10. The No Operation command should be used in cases when the DDR3(L) SDRAM is in an idle or wait state. The purpose of the No Operation command (NOP) is to prevent the DDR3(L) SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. NOTE11. The Deselect command performs the same function as No Operation command. NOTE12. Refer to the CKE Truth Table for more detail with CKE transition. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP >1 2 62 " CKE Current State Previous Current Cycle Cycle (N-1) (N) L L L Command (N) Action (N) Notes X Maintain Power-Down 14,15 H DESELECT or NOP Power-Down Exit 11,14 L L X Maintain Self-Refresh 15,16 L H DESELECT or NOP Self-Refresh Exit 8,12,16 Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 11,13,14 Reading H L DESELECT or NOP Power-Down Entry 11,13,14,17 Writing H L DESELECT or NOP Power-Down Entry 11,13,14,17 Precharging H L DESELECT or NOP Power-Down Entry 11,13,14,17 Refreshing H L DESELECT or NOP Precharge Power-Down Entry 11 H L DESELECT or NOP Precharge Power-Down Entry 11,13,14,18 H L REFRESH Self-Refresh 9,13,18 Power-Down Self-Refresh All Banks Idle , , , NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. NOTE 2 Current state is defined as the state of the DDR3(L) SDRAM immediately prior to clock edge N. NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here. NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh. NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH. NOTE 7 DESELECT and NOP are defined in the Command Truth Table. NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied. NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state. NOTE 10 Must be a legal command as defined in the Command Truth Table. NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only. NOTE 13 Self-Refresh cannot be entered during Read or Write operations. NOTE 14 The Power-Down does not perform any refresh operations. NOTE 15 "X" means "don't care"(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins. NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation. NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-Down is entered. NOTE 18 `Idle state' is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc). REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ? . $?. & 00 / The No operation (NOP) command is used to instruct the selected DDR3(L) SDRAM to perform a NOP ( , and low and , high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. " 00 The Deselect function ( / HIGH) prevents new commands from being executed by the DDR3(L) SDRAM. The DDR3(L) SDRAM is effectively deselected. Operations already in progress are not affected. . / DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to "1"; this will disable the DLL for subsequent operations until A0 bit set back to "0". The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode operations listed below are an optional feature for DDR3(L). The maximum clock frequency for DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8) REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 0 / 1 T0 20 T1 . T2 T3 T4 T5 T6 T7 T8 T9 CK CK CMD Address READ Bank, Col b RL = AL+CL = 6 (CL=6, AL=0) DQSdiff_DLL_on Din b DQ_DLL_on RL(DLL_off) = AL+(CL-1) = 5 Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tDQSCKDLL_diff_min DQSdiff_DLL_off Din b DQ_DLL_off Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Din b+3 Din b+4 Din b+5 Din b+6 DQSdiff_DLL_off tDQSCKDLL_diff_max Din b DQ_DLL_off Din b+1 Din b+2 Din b+7 Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and REV 1.1 07/ 2012 signals will still be tDQSQ. CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP - 4 6 / DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to "1"; this will disable the DLL for subsequent operation until A0 bit set back to "0". @ A @ A / To switch from DLL "on" to DLL "off" requires the frequency to be changed during Self-Refresh outlined in the following procedure: Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, 1. must be in high impedance state before MRS to MR1 to disable the DLL). 2. Set MR1 Bit A0 to "1" to disable the DLL. 3. Wait tMOD. 4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with "Input Clock Frequency Change" section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be 8. necessary. A ZQCL command may also be issued after tXS). Wait for tMOD, and then DRAM is ready for next command. 9. 4 6 T0 0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 SRX 6) NOP Te 0 Te1 Tf0 CK CK tMOD CMD 1) MRS 2) NOP tCKSRE SRE 3) 4) tCKSRX 5) NOP tXS tMOD MRS 7) NOP Valid 8) tCKESR CKE Valid 8) ODT Valid 8) Time break Do not Care Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting with Idle State, RTT in Hi-Z State. 2) Disable DLL by setting MR1 Bit A0 to 1. 3) Enter SR. 4) Change Frequency. 5) Clock must be stable at least tCKSRX. 6) Exit SR. 7) Update Mode registers with DLL off parameters setting. 8) Any valid command. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP @ A @ A / To switch from DLL "off" to DLL "on" (with requires frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered). 2. Enter Self Refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with "Input clock frequency change" section. 4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 6. Wait tXS, then set MR1 Bit A0 to "0" to enable the DLL. 7. Wait tMRD, then set MR0 Bit A8 to "1" to start DLL Reset. 8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK). 9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. 4 6 0 T0 Ta 0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf1 Tg0 Th0 SRX 5) MRS 6) MRS 7) MRS 8) Valid CK CK CMD 1) NOP SRE 2) ODTLoff + 1tck NOP tCKSRE 3) tCKSRX 4) tXS tMRD tMRD CKE tDLLK Valid tCKESR ODT Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting from Idle State. 2) Enter SR. 3) Change Frequency. 4) Clock must be stable at least tCKSRX. 5) Exit SR. 6) Set DLL-on by MR1 A0="0" 7) Start DLL Reset 8) Any valid command REV 1.1 07/ 2012 Time break Do not Care CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , " # 6 Once the DDR3(L) SDRAM is initialized, the DDR3(L) SDRAM requires the clock to be "stable" during almost all states of normal operation. This means once the clock frequency has been set and is to be in the "stable state", the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3(L) SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has been satisfied, the state of the clock becomes a don't care. Once a don't care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole purpose of changing the clock frequency. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. The second condition is when the DDR3(L) SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency may change. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 6 / 6 4 / 4 Tc0 Tc1 Previous Clock Frequency T0 T1 T2 New Clock Frequency Ta0 Tb0 tCK CK tCKb tCHb tCLb Td0 Td1 Te0 Te1 NOP MRS NOP Valid CK tCH tCL tCKSRE tCKSRX CKE tIH tIS tIH tCPDED tIS tCKE Command NOP NOP NOP NOP DLL Reset Address ODT tAOFPD/tAOF Valid tXP tIH DQS, DQS High-Z DQ High-Z tIS tDLLK DM Enter Precharge Power-Down mode Frequency Change Exit Precharge Power-Down mode NOTES: 1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down 2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements 3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 9 :" For better signal integrity, DDR3(L) memory adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support "write leveling" in DDR3(L) SDRAM to compensate the skew. The memory controller can use the "write leveling" feature and feedback from the DDR3(L) SDRAM to adjust the DQS to CK - relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - to align the rising edge of DQS - with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - , sampled with the rising edge of DQS transition from 0 to 1 is detected. The DQS - , through the DQ bus. The controller repeatedly delays DQS - until a delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS- signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in "AC Timing Parameters" section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is show as below figure. 9 :" Diff _ CK Source Diff _ DQS Diff _ CK Destination Diff _ DQS DQ 0 or 1 0 0 Push DQS to capture 0 -1 transition DQ DQS/ 0 or 1 1 1 driven by the controller during leveling mode must be determined by the DRAM based on ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations. Therefore, a separate feedback mechanism should be able for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS (diff_LDQS) to clock relationship. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 4 ": " / 0 6 0 / DRAM enters into Write leveling mode if A7 in MR1 set "High" and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set "Low". Note that in write leveling mode, only DQS/ terminations are activated and deactivated via ODT pin not like normal operation. : ": / 6 ": " Function / MR1 Enable Disable Write leveling enable A7 1 0 Output buffer mode (Qoff) A12 0 1 0 6 ": " ODT pin at DRAM DQS/ 0 / termination DQs termination De-asserted off off Asserted on off Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are allowed. / Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, DRAM to sample CK - DRAM samples CK - edge which is used by the driven from controller. tWLMRD (max) timing is controller dependent. status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - delay setting and launches the next DQS/ transition is detected, the controller locks DQS - pulse after some time, which is controller dependent. Once a 0 to 1 delay setting and write leveling is achieved for the device. The following figure describes the timing diagram and parameters for the overall Write leveling procedure. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 20 / DQS - " 9 ": " is capturing CK - low at T1 and CK - high at T2 T1 tWLS T2 t WLH tWLS t WLH CK CK M RS CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT t DQSL tWLDQSEN tDQSH tDQSL tDQSH Di ff_ DQS tWLMR D On e Pri me DQ: tWLO t WLO Prime DQ t WLO Late Re ma ini ng DQs Earl y Re ma ini ng DQs tWLO All DQs are Prime : tWLMRD tWLOE t WLO Late Re ma ini ng DQs tWLO t WLOE Earl y Re ma ini ng DQs tWLO tWLOE t WLO Undefined Driving Mode Note: 1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out the leveling procedure. 2. MRS: Load MR1 to enter write leveling mode 3. NOP: NOP or deselect 4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS is shown with solid line, is shown with dotted line. 6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. 9 :" Time break Do not Care / 1* The following sequence describes how Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0). 3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1). REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 20 / " 9 : " * Extended Temperature Usage T0 T1 NOP NOP T2 Ta0 Tb0 Tc0 Tc1 NOP NOP Tc2 Td0 Td1 Te0 Te1 NOP Valid NOP Valid CK CK CMD NOP NOP NOP MRS tMOD MR1 BA Valid Valid tMRD ODT tIS tWLO tODTLoff tAOFmin RTT _Nom RTT_DQS_DQS tAOFmax DQS_DQS DQ Result = 1 Time Break Transitioning Do not Care Undefined Driving Mode Nanya's DDR3(L) SDRAM supports the optional extended temperature range of 0C to +95C, TC. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above +85C (and does not exceed +95C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85C or self refresh cannot be used until the case temperature is at or below +85C. Table 14 summarizes the two extended temperature options and Table 15 summarizes how the two extended temperature options relate to one another / Field Bits Description Auto Self-Refresh (ASR) When enabled, DDR3(L) SDRAM automatically provides Self-Refresh power management ASR MR2(A6) functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation. 0 = Manual SR Reference (SRT) 1 = ASR enable Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh SRT MR2(A7) operation. If ASR = 1, SRT bit must be set to 0. 0 = Normal operating temperature range 1 = Extended operating temperature range REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " 60 / 0 / DDR3(L) SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. " 62 0 2 SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details. " 60 / 00 Allowed Operating MR2 MR2 A[6] A[7] Self-Refresh operation Temperature Range for Self-Refresh mode 0 0 Self-Refresh rate appropriate for the Normal Temperature Range Normal (0 ~ 85C) Self-Refresh appropriate for either the Normal or Extended Temperature 0 1 Ranges. The DRAM must support Extended Temperature Range. The value of Normal and Extended the SRT bit can effect self-refresh power consumption, please refer to the IDD (0 ~ 95C) table for details. 1 0 1 0 1 1 REV 1.1 07/ 2012 ASR enabled (for devices supporting ASR and Normal Temperature Range). Self-Refresh power consumption is temperature dependent. Normal (0 ~ 85C) ASR enabled (for devices supporting ASR and Extended Temperature Range). Normal and Extended Self-Refresh power consumption is temperature dependent. (0 ~ 95C) Illegal CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP MR3 A[2] 0 1 MR3 A[1:0] don't care (0 or 1) See the following table Function Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Writes will go to DRAM array. Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. " One bit wide logical interface via all DQ pins during READ operation. Register Read on x8: DQ [0] drives information from MPR. DQ [7:1] either drive the same information as DQ [0], or they drive 0. Addressing during for Multi Purpose Register reads for all MPR agents: BA [2:0]: don't care. A [1:0]: A [1:0] must be equal to "00". Data read burst order in nibble is fixed. A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *) A [9:3]: don't care. A10/AP: don't care. A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0 A11, A13: don't care. Regular interface functionality during register reads: Support two Burst Ordering which are switched with A2 and A[1:0]=00. Support of read burst chop (MRS and on-the-fly via A12/BC). All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the DDR3(L) SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR READs. Note *): Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP // The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read. MR3 A[2] MR3 A[1:0] Function Read Burst Length Read Address A[2:0] 00 Pattern for 000 BC4 000 BC4 100 BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 System Calibration 1 1 1 01 10 11 RFU RFU RFU Burst order 0,1,2,3,4,5,6,7 BL8 Predefined 1 Burst Order and Data Pattern Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 2,;1 00 / The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A15 selects the row. These rows remain active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. 1 B 1 00 / The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1 . / . During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12=0, BC4 (BC4 = burst chop, tCCD=4) A12=1, BL8 A12 will be used only for burst length control, not a column address. / . 1 CD $ C78 CD8 C!& . T0 C ( $ C 8 CD8 C!& T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T145 NOP NOP NOP NOP CK CK CMD READ Address Bank Col n NOP NOP AL = 4 tRPRE DQS, DQS CL=5 DQ RL = AL + CL REV 1.1 07/ 2012 Dout n Dout n +1 Dout n +2 Dout n +3 Dout n +4 Dout n +5 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1 20 Read timing is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, tDQSCK is the actual position of a rising strobe edge relative to CK, tQSH describes the DQS, . . differential output high time. tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: tQSL describes the DQS, differential output low time. tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. /2 0 C K C K tD Q S K , m in tD Q S K , m a x R is in g S tr o b e R e g io n tD Q S K R is in g S tr o b e R e g io n tQ S H tQ S L tD Q S K D Q S D Q S tQ H tD Q S Q tQ H tD Q S Q A s s o c ia te d D Q p in s REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP /2 0 E " # " 6 Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and tDQSCK is the actual position of a rising strobe edge relative to CK and . . tQSH describes the data strobe high pulse width. Falling data strobe edge parameters: tQSL describes the data strobe low pulse width. " # " 6 RL M easured to this point CK CK tLZ(DQS)min tDQSCKmin tQSH tRPRE tQSL tRPST tHZ(DQS)min DQS, DQS Early Strobe tHZ(DQS)max tDQSCKmax tLZ(DQS)max tRPST DQS, DQS Late Strobe tRPRE NOTES: 1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe edge can vary between tDQSCK(min) and tDQSCK(max). 2. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by tQSL. 3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are not tied to tDQSCKmax (late strobe case). 4. The minimum pulse width of read preamble is defined by tRPRE(min). 5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side. 6. The minimum pulse width of read postamble is defined by tRPST(min). 7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP /2 0 E " 6 The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked. Rising data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined " T0 6 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 NOP NOP CK CK CMD READ Address Bank Col n NOP tRPRE NOP tDQSQmax tQH tRPST DQS, DQS tLZ(DQ)min RL = AL + CL DQ (Last data valid) DQ (First data no longer valid) tDQSQmin Dout n Dout n Dout n +1 Dout n +1 tHZ(DQ)min tQH Dout n +2 Dout n +2 Dout n +3 Dout n +3 Dout n +4 Dout n +4 Dout n +5 Dout n +5 Dout n +6 Dout n +6 Dout n +7 Dout n +7 All DQ collectively Valid data REV 1.1 07/ 2012 Valid data CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK Col n Bank READ Col n Bank READ T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Col b Bank READ Col b Bank READ T4 tRPRE tRPRE NOP NOP T5 Dout n +1 n n +1 n Dout Dout Dout NOP NOP T6 n +2 Dout NOP tRPST n +3 Dout n +3 Dout RL = 5 n +2 Dout RL = 5 NOP T7 n +5 Dout n +6 Dout n +7 Dout NOP T9 tRPRE NOP READ (BL4) to READ (BL4) NOP READ (BL8) to READ (BL8) n +4 Dout NOP T8 b Dout b Dout b +1 Dout b +1 Dout NOP NOP T10 b +2 Dout b +2 Dout NOP b +3 Dout tRPST b +3 Dout NOP T11 b +4 Dout b +5 Dout NOP NOP T12 b +6 Dout b +7 Dout NOP tRPST NOP T13 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Read to Read (CL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK NOP T4 tRPRE NOP T5 Col n Bank READ NOP NOP READ RL = 5 READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL NOP RL = 5 Col b Bank WRITE tRPRE READ to Write Command delay = RL +tCCD + 2tCK -WL NOP Dout n +1 n n +1 n Dout Dout Dout NOP n +2 Dout n +3 Dout n +5 Dout n +6 Dout n +7 Dout WL = 5 tRPST NOP T9 NOP tWPRE Dout b +1 Dout b NOP READ (BL8) to WRITE (BL8) n +4 Dout NOP T8 READ (BL4) to WRITE (BL4) NOP NOP T7 tRPST n +3 Dout WL = 5 n +2 Dout WRITE T6 Bank NOP T3 Col b NOP T2 Bank NOP T1 Col n READ T0 b +2 Dout NOP NOP T10 NOP b +3 Dout b Dout tBL = 4 clocks tWPST tWRPRE NOP T11 b +1 Dout NOP b +2 Dout NOP T12 b +3 Dout NOP b +4 Dout NOP T13 b +5 Dout NOP b +6 Dout NOP T14 tWTR tWR b +7 Dout NOP tWPST NOP T15 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK Col n Bank READ Col n Bank READ T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Col b Bank READ Col b Bank READ T4 tRPRE tRPRE NOP NOP T5 n n +1 Dout n +1 n Dout Dout Dout NOP NOP T6 n +2 Dout NOP tRPST n +3 Dout n +3 Dout RL = 5 n +2 Dout RL = 5 NOP T7 n +5 Dout n +6 Dout n +7 Dout NOP T9 tRPRE NOP READ (BC4) to READ (BL8) NOP READ (BL8) to READ (BC4) n +4 Dout NOP T8 b Dout b Dout b +1 Dout b +1 Dout NOP NOP T10 b +2 Dout b +2 Dout b +3 Dout b +3 Dout NOP tRPST NOP T11 b +4 Dout b +5 Dout NOP NOP T12 b +6 Dout b +7 Dout tRPST NOP NOP T13 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP READ to READ (CL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK Col n Bank READ Col n Bank READ T0 NOP T3 READ NOP T4 tRPRE NOP RL = 5 NOP READ RL = 5 Col b Bank WRITE tRPRE READ to WRITE Command delay = RL + tCCD +2tCK - WL NOP T2 READ to WRITE Command delay = RL + tCCD/2 +2tCK - WL NOP NOP T1 NOP NOP T5 n n +1 Dout n +1 n Dout Dout Dout NOP Col b Bank n +2 Dout NOP NOP T7 tRPST n +3 Dout n +3 Dout WL = 5 n +2 Dout WRITE T6 n +5 Dout n +6 Dout n +7 Dout WL = 5 tRPST NOP T9 tWPRE b Dout NOP READ (BL4) to WRITE (BL8) NOP READ (BL8) to WRITE (BC4) n +4 Dout NOP T8 b +1 Dout b +2 Dout NOP NOP T10 b +3 Dout tWPRE b +4 Dout NOP b Dout NOP T11 b +5 Dout b +1 Dout b +6 Dout NOP b +2 Dout NOP T12 b +7 NOP tWPST Dout b +3 Dout tWPST NOP T13 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Write Operation DDR3(L) Burst Operation During a READ or WRITE command, DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (Auto Precharge can be enabled or disabled). A12=0, BC4 (BC4 = Burst Chop, tCCD=4) A12=1, BL8 A12 is used only for burst length control, not as a column address. WRITE Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to "hang up" and errors be limited to that particular operation. For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Write Timing Parameters This drawing is for example only to enumerate the strobe edges that "belong" to a write burst. No actual timing violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge as shown). REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Write Timing Definition T0 T1 T2 T3 CMD Write NOP NOP NOP Address Bank Col n T4 T5 T6 NOP NOP T7 T8 T9 Tn NOP NOP NOP CK CK NOP tDSH tDSH tDSH tDQSS tDSH tWPRE(min) NOP tWPST(min) tDSS DQS, DQS (tDQSS min) tDQSH tDQSL tDQSH Din n DQ tDQSH tDSS tDSS Din n +1 Din n +2 Din n +3 Din n +4 Din n +5 Din n +6 tDQSL(min) tDSS Din n +7 tDSS WL = AL + CWL tWPST(min) tDSH tDSH tDSH tDSH tWPRE(min) tDSS DQS, DQS (tDQSS nominal) tDQSH tDQSL tDQSH Din n DQ Din n +2 Din n +3 tDQSL(min) tDQSH tDSS tDSS Din n +1 Din n +4 Din n +5 Din n +6 Din n +7 tDSS tDSS tDSH tDQSS tDSH tWPRE(min) tWPST(min) tDSH tDSH DQS, DQS (tDQSS max) tDQSH tDQSL tDQSH Din n DQ tDSS Din n +1 tDSS Din n +2 tDSS Din n +3 tDSS Din n +4 Din n +5 tDQSH Din n +6 tDQSL(min) Din n +7 tDSS Note: BL=8, WL=5 (AL=0, CWL=5). Din n = data in from column n. NOP commands are shown for ease of illustration; other command may be valid at these times. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0. tDQSS must be met at each rising clock edge. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK WL = 5 WRITE T4 Col n Bank WRITE NOP WL = 5 NOP READ WRITE (BC4) to WRITE (BC4) tCCD NOP WRITE (BL8) to WRITE (BL8) tCCD Col b Bank WRITE Col b NOP T3 Col n NOP T2 Bank NOP T1 Bank WRITE T0 tRPRE tWPRE n +1 n Dout n +1 Dout n NOP Dout Dout NOP T5 n +2 Dout NOP n +2 Dout NOP T6 NOP n +4 Dout n +3 Dout WL = 5 tWPST WL = 5 n +3 Dout NOP T7 n +5 Dout NOP n +6 Dout NOP T8 tWPRE n +7 Dout b Dout NOP b Dout NOP T9 b +1 Dout b +1 Dout b +2 Dout NOP b +2 Dout NOP T10 tBL=4 NOP b +4 Dout b +3 Dout tWPST b +3 Dout tBL=4 NOP T11 b +5 Dout NOP b +6 Dout NOP T12 b +7 Dout NOP tWPST NOP T13 tWTR tWR tWTR tWR NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP WRITE to WRITE (WL=5; CWL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK WL = 5 NOP T4 tWPRE NOP T5 NOP T6 Dout NOP T7 Dout NOP T8 Dout NOP T9 NOP T10 tWTR NOP T11 NOP NOP T12 READ T13 WL = 5 NOP tRPRE NOP NOP WRITE (BC4) to READ (BC4/BL8) Dout n +1 Dout n Dout n +2 tBL=4 n +3 Dout tWPST NOP n +4 Dout n +5 NOP n +6 Dout n +7 NOP NOP tWTR NOP READ Bank NOP n +3 Col b NOP n +2 Dout Bank NOP n +1 n Col n WRITE WRITE (BL8) to READ (BC4/BL8) Dout Dout tWPST Bank NOP T3 Col b NOP T2 Col n NOP T1 Bank WRITE T0 RL=5 RL=5 NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved REV 1.1 07/ 2012 DQ DQS, DQS Address CMD DQ DQS, DQS Address CMD CK CK WL = 5 WRITE T4 Col n Bank WRITE NOP WL = 5 NOP READ WRITE (BC4) to WRITE (BL8) tCCD NOP WRITE (BL8) to WRITE (BC4) tCCD Col b Bank WRITE Col b NOP T3 Col n NOP T2 Bank NOP T1 Bank WRITE T0 tRPRE tWPRE n +1 n Dout n +1 Dout n NOP Dout Dout NOP T5 n +2 Dout NOP n +2 Dout NOP T6 NOP n +4 Dout n +3 Dout WL = 5 tWPST WL = 5 n +3 Dout NOP T7 n +5 Dout NOP n +6 Dout NOP T8 tWPRE n +7 Dout b Dout NOP b Dout NOP T9 b +1 Dout b +1 Dout b +2 Dout NOP b +2 Dout NOP T10 b +3 Dout b +3 Dout b +3 Dout tBL=4 NOP tWPST tBL=4 NOP T11 b +4 Dout b +5 Dout NOP NOP T12 b +6 Dout b +7 Dout tWPST NOP NOP T13 tWTR tWR tWTR tWR NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP WRITE to WRITE (WL=5, CWL=5, AL=0) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Refresh Command The Refresh command (REF) is used during normal operation of the DDR3(L) SDRAMs. This command is not persistent, so it must be issued each time a refresh is required. The DDR3(L) SDRAM requires Refresh cycles at an average periodic interval of tREFI. When , , and are held Low and High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during a Refresh command. An internal address counter suppliers the address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in the following figure. In general, a Refresh command needs to be issued to the DDR3(L) SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3(L) SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in advance ("pulled in"), with each one reducing the number of regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be executed. Self-Refresh Entry/Exit Timing T0 T1 REF NOP Ta0 Tb0 Ta1 Tb1 Tb2 Tb3 Valid Valid Tc0 Tc1 CK CK CMD NOP tRFC REF NOP NOP Valid Valid Valid REF Valid tRFC(min) DRAM must be idle tREFI (max, 9 x tREFI) DRAM must be idle Time Break Postponing Refresh Commands (Example) tR E F I 9 x tR E F I t tR E F I 8 R E F -C o m m a n d p o stp o n e d REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Pulled-in Refresh Commands (Example) tR E F I 9 x tR E F I t tR E F I 8 R E F - C o m m a n d s p u lle d -in Self-Refresh Operation The Self-Refresh command can be used to retain data in the DDR3(L) SDRAM, even if the reset of the system is powered down. When in the Self-Refresh mode, the DDR3(L) SDRAM retains data without external clocking. The DDR3(L) SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by having , , , and held low with WE high at the rising edge of the clock. Before issuing the Self-Refreshing-Entry command, the DDR3(L) SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering ODT pin low "ODTL + 0.5tCK" prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh. When the DDR3(L) SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and , are "don't care". For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters Self-Refresh mode. The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3(L) SDRAM must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-Refresh mode. The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements [TBD] must be satisfied. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to compensate for the voltage and temperature drift as described in "ZQ Calibration Commands". To issue ZQ calibration commands, applicable timing requirements must be satisfied. CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3(L) SDRAM can be put back into Self-Refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3(L) SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh mode. " 61 T0 -1* 2 0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf Valid Valid CK, CK tCKSRE tCKSRX tCPDED CKE tCKESR Valid ODT ODTL CMD NOP SRE NOP SRX Enter Self Refresh Valid 3) Valid Valid Exit Self Refresh Note: 1. Only NOP or DES commands 2. Valid commands not requiring a locked DLL 3. Valid commands requiring a locked DLL 07/ 2012 Valid 2) tXS tXSDLL tRF REV 1.1 NOP 1) Do Not Care Time Break CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 4 4 4 4 1 / / 1* Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active Power-Down mode. Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, , and . To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. 4 4 1 Status of DRAM Active (A Bank or more open) MRS bit A12 DLL PD Exit Don't Care On Fast Relevant Parameters tXP to any valid command. tXP to any valid command. Since it is in precharge state, commands Precharged (All Banks Precharged) 0 Off Slow here will be ACT, AR, MRS/EMRS, PR, or PRA. tXPDLL to commands who need DLL to operate, such as RD, RDA, or ODT control line. Precharged (All Banks Precharged) 1 On Fast tXP to any valid command. Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, high, and a stable clock signal must be maintained at the inputs of the DDR3(L) SDRAM, and ODT should be in a valid state but all other input signals are "Don't care" (If goes low during Power-Down, the DRAM will be out of PD mode and into reset state). CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet. : 4 4 1 / 1* T0 T1 T2 Valid NOP N OP 0 / 0 Ta0 Ta1 Tb0 Tb1 Tc0 N OP NO P NO P V alid V alid CK CK CM D NO P tIS C KE tPD tIH tIH Address tIS tCK E Valid V alid tCPDED tX P Enter Power-D own Exit Power-Down Do not care Tim e Break iming Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate, Precharge, Refresh, MRS: 4 4 1 / T0 T1 Ta0 Ta1 Ta2 WRITE NOP NOP NOP NOP / /4 6 6 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tc0 NOP NOP Valid CK CK CMD NOP tIS CKE Address tCPDED Bank, Col n WL=AL+CWL WR (1) tPD DQS BL8 Din b Din b+1 Din b+2 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Start Internal Precharge Din b+3 tWRAPDEN Power-Down Entry 4 4 1 9 4 6 T0 T1 Ta0 Ta1 T a2 R D or RDA NOP NOP NOP NOP Do not care Time Break 6 T a3 T a4 T a5 T a6 NOP NOP NOP NOP T a7 T a8 T b0 Tb 1 NOP NOP NOP V alid CK CK CM D tIS C KE tC P D ED V alid tPD A dd ress V alid V alid RL = AL + CL DQS BL8 D in b D in b +1 D in b+2 D in b +3 BC4 D in b D in b+1 D in b+2 D in b +3 D in b+4 D in b +5 D in b+6 D in b +7 tR D P D E N P ow er-D ow n E ntry REV 1.1 07/ 2012 D o n ot care T im e B reak CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 4 4 1 9 T0 T1 T a0 T a1 T a2 W RITE NO P NOP NOP NOP T a3 Ta4 Ta5 Ta6 Ta7 T b0 NOP NOP NOP NOP NOP NOP T b1 Tb2 T c0 CK CK CM D NOP tIS CKE NOP NOP tC P D E D Bank, C ol n A d d res s W L =A L+C W L WR tP D DQS BL8 D in b D in b+1 D in b+2 D in b+3 BC4 D in b D in b+1 D in b+2 D in b+3 D in b+4 D in b+5 D in b+6 D in b+7 tW R P D E N P o w er-D o w n E n try 6 4 4 $ T0 T1 W R IT E NO P 1* / &1 T2 Do not ca re T im e B rea k / 1* Ta0 T a1 NO P N O P T b0 Tb1 T c0 N O P N O P N O P V a lid C K C K C M D NO P N O P tC P D E D tIS tC K E tIH C K E tIS tP D tX P E n te r P o w er-D o w n M ode 6 4 E x it P o w er -D o w n M ode 4 $ " 4 1* / &1 T0 T1 T2 T a0 T a1 W R IT E NOP NOP NOP NOP D o not ca re T im e B reak / 1* Tb0 Tb1 T c0 Td0 NOP NOP V a lid V a lid NOP V a lid V a lid CK CK CM D tIS tC P D E D tC K E tIH CKE tIS tX P tP D E n te r P o w e r -D o w n M ode 6 00 T0 / E x it P o w e r -D o w n M ode 4 tX P D L L T im e B reak D o not care 4 1 T1 T2 T3 T a0 N O P N O P T a1 CK CK C M D A d d ress R EF N O P V a lid V a lid V a lid tIS tC P D E D tP D CK E V a lid tR E F P D E N D o not care REV 1.1 07/ 2012 T im e B reak CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP : 00 / 4 T0 4 1 T1 T2 T3 T a0 CM D A c tiv e NOP NOP NOP A d d r e ss V a lid Ta1 CK CK V a lid V a lid tC P D E D tIS tP D CKE V a lid tA C T P D E N D o not care 6 - 6 "" T0 00 / 4 T im e B reak 4 1 T1 T2 T3 Ta0 CMD PRE PREA NOP NOP NOP A d d r e ss V a lid T a1 CK CK V a lid V a lid tC P D E D tIS tP D CKE V a lid tP R E P D E N D o not care 00 / 4 T im e B reak 4 1 T0 T1 T a0 T a1 CMD MRS NOP NOP NOP A d d ress V alid Tb0 Tb1 CK CK V alid V alid tIS tC P D E D tP D CKE V alid tM R S P D E N D o n ot care REV 1.1 07/ 2012 T im e B reak CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . 2 0 $. 2& ODT (On-Die Termination) is a feature of the DDR3(L) SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, , and DM for x8 configuration and TDQS, for x8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown as below. " . 2 ODT To other circuitry like RCV, ... VDDQ/ 2 RTT Switch DQ , DQS, DM, TDQS The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode. . 2 / /. 22 62 " The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is determined by the settings of those bits. Application: Controller sends WR command together with ODT asserted. One possible application: The rank that is being written to provides termination. DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) DRAM does not use any write or read command decode information. 2 0 2 62 " ODT pin DRAM Termination State 0 OFF 1 ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general) REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 6 . 2 / Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are: Any bank active with CKE high Refresh with CKE high Idle mode with CKE high Active power down mode (regardless of MR0 bit A12) Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12 The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2. . 2 / /. 2 In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3(L) SDRAM latency definitions. ODT Latency Symbol ODTLon ODTLoff REV 1.1 07/ 2012 Parameter ODT turn on Latency ODT turn off Latency DDR3/DDR3L-1066 DDR3/DDR3L-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit WL - 2 = CWL + AL - 2 tCK WL - 2 = CWL + AL - 2 tCK CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 20 0 In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max. Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. 6 . 2 . 22 0 F 9 <C) C T0 T1 T2 T3 1* 0 " T4 T5 C E 9 CDE. 2 T6 T7 T8 T9 T10 C T11 F 9 T12 T13 <C)E T14 T15 CK CK CKE ODT AL=3 AL=3 tAONmax CWL - 2 tAONmax ODTH4, min ODTLon = CWL + AL -2 tAONmin tAONmin ODTLoff = CWL + AL -2 RTT_NOM DRAM_RTT Transitioning 6 . 2 * 0 "4 6 T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 NOP NOP Do not care C 89 C T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK NOP NOP WRS4 NOP ODTH4 ODTH4 ODT ODTH4min ODTLoff = CWL -2 tAONmin tAONmax ODTLoff = WL- 2 tAOFmax tAOFmin tAOFmax tAONmax tAONmin tAOFmin RTT_NOM DRAM_RTT ODTLon = CWL-2 ODTLon = CWL -2 Transitioning Do not care ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . 2/ /G As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example. . 20 / "/ * "" / $1* 0 " G C)E C +CDE C F . 2 C 9 F <C!& T0 T1 T2 T3 T4 T5 T6 T7 / / : . 2" 4H C++E 9 CDE. 2 C 9 F <C!E T8 T9 T10 T11 T12 T13 T14 T15 T16 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD Read Address Valid NOP NOP NOP NOP NOP NOP NOP RL = AL + CL ODT ODTLon = CWL + AL - 2 ODTLoff = CWL + AL - 2 tAONmax tAOFmin DRAM ODT RTT_NOM RTT RTT_NOM tAOFmax DQSdiff Din b DQ 0 Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 . 2 In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. This requirement is supported by the "Dynamic ODT" feature as described as follows: " The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to `1'. The function is described as follows: Two RTT values are available: RTT_Nom and RTT_WR. The value for RTT_Nom is preselected via bits A[9,6,2] in MR1. The value for RTT_WR is preselected via bits A[10,9] in MR2. During operation without write commands, the termination is controlled as follows: Nominal termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows: A latency ODTLcnw after the write command, termination strength RTT_WR is selected. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic ODT mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9 = [0,0], to disable Dynamic ODT externally. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT is register low. / 0 Name and Description ODT turn-on Latency ODT turn-off Latency ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BL=4) ODT Latency for change from RTT_WR to RTT_Nom (BL=8) Minimum ODT high time after ODT assertion Minimum ODT high time after Write (BL=4) Minimum ODT high time after Write (BL=8) RTT change skew Abbr. ODTLon ODTLoff ODTLcnw 0 ": Defined from registering external ODT signal high registering external ODT signal low registering external write command 0 Defined to turning termination on turning termination off change RTT strength from RTT_Nom to RTT_WR change RTT strength from RTT_WR to RTT_Nom change RTT strength from RTT_WR to RTT_Nom ODT registered low . 2 Definition for all DDR3(L) speed pin ODTLon=WL-2 tCK ODTLoff=WL-2 tCK ODTLcnw=WL-2 tCK ODTLcwn4=4+ODTLoff tCK ODTLcwn8=6+ODTLoff tCK(avg) ODTH4=4 tCK(avg) Unit ODTLcwn4 registering external write command ODTLcwn8 registering external write command ODTH4 registering ODT high ODTH4 registering write with ODT high ODT registered low ODTH4=4 tCK(avg) ODTH8 registering write with ODT high ODT register low ODTH8=6 tCK(avg) tADC ODTLcnw ODTLcwn RTT valid tADC(min)=0.3tCK(avg) tADC(max)=0.7tCK(avg) tCK(avg) Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn) REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . 22 0 0 T0 0 . 2G T1 6 : T2 T3 4 6. 2 T4 T5 T6 / T7 / 6 4 T8 T9 T10 T11 T12 T13 T 14 T 15 T16 T 17 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CM D NOP NOP NOP NOP W RS4 A d d ress NOP NOP NOP V a lid ODT O D T L o ff O DTH 4 O D TLcw n4 tA D C m in tA O N m in R TT_N om RT T R TT_W R tA O N m a x OD TLon tA O F m in tA D C m in R TT _N om tA D C m a x tA O F m a x tA D C m ax O D T L cn w OD TH4 D Q S /D Q S WL D in n DQ D in n+1 D in n+2 D in n+3 D o not care T r a n sit io n in g Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command). 0 . 2G 6 : 4 6 T0 T1 T2 T3 Valid Valid Valid Valid 4 00 T4 T5 T6 Valid Valid /8 C78 9 CD T7 T8 T9 T10 T11 Valid Valid Valid Valid CK CK CMD Valid Valid Address ODTLoff ODT ODTH4 ODTLoff tADCmin tAONmin RTT_Nom RTT tADCmax tAONmax ODTLon DQS/DQS DQ Do not care Transitioning Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 6 clock cycles. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CM D NOP W RS8 NOP NOP NOP NOP NOP NOP O D T L cnw A d d re ss V a lid ODT ODTH8 O D T L on O D T L o ff tA O F m in tA O N m in R T T _W R RTT tA O F m a x tA O N m a x O D T L c w n8 D Q S /D Q S WL DQ D in h D in h+1 D in h+2 D in h+3 D in h+4 D in h+ 5 D in h+6 D in h+7 D o n ot care T r a n sitio n in g Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL=0, CWL=5. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CM D O D T Lcnw NOP W RS4 NOP NOP NOP NOP NOP NOP V a lid A d dress ODT ODTH4 tA O N m in O D T L o ff tA D C m in R TT_W R RTT tA O N m a x O D TLon tA O F m in R TT_N om tA O F m a x tA D C m a x O D T L cw n4 D Q S /D Q S WL D in n DQ D in n+1 D in n+2 D in n+3 D o not ca re T r a n s it io n in g Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 4 clock cycles. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T11 NOP NOP NOP NOP CK CK# CM D O D T L cnw NOP A d dress W RS4 NOP NOP NOP NOP NOP NOP V a li d ODT O DTH4 tA O N m in O D T L o ff t A O F m in R TT_W R RTT tA O N m a x O D TLon tA O F m a x O D T L cw n4 D Q S /D Q S WL DQ D in n D in n+1 D in n+2 D in n+3 D o not care REV 1.1 07/ 2012 T r a n s it io n in g CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max. Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in time when the ODT resistance is fully on. tAONPDmin and tAONPDmax are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low. Asynchronous ODT Timings on DDR3(L) SDRAM with fast ODT transition: AL is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# CKE tIS tIH ODT tIS tIH tAONPDmax tAOFPDmin RTT tAONPDmin tAOFPDmax Do not care Transitioning In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the respective ADD/CMD receivers may be disabled. Asynchronous ODT Timing Parameters for all Speed Bins Symbol Description Min. Max. Unit tAONPD Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 2 8.5 ns tAOFPD Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 2 8.5 ns ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period Description Min. Max. ODT to RTT min{ ODTLon * tCK + tAONmin; tAONPDmin } max{ ODTLon * tCK + tAONmax; tAONPDmax } turn-on delay min{ (WL - 2) * tCK + tAONmin; tAONPDmin } max{ (WL - 2) * tCK + tAONmax; tAONPFmax } ODT to RTT min{ ODTLoff * tCK + tAOFmin; tAOFPDmin } max{ ODTLoff * tCK + tAOFmax; tAOFPDmax } turn-off delay min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin } max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax } tANPD REV 1.1 07/ 2012 WL-1 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to "0", there is a transition period around power down entry, where the DDR3(L) SDRAM may show either synchronous or asynchronous ODT behavior. The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period. ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and (ODTLon*tck+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period. Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen) entry (AL=0; CWL=5; tANPD=WL-1=4) CK T1 T2 T3 T4 NOP NOP NOP T5 T6 T7 T8 T9 T 10 T11 T12 CK CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE tA N P D t C P D E D m in tC P D E D P D e n tr y tr a n s itio n p e r io d L ast sync. ODT t A O F m in RTT RTT O D T L off tA O F m ax S ync. O r async. O D T RTT RTT tA O F P D m in tA O F P D m a x O D T L o ff+ tA O F P D m in O D T L o ff+ tA O F P D m a x F irs t a s y n c . ODT tA O F P D m a x RTT RTT tA O F P D m in T r a n s itio n in g REV 1.1 07/ 2012 D o not care T im e B reak CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Asynchronous to Synchronous ODT Mode transition during Power-Down Exit If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to "0", there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3(L) SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response. Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9) CK T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CKE CMD NOP tANPD NOP NOP NOP NOP PD exit transition period tXPDLL ODT_C _sync tAOFPDmin DRAM _RTT_ C_sync RTT tAOFPDmax ODT_B _tran tAOFPDmin DRAM _RTT_ B_tran RTT tAOFPDmax ODTLoff + tAOFmin ODTLoff + tAOFmax ODTLoff ODT_A _async tAOFmax tAOFmin DRAM_ RTT_A_ async RTT Transitioning REV 1.1 07/ 2012 Do not care Time Break CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period (even if the entry ends later than the exit period). If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered. Transition period for short CKE cycles with entry and exit period overlapping (AL=0; WL=5; tANPD=WL-1=4) T0 T1 T2 T3 REF NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP NOP CK CK CMD NOP NOP CKE tANPD tANPD PD exit transition period PD entry transition period tRFC(min) tXPDLL CKE Short CKE high transition period REV 1.1 07/ 2012 tXPDLL Do not care Transitioning CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ZQ Calibration Commands ZQ Calibration Description ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3(L) SDRAM needs longer time to calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh exit, DDR3(L) SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between ranks. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ZQ Calibration Timing T0 T1 Ta0 Ta1 ZQCL NOP NOP NOP Ta2 Ta3 Tb0 Tb1 Valid Valid ZQCS Address Valid Valid A10 Valid Valid Tc0 Tc1 Tc2 NOP NOP Valid CK CK CMD NOP Valid CKE (1) Valid Valid (1) Valid ODT (2) Valid Valid (2) Valid DQ Bus (3) Hi-Z Activities (3) tZQCS Hi-Z Activities tZQCS Do not care Time Break Note: 1. CKE must be continuously registered high during the calibration procedure. 2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure. 3. All devices connected to the DQ bus should be high impedance during the calibration procedure. ZQ External Resistor Value, Tolerance, and Capacitive loading In order to use the ZQ calibration function, a 240 ohm +/- 0.1% tolerance external resistor connected between the ZQ pin and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Absolute Maximum Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Vin, Vout Tstg Parameter Rating Units Note Voltage on VDD pin relative to Vss -0.4 ~ 1.975 V 1,3 Voltage on VDDQ pin relative to Vss -0.4 ~ 1.975 V 1,3 Voltage on any pin relative to Vss -0.4 ~ 1.975 V 1 -55 ~ 100 C 1,2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and VDDQ are less than 500Mv; Vref may be equal to or less than 300mV. Temperature Range Symbol Toper Condition Commercial Industrial Parameter Value Units Notes Normal Operating Temperature Range 0 to 85 C 1,2 Extended Temperature Range 85 to 95 C 1,3 Operating Temperature Range -40 to 95 C 1.4 Note: 1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional apply. a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also possible to specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0). 4. During Industrial Temperature Operation Range, the DRAM case temperature must be maintained between -40C~95C under all operating Conditions. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP AC & DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Rating Parameter Supply Voltage Supply Voltage for Output Unit Min. Typ. Max. DDR3 1.425 1.5 1.575 DDR3L 1.283 1.35 1.45 DDR3 1.425 1.5 1.575 DDR3L 1.283 1.35 1.45 V Note 1,2 3,4,5,6 V 1,2 3,4,5,6 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time (e.g., 1 sec). 4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 5. Under these supply voltages, the device operates to this DDR3L specification. 6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP AC & DC Input Measurement Levels / , : " Symbol " 1 / / "I 00 / / // DDR3-1066/1333/1600 Parameter Min. Max. Unit Note VIH.CA(DC100) DC input logic high Vref + 0.100 VDD V 1 VIL.CA(DC100) DC input logic low VSS Vref - 0.100 V 1 VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 V 1,2 VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 V 1,2 VIH.CA(AC150) AC input logic high Vref + 0.150 Note2 V 1,2 VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 V 1,2 VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3,4 DDR3L-1066/1333/1600 VIH.CA(DC90) DC input logic high Vref + 0.09 VDD V 1 VIL.CA(DC90) DC input logic low VSS Vref - 0.09 V 1 VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 V 1,2 VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 V 1,2 VIH.CA(AC135) AC input logic high Vref + 0.135 Note2 V 1,2 VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 V 1,2 VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3,4 Note: 1. For input only pins except RESET.Vref=VrefCA(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD. 4. For reference: approx. VDD/2 +/- 15mv, DDR3L is VDD/2 +/-13.5mv. 5 These levels apply for 1.35 Volt operation only. If the device is operated at 1.5V, the respective levels in JESD79-3. (VIH/L.CA(DC100), VIH/L.CA (AC175), VIH/L.CA (AC150), etc.) apply. The 1.5V levels (VIH/L.CA (DC100), VIH/L.CA (AC175), VIH/L.CA (AC150), etc.) do not apply when the device is operated in the 1.35Voltage range. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM Symbol DDR3-1066 Parameter DDR3-1333/1600 DDR3-1866/2133 Max. Min. Max. VIH.DQ(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.DQ(DC100) DC input logic low VSS Vref - 0.1 VSS Vref - 0.1 V 1 VIH.DQ(AC175) AC input logic high Vref + 0.175 Note2 - - V 1,2,5 VIL.DQ(AC175) AC input logic low Note2 Vref - 0.175 - - V 1,2,5 VIH.DQ(AC150) AC input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 V 1,2,5 VIL.DQ(AC150) AC input logic low Note2 Vref - 0.15 Note2 Vref - 0.15 V 1,2,5 V 1,2,5 V 1,2,5 V 3,4 Vref + VIH.DQ(AC135) AC input logic high 0.135 VIL.DQ(AC135) AC input logic low VREFDQ(DC) Min. Note2 Reference Voltage for DQ, DM inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD DDR3L-1066 VIH.DQ(DC90) DC input logic high Max. Unit Note Min. Note2 Vref 0.135 0.49 * 0.51 * VDD VDD DDR3L-1333/1600 Vref + 0.09 VDD Vref + 0.09 VDD V 1 VSS Vref - 0.09 VSS Vref - 0.09 V 1 VIH.DQ(AC160) AC input logic high Vref + 0.160 Note2 - V 1,2,5 VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160 - - V 1,2,5 VIH.DQ(AC135) AC input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5 VIL.DQ(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 VIL.DQ(DC90) VREFDQ(DC) DC input logic low Reference Voltage for DQ, DM inputs 0.49 * VDD - Note: 1. For input only pins except . Vref = VrefDQ(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than 0.1% VDD. 4. For reference: approx. VDD/2 15mv, DDR3L is for VDD/2 13.5mv. 5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5V, the respective levels in JESD79-3.(VIH/L.CA(DC100), VIH/L.CA (AC175), VIH/L.CA (AC150), etc.) apply. The 1.5V levels (VIH/L.CA (DC100), VIH/L.CA (AC175), VIH/L.CA (AC150), etc.) do not apply when the device is operated in the 1.35Voltage range. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Vref Tolerances The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise). Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than 1% VDD. The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref. "Vref" shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit ( 1% of VDD) are included in DRAM timing and their associated de-ratings. H+G ,"" ; $ & " /; "0 V o lta g e VDD V re f a c - n o is e V re f (D C ) V re f( D C )m a x V D D /2 V re f(D C )m in V SS tim e REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / , Symbol : " " Parameter VIHdiff VILdiff VIHdiff(ac) VILdiff(ac) Differential input logic high Differential input logic low Differential input high ac Differential input low ac VIHdiff VILdiff Differential input logic high Differential input logic low " DDR3-1066, 1333 &1600 Min. Max. +0.2 Note3 Note3 -0.2 2 x ( VIH(ac) - Vref ) Note3 Note3 2 x ( Vref - VIL(ac) ) DDR3L-1066,1333 +0.180 Note3 Unit Note3 -0.180 Notes V V V V 1 1 2 2 V V 1 1 VIHdiff(ac) Differential input high ac 2 x ( VIH(ac) - Vref ) Note3 V 2 VILdiff(ac) Differential input low ac Note3 2 x ( Vref - VIL(ac) ) V 2 Note: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there. 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot. Differential Input Voltage(i.e. DQS -DQS, CK- CK) / " 4 /@ 0 : " : "A tDVAC VIH.Diff.AC.min VIH.Diff. DC min 0 Half cycle VIL. Diff. DC max VIL.Diff.AC. max tDVAC Time REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP "" 4 / 0 Slew Rate [V/ns] #$ ; & > / J +HD; tDVAC [ps] tDVAC [ps] @IVIH/Ldiff(ac)I = 350Mv @IVIH/Ldiff(ac)I = 300mV Min. Max. Min. Max. > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - 1.35V Slew Rate [V/ns] REV 1.1 07/ 2012 tDVAC [ps] tDVAC [ps] @IVIH/Ldiff(ac)I = 320mV @IVIH/Ldiff(ac)I = 270mV Min. Max. Min. Max. > 4.0 TBD - TBD - 4.0 TBD - TBD - 3.0 TBD - TBD - 2.0 TBD - TBD - 1.8 TBD - TBD - 1.6 TBD - TBD - 1.4 TBD - TBD - 1.2 TBD - TBD - 1.0 TBD - TBD - < 1.0 TBD - TBD - CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " / / 0 / " " Each individual component of a differential signal (CK, DQS, DQSL, DQSU, , , , or ) has also to comply with certain requirements for single-ended signals. CK and have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, , have to reach VSEHmin / VSELmax (approxi- mately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g., if VIH150 (ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " / /": " Symbol VSEH VSEL >8 J 8 J 8 J K, , , , DDR3-1066, 1333 &1600 Parameter Unit Notes note3 V 1, 2 (VDDQ/2) + 0.175 note3 V 1, 2 Single-ended low-level for strobes note3 (VDDQ/2) - 0.175 V 1, 2 Single-ended Low-level for CK, note3 (VDDQ/2) - 0.175 V 1, 2 Min. Max. Single-ended high-level for strobes (VDDQ/2) + 0.175 Single-ended high-level for CK, Note: 1. For CK, use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, , , or ) use VIH/VIL(ac) of DQs. 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there. 3. These values are not defined, however the single-ended signals CK, , DQS, , DQSL, , DQSU, need to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot. ", ; " To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the following table. The differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel between of VDD and VSS. ;* VDD , V IX VSEH V IX VIX VDD/2 CK,DQS VSEL REV 1.1 07/ 2012 VSS CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP : " / Symbol " " $ >8 J & DDR3-1066, 1333 &1600 Parameter Note Max. -150 150 mV -175 175 mV 1 DDR3L -150 150 mV 2 Differential Input Cross Point Voltage relative to VDD/2 DDR3 -150 150 mV for DQS, DQS DDR3L -150 150 mV DDR3 Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Vix Unit Min. Note 1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and with a single-ended swing VSEL / VSEH of at least VDD/2 are monotonic 250mV, and when the differential slew rate of CK - is larger than 3V/ns. 2: The relation between Vix Min/Max and VSEL/VSEH should satisfy following. (VDD/2)+Vix (Min.)-VSE VSEH - ((VDD/2) +Vix (Max.)) "4 ", " Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown below. ", "4 Measured Description Differential input slew rate for rising edge (CKDQS- & ) Differential input slew rate for falling edge (CKDQS- From ) The differential signal (i.e., CK- & DQS- & Defined by To VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff ) must be linear between these thresholds. Input Nominal Slew Rate Definition for single ended signals Delta TRdiff VIHdiffMin 0 VILdiffMax Delta TFdiff REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / . 0 "1 / / / . Symbol :" : " Parameter Value Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.8xVDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5xVDDQ V VOL(DC) DC output low measurement level (fro IV curve linearity) 0.2xVDDQ V VOH(AC) AC output high measurement level (for output SR) VTT+0.1xVDDQ V 1 VOL(AC) AC output low measurement level (for output SR) VTT-0.1xVDDQ V 1 Note: 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 " and an effective test load of 25 / . Symbol to VTT = VDDQ/2. : " Parameter DDR3/DDR3L Unit Notes VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1 VOLdiff(AC) -0.2 x VDDQ V 1 AC differential output low measurement level (for output SR) Note: 1. The swing of impedance of 40 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver and an effective test load of 25 " 1 / /. to VTT=VDDQ/2 at each of the differential outputs. "4 Description Measured From To Defined by Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse Note: Output slew rate is verified by design and characterization, and may not be subject to production test. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP " 1 / /. "4 D e lta T F se Single Ended Output Voltage (i.e. DQ) V O H (A C ) V TT V O L (A C ) D elta T F se . "4 Parameter Single-ended Output Slew Rate $ Symbol SRQse " / /& Operation DDR3(L)-1066 DDR3(L)-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit Note Voltage Min. Max. Min. 1.35V 1.75 5 1.75 5 1.75 5 TBD TBD TBD TBD V/ns 1.5V 2.5 5 2.5 5 TBD 5 2.5 2.5 Max. Min. Max. Min. Max. Min. Max. 5 5 1 V/ns Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting. Note: 1) In two cased, a maximum slew rate of 6V/ns applies for a signal within a byte lane. -Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low). -Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e., from low to high or high to low respectively). For the remaining DQ signal switching into the opppsite direction, the regular maximum limit of 5 V/ns applies. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ". "4 Measured Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Description ". "4 Differential Output Voltage (i.e. DQS-DQS) D e lta T F s e V O h d iff (A C ) 0 V O L d iff (A C ) D e lta T F s e ". Parameter Single-ended Output Slew Rate "4 Symbol SRQse Operation DDR3(L)-1066 DDR3(L)-1333 DDR3-1600 DDR3-1866 DDR3-2133 Voltage Min. Max. Min. Max. 1.35V 3.5 12 3.5 12 3.5 12 1.5V 5 10 5 10 TBD 10 Min. Max. Min. Max. Min. Max. Unit TBD TBD TBD TBD V/ns 5 12 5 12 V/ns Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). diff: Differential signals. For Ron = RZQ/7 setting. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / 20 /. "4 The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK , DUT 25 Ohm DQ DQS Vtt = VDDQ/2 Timing Reference Points REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP .: 6 .: 6 /K / 6 -K / 6 // / " DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Units Item 1.35V Maximum peak amplitude allowed for overshoot area TAB TAB TAB TAB TAB Maximum peak amplitude allowed for undershoot TAB TAB TAB TAB TAB Maximum overshoot area above VDD TAB TAB TAB TAB TAB V-ns Maximum undershoot area below VSS TAB TAB TAB TAB TAB V-ns 0.4 0.4 0.4 0.4 0.4 V 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.5 0.4 0.33 0.28 0.25 V-ns Maximum undershoot area below VSS 0.5 0.4 0.33 0.28 0.25 V-ns area V V 1.5V Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area (A0-A15, BA0-BA3, REV 1.1 07/ 2012 , , , , CKE, ODT) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP .: 6 -K / 6 " #8 Item 8 8 / # DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Units 1.35V Maximum peak amplitude allowed for overshoot area TAB TAB TAB TAB TAB Maximum peak amplitude allowed for undershoot TAB TAB TAB TAB TAB Maximum overshoot area above VDD TAB TAB TAB TAB TAB V-ns Maximum undershoot area below VSS TAB TAB TAB TAB TAB V-ns 0.4 0.4 0.4 0.4 0.4 V 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.19 0.15 0.13 0.11 0.1 V-ns Maximum undershoot area below VSS 0.19 0.15 0.13 0.11 0.1 V-ns area V V 1.5V Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area (CK, REV 1.1 07/ 2012 , DQ, DQS, , DM) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP .60 . : 1" " 6 A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms) The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = [VDDQ-Vout] / l Iout l ------------------- under the condition that RONPd is turned off (1) RONPd = Vout / I Iout I -------------------------------under the condition that RONPu is turned off (2) . : G ; " / Chip in Drive Mode Output Driver VDDQ I Pu To other circuitry like RCV, ... REV 1.1 07/ 2012 RONPu I Pd DQ I Out RONPd V Out VSSQ CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . : 1" 0 " 6 RONNom 8 0 E Resistor LJ Vout LJ C < 7 60 ; " Min. Nom. Max. Unit Notes 1.35V RON34Pd 34 ohms RON34Pu RON40pd 40 ohms RON40pu Mismatch between pull-up and pull-down, MMPuPd VOLdc = 0.2 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ -10 +10 % VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ -10 +10 % 1,2,4 1.5V RON34Pd 34 ohms RON34Pu RON40pd 40 ohms RON40pu Mismatch between pull-up and pull-down, MMPuPd REV 1.1 07/ 2012 1,2,4 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Note: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above. e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, but at 0.5 x VDDQ: MMPuPd = [RONPu - RONPd] / RONNom x 100 REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . : 2 0 /; " : If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. . : : Items Min. Max. Unit RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RZQ/7 RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl 1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RZQ/7 RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl 1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl RZQ/7 Output Driver Voltage and Temperature Sensitivity Speed Bin Items DDR3(L)-1066/1333 DDR3-1600 Unit Min. Max. Min. Max. dRONdTM 0 1.5 0 1.5 %/C dRONdVM 0 0.15 0 0.13 %/mV dRONdTL 0 1.5 0 1.5 %/C dRONdVL 0 0.15 0 0.13 %/mV dRONdTH 0 1.5 0 1.5 %/C dRONdVH 0 0.15 0 0.13 %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS/ , and TDQS/ (x8 devices only) pins. A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: RTTPu = [VDDQ - Vout] / I Iout I ------------------ under the condition that RTTPd is turned off (3) RTTPd = Vout / I Iout I ------------------------------ under the condition that RTTPu is turned off (4) On-Die Termination: Definition of Voltages and Currents Chip in Termination M ode ODT VDDQ I Pu To other circuitry like RCV, ... RTT I Out =I Pd -I Pu Pu DQ I Pd RTT I Out V Out Pd VSSQ ODT DC Electrical Characteristics The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ /2 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4 1.35V RTT120Pd240 0,1,0 120 RTT120Pu240 RTT120 RTT60Pd120 0, 0, 1 60 RTT60Pu120 RTT60 RTT40Pd80 0, 1, 1 40 RTT40Pu80 RTT40 RTT30Pd60 1, 0, 1 30 RTT30Pu60 RTT30 RTT20Pd40 1, 0, 0 20 RTT20Pu40 RTT20 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/4 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/6 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/8 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/12 1,2,5 +5 % 1,2,5,6 Deviation of VM w.r.t. VDDQ/2, DVM REV 1.1 07/ 2012 -5 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1,1 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4 1.5V RTT120Pd240 0,1,0 120 RTT120Pu240 RTT120 RTT60Pd120 0, 0, 1 60 RTT60Pu120 RTT60 RTT40Pd80 0, 1, 1 40 RTT40Pu80 RTT40 RTT30Pd60 1, 0, 1 30 0.9 1 1.6 RZQ /2 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/4 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/6 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 RTT30 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/8 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 RTT20Pd40 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/12 1,2,5 +5 % 1,2,5,6 RTT30Pu60 1, 0, 0 VIL(ac) to VIH(ac) 20 RTT20Pu40 RTT20 Deviation of VM w.r.t. VDDQ/2, DVM REV 1.1 07/ 2012 -5 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Note: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration may be used to achieve the linearity spec shown above. 4. Not a specification requirement, but a design guide line. 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current / (VIH(ac)), then apply VIL(ac) to pin under test and measure current / (VIL(ac)) respectively. RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))] 6. Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no lead: Delta VM = [2VM / VDDQ -1] x 100 . 22 0 /; " : If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ . 2 : Min. Max. RTT 0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl . 2; " /2 0 Unit 1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl RZQ/2,4,6,8,12 : Min. Max. Unit dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. 2 / . 22 0 Different than for timing measurements, the reference load for ODT timings is defined in the following figure. . 22 0 / VDDQ CK , DUT RTT= 25 Ohm Vtt = VSSQ DQ , DM DQS , TDQS , Timing Reference Points VSSQ REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . 22 0 Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures. Symbol tAON Begin Point Definition End Point Definition Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom tADC Rising edge of CK - CK defined by the end point of ODTLcnw, End point: Extrapolated point at VRTT_Wr and ODTLcwn4, or ODTLcwn8 REV 1.1 07/ 2012 VRTT_Nom respectively CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . 22 0 Measured Parameter 0 RTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/4 NA 0.05 0.10 RZQ/12 NA 0.10 0.20 RZQ/12 RZQ/2 0.20 0.30* tAON tAONPD tAOF tAOFPD tADC Note 1 Note1: VSW2 of tADC1.35V is 0.25V .? B e g in p o in t: R is in g e d g e o f C K - C K # D e f in e d b y th e e n d p o in t o f O D T L o n C K V T T C K # tA O N T sw 2 T sw 1 D Q , D M D Q S , D Q S # T D Q S , T D Q S # V sw 2 V sw 1 V S S Q E n d p o in t: E x tr a p o la te d p o in t a t V S S Q .? B e g in p o in t: R is in g e d g e o f C K - C K # w it h O D T b e in g fir s t r e g is t e r h ig h C K V TT C K # tA O N P D Tsw 2 Tsw 1 D Q , D M D Q S , D Q S # TD Q S , TD Q S # V sw 2 V sw 1 V S S Q E n d p o in t: E x tr a p o la te d p o in t a t V S S Q REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP . B e g in p o in t: R is in g e d g e o f C K - C K # d e fin e d b y th e e n d p o in t o f O D T L o ff C K VTT C K# tA O F VR TT_N om E n d p o in t: E x tr a p o la te d p o in t a t V R T T _ N o m Tsw 2 D Q , D M D Q S, D Q S# TD Q S, TD Q S# Tsw 1 V sw 2 V sw 1 VSSQ . B e g in p o in t: R is in g e d g e o f C K - C K # w ith O D T b e in g fir s t r e g is te r e d lo w C K V TT C K# tA O F P D VR TT_N om E n d p o in t: E x tr a p o la te d p o in t a t V R T T _ N o m Tsw 2 D Q , D M D Q S, D Q S# TD Q S, TD Q S # Tsw 1 V sw 2 V sw 1 B e g in p o in t: R is in g e d g e o f C K - C K # d e fin e d b y th e e n d o f O D T L c n w CK VS SQ B e g in p o in t: R is in g e d g e o f C K - C K # d e fin e d b y th e e n d o f O D T L c w n 4 o r O D T L c w n 8 CK VTT CK# CK# tA D C VR TT_N om tA D C E n d p o in t: E x tra p o la te d p o in t a t V R T T _ N o m VR TT_N om Tsw 22 Tsw 21 DQ, DM DQS, DQS# TD Q S, TD Q S# Tsw 12 Tsw 11 V sw 2 REV 1.1 07/ 2012 VR TT_W r E n d p o in t: E x tra p o la te d p o in t a t V R T T _ W r V sw 1 VSSQ CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , -. Symbol CIO Parameter Voltage DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 1.4 2.2 1.4 2.1 Input/output capacitance (DQ, DM, 1.5V 1.50 3.00 1.50 2.50 1.50 2.30 DQS, 1.35V 1.50 2.50 1.50 2.30 1.50 2.30 TBD TBD TBD TBD , TDQS, ) Units Notes pF 1,2,3 CCK Input capacitance, CK and CK 1.5V 0.80 1.60 0.80 1.40 0.80 1.40 0.8 1.3 0.8 1.3 pF 2,3 CDCK Input capacitance delta, 1.5V 0.00 0.15 0.00 0.15 0.00 0.15 0 0.15 0 0.15 pF 2,3,4 1.5V 0.00 0.20 0.00 0.15 0.00 0.15 0 0.15 0 0.15 pF 2,3,5 Input capacitance, CTRL, ADD, CMD 1.5V 0.75 1.35 0.75 1.30 0.75 1.30 0.75 input-only pins 1.35V 0.75 1.30 0.75 1.30 0.75 1.30 TBD TBD TBD TBD pF 2,3,7,8 1.5V -0.50 0.30 -0.40 0.20 -0.40 0.20 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 1.5V -0.50 0.50 -0.40 0.40 -0.40 0.40 -0.4 0.4 -0.4 0.4 pF 2,3,9,10 1.5V -0.50 0.30 -0.50 0.30 -0.50 0.30 -0.5 0.3 -0.5 0.3 pF 2,3,11 - 3.00 - 3.00 pF 2,3,12 CDDQS CI CDI_CTRL CDI_ADD_CMD CDIO CZQ CK and Input/output capacitance delta, DQS and Input capacitance delta, all CTRL input-only pins Input capacitance delta, all ADD/CMD input-only pins Input/output capacitance delta, DQ, DM, DQS, , TDQS, Input/output capacitance of ZQ pin 1.5V - 3.00 - 3.00 - 3.00 1.2 0.75 1.2 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V or 1.35V VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, , CKE, A0-A13, BA0-BA2, 7. CDI_CTRL applies to ODT, , , . and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, , 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI( 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO and )) )) 12. Maximum external load capacitance on ZQ pin: 5 pF. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , , / $+H D;& 0 / DDR3L-1333 DDR3L-1600 Symbol (-CG) Parameter/Condition (-DI) Unit X8 X16 X8 X16 65 80 75 90 85 110 90 115 mA 25 25 25 25 mA 32 32 37 37 mA Operating Current 0 IDD0 -> One Bank Activate mA -> Precharge Operating Current 1 IDD1 -> One Bank Activate -> Read -> Precharge IDD2P0 IDD2P1 Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 IDD2Q Precharge Quiet Standby Current 44 44 47 47 mA IDD2N Precharge Standby Current 47 47 47 47 mA 50 60 50 60 mA mA IDD3P Active Power-Down Current Always Fast Exit IDD3N Active Standby Current 57 70 62 77 IDD4R Operating Current Burst Read 167 240 180 270 mA IDD4W Operating Current Burst Write 155 230 190 260 mA IDD5B Burst Refresh Current 195 195 203 203 mA 25 25 25 25 mA 30 30 30 30 mA 268 285 268 320 mA IDD6 IDD6ET IDD7 REV 1.1 07/ 2012 Self-Refresh Current: Normal Temperature Range (Tcase: 0-85C) Self-Refresh Current: Extended Temperature Range (Tcase: 0-95C) All Bank Interleave Read Current CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , $+HD;& Symbol Parameter/Condition DDR3-1333 DDR3-1600 (-CG) (-DI) Unit X8 X16 X8 X16 75 85 80 90 mA 90 110 100 115 mA 25 25 25 25 mA 35 35 40 40 mA Operating Current 0 IDD0 -> One Bank Activate -> Precharge Operating Current 1 IDD1 -> One Bank Activate -> Read -> Precharge IDD2P0 IDD2P1 Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 IDD2Q Precharge Quiet Standby Current 45 45 50 50 mA IDD2N Precharge Standby Current 50 50 50 50 mA 60 60 60 60 mA IDD3P Active Power-Down Current Always Fast Exit IDD3N Active Standby Current 60 73 62 77 mA IDD4R Operating Current Burst Read 167 240 187 280 mA IDD4W Operating Current Burst Write 170 240 193 280 mA IDD5B Burst Refresh Current 195 195 203 203 mA 25 25 25 25 mA 30 30 30 30 mA 268 300 280 330 mA IDD6 IDD6ET IDD7 REV 1.1 07/ 2012 Self-Refresh Current: Normal Temperature Range (Tcase: 0-85C) Self-Refresh Current: Extended Temperature Range (Tcase: 0-95C) All Bank Interleave Read Current CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , 0 Symbol IDD0 IDD1 IDD2N IDD2P(0) IDD2P(1) IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC REV 1.1 07/ 2012 / Parameter/Condition Operating Current - One bank Active - Precharge current CKE: High; External clock: On; tCK, tRC, tRAS: see table in the next page; CS: High between ACT and PRE; Command Inputs: SWITCHING1 (except for ACT and PRE); Row, Column Address, Data I/O: SWITCHING1 (A10 Low permanently); Bank Address: fixed (Bank 0); Output Buffer: off 2; ODT: disabled 3; Active Banks: one (ACT-PRE loop); Idle Banks: all other; Pattern example: A0 D DD DD DD DD DD DD D P0.4 Operating One bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, tRC, tRAS, tRCD, CL, AL: see table in the next page; CS: High between 1 ACT, RD, and PRE; Command Inputs: SWITCHING (except ACT, RD, and PRE Commands); Row, Column Address: SWITCHING1 (A10 Low permanently); Bank Address: fixed (Bank 0); Data I/O: switching every clock 2 3 (RD Data stable during one Clock cycle); floating when no burst activity; Output Buffer: Off ; ODT: disabled ; Burst Length: BL85; Active Banks: one (ACT-RD-PRE loop); Idle Banks: all other; Pattern example: A0 D DD D 4 R0 DD DD DD DD D P0 . Precharge Standby Current CKE=High; External Clock=On; tCK: see table in the next page; CS: High; Command Inputs, Row, Column, 1 2 3 Bank Address, Data I/O: SWITCHING ; Output Buffer: Off ; ODT: disabled ; Active / Idle Banks: none / all. Precharge Power-Down Current - (Slow Exit) CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs: Stable; Row, Column / Bank Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: 6 none / all. Precharge Power Down Mode: Slow Exit (RD and ODT must satisfy tXPDLL - AL) Precharge Power-Down Current - (Fast Exit) CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs, Row, Column, 2 3 Bank Address: Stable; Data I/O: floating; Output Buffer: Off ; ODT: disabled ; Active / Idle Banks: none / all. 7 Precharge Power Down Mode: Fast Exit 6(any valid Command after tXP) Precharge Quiet Standby Current CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column, Bank Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled 3; Active / Idle Banks: none / all. Active Standby Current CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column, 1 3 Bank Address, Data I/O: SWITCHING ; Output Buffer: Off2; ODT: disabled ; Active / Idle Banks: All / none. Active Power-Down Current CKE=Low; External Clock=On; tCK: see table in the next page; CS, Command Inputs, Row, Column, Bank 3 Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled ; Active / Idle Banks: All / none. Operating Burst Read Current CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands; 1 1 Command Inputs: SWITCHING (except RD Commands); Row, Column Address: SWITCHING (A10: Low 10 permanently); Bank Address: cycling ; Data I/O: Seamless Read Data Burst : Output Data switches every 2 3 5 clock cycle (i.e. data stable during one clock cycle); Output Buffer: Off ; ODT: disabled ; Burst Length: BL8 ; 10 4 Active / Idle Banks: All / none ; Pattern: R0 D DD R1 D DD R2 D DD R3 D DD R4 Operating Burst Write Current CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands; 1 1 Command Inputs: SWITCHING (except WR Commands); Row, Column Address: SWITCHING (A10: Low 10 permanently); Bank Address: cycling ; Data I/O: Seamless Write Data Burst : Input Data switches every clock 2 3 cycle (i.e. data stable during one clock cycle); DM: L permanently; Output Buffer: Off ; ODT: disabled ; Burst 5 10 4 Length: BL8 ; Active / Idle Banks: All / none ; Pattern: W0 D DD W1 D DD W2 D DD W3 D DD W4 Burst Refresh Current CKE=High; External Clock=On; tCK, tRFC: see table in the next page; CS: High between valid Commands; Command Inputs, Row, Column, Bank Addresses, Data I/O: SWITCHING1; Output Buffer: Off2; ODT: disabled 3 ; Active Banks: Refresh Command every tRFC=tRFC(IDD); Idle banks: none. Self-Refresh Current 9 Tcase=0-85C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Normal ; CKE=Low; External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; 2 3 Output Buffer: off ; ODT: disabled ; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) Self-Refresh Current: extended temperature range 9 Tcase=0-95C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Extended ; CKE=Low; External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; Output Buffer: off 2; ODT: disabled 3; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) Auto Self-Refresh Current 8 9 Tcase=0-95C; Auto Self Refresh =Enable ; Self Refresh Temperature Range=Normal ; CKE=Low; External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 2 3 Output Buffer: off ; ODT: disabled ; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) Operating Bank Interleave Read Current CKE=High; External Clock=On; tCK, tRC, tRAS, tRCD, tRRD, CL: see table as below; AL=tRCD.min-tCK; CS=High between valid commands; Command Input: see table; Row, Column Address: Stable during IDD7 10 DESELECT; Bank Address: cycling ; Data I/O: Read Data: Output Data switches every clock cycle (i.e. data 2 3 10 stable during one clock cycle); Output Buffer: Off ;ODT: disabled ; Burst Length: BL8; Active / Idle Banks: All / none. Note1: SWITCHING for Address and Command Input Signals as described in Definition of SWITCHING for Address and Command Input Signals Table. Note2: Output Buffer off: set MR1 A[12] = 1 Note3: ODT disable: set MR1 A[9,6,2]=000 and MR2 A[10,9]=00 Note4: Definition of D and D: described in Definition of SWITCHING for Address and Command Input Signals Table; Ax/Rx/Wx: Activate/Read/Write to Bank x. Note5: BL8 fixed by MRS: set MR0 A[1,0]=00 Note6: Precharge Power Down Mode: set MR0 A12=0/1 for Slow/Fast Exit Note7: Because it is an exit after precharge power down, the valid commands are: ACT, REF, MRS, Enter Self-Refresh. Note8: Auto Self-Refresh(ASR): set MR2 A6 = 0/1 to disable/enable feature Note9: Self-Refresh Temperature Range (SRT): set MR2 A7 = 0/1 for normal/extended temperature range Note10: Cycle banks as follows: 0,1,2,3,...,7,0,1,... REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP , 6 "" 4 6 , 0 0 86 "3 /H "" 4 0 0 /G DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Parameter Symbol (-AC) (-AD) (-BE) (-CG) (-DI) (-EJ) -5-5-5 -6-6-6 -7-7-7 -9-9-9 2.5 1.875 1.5 1.25 1.07 0.935 ns -11-11-11 -12-12-12 (-FK) Unit -13-13-13 Clock Cycle Time tCKmin(IDD) CAS Latency CL(IDD) 5 6 7 9 11 12 13 nCK Active to Read or Write delay tRCDmin(IDD) 5 6 7 9 11 12 13 nCK tRCmin(IDD) 20 21 27 33 39 44 49 nCK 20 24 28 32 36 nCK 7 9 11 12 13 nCK 16 20 20 24 26 27 nCK 20 27 30 32 33 38 nCK 4 4 4 5 5 6 nCK 4 6 5 6 6 7 nCK 1Gb 44 59 74 88 103 118 tRFC(IDD) 2Gb 64 86 107 128 150 172 4Gb 120 160 200 240 281 321 Active to Active / Auto-Refresh command period Active to Precharge Command tRASmin(IDD) Precharge Command Period tRPmin(IDD) 1kB Four activate window 2kB Active to Active command period 1kB 2kB Auto-Refresh to Active / Auto-Refresh command period 15 5 6 tFAW(IDD) tRRD(IDD) 9 ,2 B,? // / 00 /, nCK " SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change Address then to the opposite value (row, column) (e.g. Ax Ax Ax Ax Ax Ax Ax Ax... Please see each IDDx definition for details If not otherwise mentioned the bank addresses should be switched like the row/column address - Bank Address please see each IDDx for details Command ( , , Define D = { , Define D = { , , , , } := {HIGH, LOW, LOW, LOW} , } := {HIGH, HIGH, HIGH, HIGH} Define Command Background Pattern = D D , ) DD DD .... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective , , , levels of the necessary command. See each IDDx definition for details. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP / / / $ & +7)) Speed Bin DDR3(L)-1066 CL-nRCD-nRP 7-7-7 (-BE) Parameter Symbol Min. Unit Max. Internal read command to first data tAA 13.125 20.0 ns ACT to internal read or write delay time tRCD 13.125 - ns PRE command period tRP 13.125 - ns ACT to ACT or REF command period tRC 50.625 - ns ACT to PRE command period tRAS 37.5 9*tREFI ns CWL=5 tCK(AVG) 3.0 3.3 ns CWL=6 tCK(AVG) Reserved CWL=5 tCK(AVG) 2.500 CWL=6 tCK(AVG) Reserved ns CWL=5 tCK(AVG) Reserved ns CWL=6 tCK(AVG) 1.875 CWL=5 tCK(AVG) Reserved CWL=6 tCK(AVG) 1.875 CL=5 CL=6 CL=7 CL=8 ns 3.3 ns <2.5 ns ns <2.5 ns Supported CL Settings 5,6,7,8 nCK Supported CWL Settings 5,6 nCK REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP $&+ Speed Bin DDR3(L)-1333 CL-nRCD-nRP 9-9-9 (-CG) Parameter Symbol Min. Unit Max. Internal read command to first data tAA 13.125 20.000 ns ACT to internal read or write delay time tRCD 13.125 - ns PRE command period tRP 13.125 - ns ACT to ACT or REF command period tRC 49.125 - ns ACT to PRE command period tRAS 36.000 9*tREFI ns CWL=5 tCK(AVG) 3.0 3.300 ns CWL=6,7 tCK(AVG) Reserved Reserved ns tCK(AVG) 2.500 3.300 ns tCK(AVG) Reserved Reserved ns CWL=7 tCK(AVG) Reserved Reserved ns CWL=5 tCK(AVG) Reserved Reserved ns CWL=6 tCK(AVG) 1.875* <2.5* ns CWL=7 tCK(AVG) Reserved Reserved ns CWL=5 tCK(AVG) Reserved Reserved ns CWL=6 tCK(AVG) 1.875 <2.5 ns CWL=7 tCK(AVG) Reserved Reserved ns CWL=5 tCK(AVG) Reserved Reserved ns CWL=6 tCK(AVG) Reserved Reserved ns CWL=7 tCK(AVG) 1.500 <1.875 ns CWL=5 tCK(AVG) Reserved Reserved ns CWL=6 tCK(AVG) Reserved Reserved ns CWL=7 tCK(AVG) 1.500* <1.875* ns CL=5 CL=6 CL=7 CL=8 CL=9 CL=10 CWL=5 CWL=6 Supported CL Settings 5,6,7,8,9,(10) nCK Supported CWL Settings 5,6,7 nCK REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP +)77 Speed Bin DDR3-1600 CL-nRCD-nRP 11-11-11 (-DI) Parameter Symbol Min. Unit Max. Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 - ns PRE command period tRP 13.125 - ns ACT to ACT or REF command period tRC 48.125 - ns ACT to PRE command period CWL=5 CL=5 CWL=6,7,8 CWL =5 tRAS tCK(AVG) tCK(AVG) tCK(AVG) 35 3.0 Reserved 2.5 9*tREFI 3.3 Reserved 3.3 ns ns ns ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.5 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.5 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) 1.250 <1.5 ns CL=6 CL=7 CL=8 CL=9 CL=10 CL=11 Supported CL Settings 5,6,7,8,9,10,(11) nCK Supported CWL Settings 5,6,7,8 nCK REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP +!)) Speed Bin DDR3-1866 CL-nRCD-nRP 12-12-12 (-EJ) Parameter Symbol Min Unit Max Internal read command to first data tAA 12.84 20.000 ns ACT to internal read or write delay time tRCD 12.84 - ns PRE command period tRP 12.84 - ns ACT to ACT or REF command period tRC 46.84 - ns ACT to PRE command period CL=5 CL=6 CL=7 CL=8 CL=9 CL=10 CL=11 CL=12 CL=13 tRAS 34.000 9*tREFI ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) 2.500 3.300 ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) 1.250 <1.5 ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 CWL=5,6,7,8 CWL=9 CWL=5,6,7,8 CWL=9 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.250* Reserved 1.07 Reserved 1.07 <1.5* Reserved <1.25 Reserved <1.25 ns ns ns ns ns Supported CL Settings 5,6,7,8,9,10,11,12,(13) nCK Supported CWL Settings 5,6,7,8,9 nCK REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP <+ Speed Bin DDR3-2133 CL-nRCD-nRP 13-13-13 (-FK) Parameter Symbol Min Unit Max Internal read command to first data tAA 12.155 20.000 ns ACT to internal read or write delay time tRCD 12.155 - ns PRE command period tRP 12.155 - ns ACT to ACT or REF command period tRC 45.155 - ns ACT to PRE command period CL=5 CL=6 CL=7 CL=8 CL=9 CL=10 CL=11 CL=12 CL=13 CL=14 tRAS 33.000 9*tREFI ns CWL =5 tCK(AVG) 2.500 3.300 ns CWL =6,7,8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) 2.500 3.300 ns CWL =6,7,8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) Reserved Reserved ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) 1.875 <2.5 ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) Reserved Reserved ns CWL =5 tCK(AVG) Reserved Reserved ns CWL =6 tCK(AVG) Reserved Reserved ns CWL =7 tCK(AVG) 1.500 <1.875 ns CWL =8 tCK(AVG) 1.250 <1.5 ns CWL =5,6,7 tCK(AVG) Reserved Reserved ns CWL =8 CWL=5,6,7,8 CWL=9 CWL=5,6,7,8 CWL=9 CWL=10 CWL=5,6,7,8,9 CWL=10 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.250* Reserved 1.07 Reserved 1.07 0.935 Reserved 0.935 <1.5* Reserved <1.25 Reserved <1.25 <1.07 Reserved <1.07 ns ns ns ns ns ns ns ns Supported CL Settings 5,6,7,8,9,10,11,12,13, (14) nCK Supported CWL Settings 5,6,7,8,9,10 nCK REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1" 20 " 6 0 I / Parameter 20 $ $ & +7))8+ Symbol Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Average low pulse width tCK (DLL_OFF) tCK(avg) tCH(avg) tCL(avg) Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width Absolute clock LOW pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles tCH(abs) tCL(abs) JIT(per) JIT(per, lck) tJIT(cc) Cumulative error across n = 13, 14 . . . 49, 50 cycles Data Timing DQS, DQS# to DQ skew, per group, per access DQ output hold time from DQS, DQS# DQ low-impedance time from CK, CK# DQ high impedance time from CK, CK# Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS,DQS# differential READ Preamble DQS, DQS# differential READ Postamble DQS, DQS# differential output high time DQS, DQS# differential output low time DQS, DQS# differential WRITE Preamble DQS, DQS# differential WRITE Postamble DQS, DQS# rising edge output access time from rising CK, CK# DQS and DQS# low-impedance time (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) REV 1.1 07/ 2012 tERR(nper) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) AC175/160 tDS(base) AC150/135 tDH(base) DC100/90 tDIPW DDR3(L)-1333 Min. Max. 8 8 Refer to "Standard Speed Bins) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 Min.: tCK(avg)min + tJIT(per)min Max.: tCK(avg)max + tJIT(per)max 0.43 0.43 0.43 0.43 -90 90 -80 80 -80 80 -70 70 180 160 JIT(cc, lck) tJIT(duty) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) & DDR3(L)-1066 Min. Max. 160 140 -132 132 -118 118 -157 157 -140 140 -175 175 -155 155 -188 188 -168 168 -200 200 -177 177 -209 209 -186 186 -217 217 -193 193 -224 224 -200 200 -231 231 -205 205 -237 237 -210 210 -242 242 -215 215 tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max 0.38 -600 - 150 300 300 0.38 -500 - 125 250 250 Units Note ns ps tCK(avg) tCK(avg) ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) ps ps ps See the page 131 ps ps 490 - 400 ps tRPRE tRPST tQSH tQSL tWPRE tWPST 0.9 0.3 0.38 0.38 0.9 0.3 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 0.3 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tDQSCK -300 300 -255 255 tCK(avg) tLZ(DQS) -600 300 -500 250 tCK(avg) tHZ(DQS) - 300 - 250 tCK(avg) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse width DQS, DQS# rising edge to CK, CK# rising edge DQS, DQS# falling edge setup time to CK, CK# rising edge DQS, DQS# falling edge hold time from CK, CK# rising edge Command and Address Timing DLL locking time tDQSL tDQSH tDQSS 0.45 0.45 -0.25 0.55 0.55 0.25 0.45 0.45 -0.25 0.55 0.55 0.25 tCK(avg) tCK(avg) tCK(avg) tDSS 0.2 - 0.2 - tCK(avg) tDSH 0.2 - 0.2 - tCK(avg) tDLLK Internal READ Command to PRECHARGE Command delay tRTP Delay from start of internal write transaction to internal read command tWTR WRITE recovery time Mode Register Set command cycle time tWR tMRD Mode Register Set command update delay tMOD ACT to internal read or write delay time PRE command period ACT to ACT or REF command period CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Control and Address Input pulse width for each input Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation Short calibration time Reset Timing tRCD tRP tRC tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW tIS(base) AC150/135 ns nCK nCK nCK nCK ns ns ps See the page 128 ps ps tIPW 780 - 620 - ps tZQinit tZQoper tZQCS 512 256 64 - 512 256 64 - nCK nCK nCK tXS Exit Self Refresh to commands requiring a tXSDLL locked DLL Minimum CKE low width for Self Refresh entry tCKESR to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) tCKSRE or Power-Down Entry (PDE) 07/ 2012 4 4 WR + roundup(tRP / tCK(avg)) 1 1 Standard Speed Bins tRRDmin.: max(4nCK, 6ns) tRRDmax.: tRRDmin.: max(4nCK, 7.5ns) tRRDmax.: 37.5 0 30 50 0 45 - tIH(base) DC100/90 Self Refresh Timings REV 1.1 nCK See the page 1 tIS(base) AC175/160 Exit Reset from CKE HIGH to a valid command tXPR Exit Self Refresh to commands not requiring a locked DLL 512 512 tWTRmin.: tRTPmin.: max(4nCK, max(4nCK, 7.5ns) 7.5ns) tWTRmax.: tRTPmax. tWTRmin.: tRTPmin.: max(4nCK, max(4nCK, 7.5ns) 7.5ns) tWTRmax.: tRTPmax. 15 15 4 4 tMODmin.: max(12nCK, 15ns) tMODmax.: tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPRmax.: TXSmin.: max(5nCK, tRFC(min) + 10ns) tXSmax.: tXSDLLmin.: tDLLK(min) nCK tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns) tCKSREmax.: - CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX Power Down Timings Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to tXP commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLL requiring a locked DLL CKE minimum pulse width tCKE Command pass disable delay tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry tACTPDEN Timing of PRE or PREA command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) tPRPDEN tRDPDEN tWRPDEN Timing of WRA command to Power Down entry tWRAPDEN (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry tWRPDEN (BC4MRS) Timing of WRA command to Power Down entry tWRAPDEN (BC4MRS) Timing of REF command to Power Down entry tREFPDEN Timing of MRS command to Power Down entry tMRSPDEN tCKSRXmin.: max(5 nCK, 10 ns) tCKSRXmax.: - tXPmin.: TXPmin.: max(3nCK, max(3nCK, 7.5ns) 6ns) tXPmax.: tXPmax.: tXPDLLmin.: max(10nCK, 24ns) tXPDLLmax.: tCKEmin.: tCKEmin.: max(3nCK ,5.625n max(3nCK ,5.6 s) 25ns) tCKEmax.: tCKEmax.: tCPDEDmin.: 1 tCPDEDmin.: TPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1 tACTPDENmax.: tPRPDENmin.: 1 tPRPDENmax.: tRDPDENmin.: RL+4+1 tRDPDENmax.: tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1 tWRAPDENmax.: tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDENmax.: tREFPDENmin.: 1 tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - nCK nCK nCK nCK nCK nCK nCK nCK nCK ODT Timings ODT turn on Latency ODTLon WL-2=CWL+AL-2 nCK ODT turn off Latency ODTLoff WL-2=CWL+AL-2 nCK ODT high time without write command or with write command and BC4 ODTH4 ODT high time with Write command and BL8 ODTH8 Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing REV 1.1 07/ 2012 ODTH4min.: 4 ODTH4max.: ODTH8min.: 6 ODTH8max.: - nCK nCK tAONPD 2 8.5 2 8.5 ns tAOFPD 2 8.5 2 8.5 ns tAON -300 300 -250 250 ps tAOF 0.3 0.7 0.3 0.7 tCK(avg) tADC 0.3 0.7 0.3 0.7 tCK(avg) tWLMRD 40 - 40 - nCK tWLDQSEN 25 - 25 - nCK tWLS 245 - 195 - ps CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP Write leveling hold time from rising DQS, DQS# tWLH crossing to rising CK, CK# crossing Write leveling output delay tWLO Write leveling output error tWLOE REV 1.1 07/ 2012 245 - 195 - ps 0 0 9 2 0 0 9 2 ns ns CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 1" 20 " 6 0 I / 20 $ +)778+!))8<+ DDR3/L-1600 Parameter Symbol & DDR3-1866 DDR3-2133 Min. Max. Min. Max. Min. Max. 8 - 8 - 8 - Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Average low pulse width tCK (DLL_OFF) tCK(avg) tCH(avg) tCL(avg) Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width Absolute clock LOW pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 . . . 49, 50 cycles Data Timing DQS, DQS# to DQ skew, per group, per access DQ output hold time from DQS, DQS# DQ low-impedance time from CK, CK# DQ high impedance time from CK, CK# Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS,DQS# differential READ Preamble DQS, DQS# differential READ Postamble DQS, DQS# differential output high time DQS, DQS# differential output low time DQS, DQS# differential WRITE Preamble DQS, DQS# differential WRITE Postamble DQS, DQS# rising edge output access time from rising CK, CK# DQS and DQS# low-impedance time tCH(abs) tCL(abs) JIT(per) Refer to "Standard Speed Bins) 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 Min.: tCK(avg)min + tJIT(per)min Max.: tCK(avg)max + tJIT(per)max 0.43 0.43 0.43 0.43 0.43 0.43 -70 70 -60 60 -50 JIT(per, lck) -60 REV 1.1 07/ 2012 0.47 0.47 60 50 -50 0.53 0.53 Units ns ps tCK(avg) tCK(avg) ps -40 50 tCK(avg) tCK(avg) ps 40 ps tJIT(cc) 140 120 100 ps JIT(cc, lck) 120 100 80 ps tJIT(duty) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) AC175/160 tDS(base) AC150/135 tDH(base) DC100/90 -103 103 -88 88 -74 74 -122 122 -105 105 -87 87 -136 136 -117 117 -97 97 -147 147 -126 126 -105 105 -155 155 -133 133 -111 111 -163 163 -139 139 -116 116 -169 169 -145 145 -121 121 -175 175 -150 150 -125 125 -180 180 -154 154 -128 128 -184 184 -158 158 -132 132 -188 188 -161 161 -134 134 tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps ps ps ps ps ps ps ps ps ps ps ps ps - 100 - 85 - 75 ps 0.38 -450 - 225 225 0.38 -390 - 195 195 0.38 -360 - 180 180 tCK(avg) ps ps ps See the page 131 ps ps tDIPW 360 - 320 - 280 - ps tRPRE tRPST tQSH tQSL tWPRE 0.9 0.3 0.4 0.4 0.9 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tWPST 0.3 - 0.3 - 0.3 - tCK(avg) tDQSCK -225 225 -195 195 -180 180 tCK(avg) tLZ(DQS) -450 225 -390 195 -360 180 tCK(avg) CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved N o t e NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse width DQS, DQS# rising edge to CK, CK# rising edge DQS, DQS# falling edge setup time to CK, CK# rising edge DQS, DQS# falling edge hold time from CK, CK# rising edge Command and Address Timing DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay ACT to internal read or write delay time PRE command period ACT to ACT or REF command period CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Control and Address Input pulse width for each input Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation Short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self Refresh REV 1.1 07/ 2012 tHZ(DQS) - 225 - 195 - 180 tCK(avg) tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK(avg) tDSS 0.18 - 0.18 - 0.18 - tCK(avg) tDSH 0.18 - 0.18 - 0.18 - tCK(avg) 512 - 512 - 512 - nCK tWTRmin.: max(4nCK, 7.5ns) tWTRmax.: 15 15 4 4 tMODmin.: max(12nCK, 15ns) tMODmax.: 15 4 - ns nCK 4 - nCK tDLLK tRTPmin.: max(4nCK, 7.5ns) tRTPmax.: - tRTP tWTR tWR tMRD tMOD tRCD tRP tRC tCCD See the page 1 4 tDAL(min) tMPRR 1 tRAS - 4 - WR + roundup(tRP / tCK(avg)) - 1 nCK - 1 - nCK tRRDmin.: max(4nCK, 6ns) tRRDmax.: tRRDmin.: max(4nCK, 7.5ns) tRRDmax.: 30 0 27 40 0 35 - 25 35 - ns ns Standard Speed Bins tRRD tRRD tFAW tFAW tIS(base) AC175/160 tIH(base) AC150/135 ps See the page128 ps tIS(base) DC100/90 ps tIPW 560 - 535 - 470 - ps tZQinit tZQoper tZQCS 512 256 64 - 512 256 64 - 512 256 64 - nCK nCK nCK tXPR tXS tXSDLL tCKESR tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPRmax.: tXSmin.: max(5nCK, tRFC(min) + 10ns) tXSmax.: tXSDLLmin.: tDLLK(min) tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK nCK CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) tCKESRmax.: tCKSRE tCKSREmin.: max(5 nCK, 10 ns) tCKSREmax.: - Valid Clock Requirement before Self Refresh Exit (SRX) tCKSRX or Power-Down Exit (PDX) or Reset Exit tCKSRXmin.: max(5 nCK, 10 ns) tCKSRXmax.: - Power Down Timings Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL tXP frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL CKE minimum pulse width tCKE Command pass disable delay tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry Timing of PRE or PREA command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timings ODT turn on Latency ODT turn off Latency tXPmin.: max(3nCK, 6ns) tXPmax.: tXPDLLmin.: max(10nCK, 24ns) tXPDLLmax.: - tACTPDEN tPRPDEN tRDPDEN tWRPDEN tCKEmin.: max(3nCK ,5ns) tCKEmax.: tCPDEDmin.: 2 tCPDEDmin.: tPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1, (2 for 2133) tACTPDENmax.: tPRPDENmin.: 1 (2 for 2133) tPRPDENmax.: tRDPDENmin.: RL+4+1 tRDPDENmax.: tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDENmax.: - nCK nCK nCK nCK nCK tWRAPDEN tWRAPDENmin.: WL+4+WR+1 tWRAPDENmax.: - nCK tWRPDEN tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: - nCK tWRAPDEN tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDENmax.: - nCK tREFPDEN tMRSPDEN nCK WL-2=CWL+AL-2 WL-2=CWL+AL-2 nCK nCK ODT high time without write command or ODTH4 with write command and BC4 ODTH4min.: 4 ODTH4max.: - nCK ODT high time with Write command and BL8 Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed ODTH8min.: 6 ODTH8max.: - nCK REV 1.1 07/ 2012 ODTLon ODTLoff tREFPDENmin.: 1 (2 for 2133) tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - ODTH8 tAONPD tAOFPD 2 8.5 2 8.5 2 8.5 ns 2 8.5 2 8.5 2 8.5 ns tAON -225 225 -195 195 -180 180 ps tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) tWLMRD 40 - 40 - 40 - nCK CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing Write leveling output delay Write leveling output error REV 1.1 07/ 2012 tWLDQSEN 25 - 25 - 25 - nCK tWLS 165 - 140 - 125 - ps tWLH 165 - 140 - 125 - ps 0 0 7.5 2 0 0 7.5 2 0 0 7.5 2 ns ns tWLO tWLOE CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP M ? Specific Note a Unit "tCK(avg)" represents the actual tCK(avg) of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is registered at Tm, anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) + tERR(4per), min. Specific Note b These parameters are measured from a command/address signal (CKE, , , , , ODT, BA0, A0, A1, etc) transition edge to its respective clock signal (CK/ ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), )) crossing to its respective clock signal (CK, ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), ) crossing. Specific Note e For these parameters, the DDR3(L) SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-1066 7-7-7, of which tRP = 13.125ns, the device will support tnRP = RU{tRP/tCK(avg)} = 7, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7-Tm) is less than 13.125ns due to input clock jitter. Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of the input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.) Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (Output deratings are relative to the SDRAM input clock.) REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 20 0 ? 1. Actual value dependent upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rouned-up to next higher integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT-on time tAON See "Timing Parameters". 8. For definition of RTT-off time tAOF See "Timing Parameters". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles are programmed in MR0. 11. The maximum read postamble is bounded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. 15. tREFI depends on TOPER. 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC). 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC). 18. Start of internal write transaction is defined as follows: For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL. 19. The maximum preamble is bound by tLZ (DQS) max on the left side and tDQSCK(max) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN (min) is satisfied, there are cases where additional time such as tXPDLL (min) is also required. 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the "Output Driver Voltage and Temperature Sensitivity" and "ODT Voltage and Temperature Sensitivity" tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the following formula: ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)] where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters. 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV - 150mV) / 1V/ns]. // - 00 / 8B "/8 / For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `Vref(dc) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `Vref(dc) to ac region', the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc to Vref(dc) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to Vref(dc) region', the slew rate of a tangent line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP - / B "/ Unit [ps] reference ; " +;- DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 (-BE) (-CG) (-DI) (-EJ) (-FK) Units 1.5V tIS(base) AC175 VIH/L(ac) 125 65 45 - - ps tIS(base) AC150 VIH/L(ac) 275 190 170 - - ps ftIH(base) DC100 VIH/L(dc) 200 140 120 ps 1.35V tIS(base) AC160 VIH/L(ac) 140 80 60 ps tIS(base) AC135 VIH/L(ac) 290 205 185 ps tIH(base) DC90 VIH/L(dc) 210 150 130 ps Note: 1. (ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate. 2. The tIS(base) AC150 (AC135) specifications are adjusted from the tIS(base) specification by adding an additional 100ps (125ps for DDR3L -1066 or 100ps for DDR3L-1333/1600) of derating to accommodate for the lower alternate threshold of 150mV (135Mv) and another 25ps to account for the earlier reference point [(175mV150mV) / 1V/ns or [(160mV - 135mV) / 1V/ns]. REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP CMD/ADD Slew rate (V/ns) : " 4.0 V/ns D tIS D tIH 88 50 59 34 0 0 -2 -4 -6 -10 -11 -16 -17 -26 -35 -40 -62 -60 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 +7))-+ 3.0 V/ns D tIS D tIH 88 50 59 34 0 0 -2 -4 -6 -10 -11 -16 -17 -26 -35 -40 -62 -60 CMD/ADD Slew rate (V/ns) : " 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns D tIS D tIH 80 45 53 30 0 0 -1 -3 -3 -8 -5 -13 -8 -20 -20 -30 -40 -45 C M D /AD D Slew rate (V/ns ) : " 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns D tIS D tIH 75 50 50 34 0 0 0 -4 0 -10 0 -16 -1 -26 -10 -40 -25 -60 REV 1.1 07/ 2012 Delta tIS, Delta tIH derating in AC/DC based CK, CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH 88 50 96 58 104 66 112 74 59 34 67 42 75 50 83 58 0 0 8 8 16 16 24 24 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 -11 -16 -3 -8 5 0 13 8 -17 -26 -9 -18 -1 -10 7 -2 -35 -40 -27 -32 -19 -24 -11 -16 -62 -60 -54 -52 -46 -44 -38 -36 +7))-+ 3.0 V/ns D tIS D tIH 80 45 53 30 0 0 -1 -3 -3 -8 -5 -13 -8 -20 -20 -30 -40 -45 1.2 V/ns D tIS D tIH 120 84 91 68 32 34 30 30 26 24 21 18 15 8 -2 -6 -30 -26 1.0 V/ns D tIS D tIH 128 100 99 84 40 50 38 46 34 40 29 34 23 24 5 10 -22 -10 1.2 V/ns D tIS D tIH 112 79 85 64 32 34 31 31 29 27 27 21 24 14 12 4 -8 -11 1.0 V/ns D tIS D tIH 120 95 93 80 40 50 39 47 37 43 35 37 32 30 20 20 0 5 -+)77 , - ,B ' $ +)7& Delta tIS, Delta tIH derating in AC/DC based CK, CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH 80 45 88 53 96 61 104 69 53 30 61 38 69 46 77 54 0 0 8 8 16 16 24 24 -1 -3 7 5 15 13 23 21 -3 -8 5 1 13 9 21 17 -5 -13 3 -5 11 3 19 11 -8 -20 0 -12 8 -4 16 4 -20 -30 -12 -22 -4 -14 4 -6 -40 -45 -32 -37 -24 -29 -16 -21 +7))-+ 3.0 V/ns D tIS D tIH 75 50 50 34 0 0 0 -4 0 -10 0 -16 -1 -26 -10 -40 -25 -60 -+)77 , - ,B ' $ + D& -+)77 , - ,B ' $ +D7& Delta tIS, Delta tIH derating in AC/DC based CK,CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH 75 50 83 58 91 66 99 74 50 34 58 42 66 50 74 58 0 0 8 8 16 16 24 24 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 0 -16 8 -8 16 0 24 8 -1 -26 7 -18 15 -10 23 -2 -10 -40 -2 -32 6 -24 14 -16 -25 -60 -17 -52 -9 -44 -1 -36 1.2 V/ns D tIS D tIH 107 84 82 68 32 34 32 30 32 24 32 18 31 8 22 -6 7 -26 1.0 V/ns D tIS D tIH 115 100 90 84 40 50 40 46 40 40 40 34 39 24 30 10 15 -10 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP C M D /AD D Slew rate (V/ns ) : " 4.0 V/ns D tIS D tIH 68 45 45 30 0 0 2 -3 3 -8 6 -13 9 -20 5 -30 -3 -45 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 / 0 Slew Rate [V/ns] +7))-+ 3.0 V/ns D tIS D tIH 68 45 45 30 0 0 2 -3 3 -8 6 -13 9 -20 5 -30 -3 -45 -+)77 , - ,B ' $ + D& Delta tIS, Delta tIH derating in AC/DC based CK, CK# Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tIS D tIH D tIS D tIH D tIS D tIH D tIS D tIH 68 45 76 53 84 61 92 69 45 30 53 38 61 46 69 54 0 0 8 8 16 16 24 24 2 -3 10 5 18 13 26 21 3 -8 11 1 19 9 27 17 6 -13 14 -5 22 3 30 11 9 -20 17 -12 25 -4 33 4 5 -30 13 -22 21 -14 29 -6 -3 -45 6 -37 14 -29 22 -21 : ;,B$ & N " 4 ;, $ &O ; tVAC@175mV [ps] tVAC@160mV [ps] 1.2 V/ns D tIS D tIH 100 79 77 64 32 34 34 31 35 27 38 21 41 14 37 4 30 -11 1.0 V/ns D tIS D tIH 108 95 85 80 40 50 42 47 43 43 46 37 49 30 45 20 38 5 - tVAC@150mV [ps] tVAC@135mV [ps] Min. Max. Min. Max. Min. Max. Min. Max. >2.0 75 - TBD - 175 - TBD - 2 57 - TBD - 170 - TBD - 1.5 50 - TBD - 167 - TBD - 1 38 - TBD - 163 - TBD - 0.9 34 - TBD - 162 - TBD - 0.8 29 - TBD - 161 - TBD - 0.7 22 - TBD - 159 - TBD - 0.6 13 - TBD - 155 - TBD - 0.5 0 - TBD - 150 - TBD - <0.5 0 - TBD - 150 - TBD - REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP 8B "/8 / " 4 For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base) and tDH(base) value to the delta tDS and delta tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + delta tDS Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `Vref(dc) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `Vref(dc) to ac region', the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc level to Vref(dc) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to Vref(dc) region', the slew rate of a tangent line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. ! " Unit [ps] reference #$ ! DDR3-1066 DDR3-1333 DDR3-1600 (-BE) (-CG) (-DI) DDR3-1866 DDR3-2133 (-EJ) (-FK) Units 1.5V tDS(base) AC175 VIH/L(ac) 25 - - ps tDS(base) AC 150 VIH/L(ac) 75 30 10 ps tDS(base) AC 135 VIH/L(ac) tDH(base) DC100 VIH/L(dc) 100 65 45 TBD TBD TBD TBD ps 1.35V tDS(base) AC160 VIH/L(ac) 40 - - ps tDS(base) AC135 VIH/L(ac) 90 45 25 ps tDH(base) DC 90 VIH/L(dc) 110 75 55 ps Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP D Q Slew rate (V/ns) : " 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 D Q Slew rate (V/ns) - B ' $ + D& +7)) - B ' $ +)7& Delta tDS, Delta tDH derating in AC/DC based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 80 45 80 45 80 45 53 30 53 30 53 30 61 38 0 0 0 0 0 0 8 8 16 16 -1 -3 -1 -3 7 5 15 13 23 21 -3 -8 5 1 13 9 21 17 29 27 3 -5 11 3 19 11 27 21 35 37 8 -4 16 4 24 14 32 30 4 -6 12 4 20 20 -8 -11 0 5 : " D Q Slew rate (V/ns) -+)77 Delta tDS, Delta tDH derating in AC/DC based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 88 50 88 50 88 50 59 34 59 34 59 34 67 42 0 0 0 0 0 0 8 8 16 16 -2 -4 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 26 24 -3 -8 5 0 13 8 21 18 29 34 -1 -10 7 -2 15 8 23 24 -11 -16 -2 -6 5 10 -30 -26 -22 -10 : " 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 +7))-+ 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 REV 1.1 07/ 2012 +7))-+ -+)77 - B ' $ +D7& Delta tDS, Delta tDH derating in AC/DC based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 75 50 75 50 75 50 50 34 50 34 50 34 58 42 0 0 0 0 0 0 8 8 16 16 0 -4 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 32 24 8 -8 16 0 24 8 32 18 40 34 15 -10 23 -2 31 8 39 24 14 -16 22 -6 30 10 7 -26 15 -10 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP D Q Slew rate (V/ns) : " +7))-+ -+)77 - B ' $ + D& Delta tDS, Delta tDH derating in AC/DC based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 68 45 68 45 68 45 45 30 45 30 45 30 53 38 0 0 0 0 0 0 8 8 16 16 2 -3 2 -3 10 5 18 13 26 21 3 -8 11 1 19 9 27 17 35 27 14 -5 22 3 30 11 38 21 46 37 25 -4 33 4 41 14 49 30 29 -6 37 4 45 20 30 -11 38 5 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 / 0 : ;,B$ & N " 4 ;, $ &O ; : "/ J DDR3-1066 (AC175) DDR3L-1066 (AC160) DDR3-1333/1600 (AC150) DDR3(L)-1333/1600 (AC135) Slew Rate [V/ns] tVAC[ps] tVAC[ps] tVAC[ps] tVAC[ps] Min. Max. Min. Max. Min. Max. Min. Max. >2.0 75 - TBD - 175 - TBD - 2 57 - TBD - 170 - TBD - 1.5 50 - TBD - 167 - TBD - 1 38 - TBD - 163 - TBD - 0.9 34 - TBD - 162 - TBD - 0.8 29 - TBD - 161 - TBD - 0.7 22 - TBD - 159 - TBD - 0.6 13 - TBD - 155 - TBD - 0.5 0 - TBD - 155 - TBD - <0.5 0 - TBD - 150 - TBD - REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP # 0 (x8; 78 balls; 0.8mmx0.8mm Pitch; BGA) BOTTOM VIEW TOP VIEW 6.4 0.8 10.0 +/- 0.1 Pin A1 Index 9.6 12.0 +/- 0.1 0.8 Pin A1 Index 78Balls Min. 0.40 Max. 0.50 Min. 0.25 Max. 0.40 Max. 1.20 Units: mm REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP # 0 (x16; 96 balls; 0.8mmx0.8mm Pitch; BGA) BOTTOM VIEW TOP VIEW 6. 4 10.0 +/- 0 .1 0 .8 Pin A 1 Index 12 1 3 . 0 + /- 0 .1 0 .8 Pin A 1 Index 96 Balls Min. 0 . 42 Max. 0 .52 Min. 0 . 30 Max. 0 .40 Max . 1.20 Units : mm REV 1.1 07/ 2012 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved NT5CB512M8BN / NT5CB256M16BP NT5CC512M8BN / NT5CC256M16BP : Rev Date 1.0 2/2012 Official Release 1.1 7/2012 Deleted the part number of 1.5V DDR3-1866 and added the part number of I-Temp on page 9 REV 1.1 07/ 2012 Modification CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved