www.fairchildsemi.com
Rev. 1.07 12/8/04
Features
• 10-bit resolution
•150 megapixels per second
•± 0.1% linearity error
• Sync and blank controls
• 1.0V p-p video into 37.5
Ω
or 75
Ω
load
•Internal bandgap voltage reference
• Double-buffered data for low distortion
• TTL-compatible inputs
•Low glitch energy
• Single +5 Volt power supply
Applications
•Video signal conversion
– RGB
– YC
B
C
R
– Composite, Y, C
• Multimedia systems
• Image processing
•True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Description
FMS3110/3115 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5
Ω
loads corresponding to doubly-terminated
50–75
Ω
loads. A sync current following SYNC input timing
is added to the I
OG
output. BLANK will override RGB
inputs, setting I
OG
, I
OB
and I
OR
currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the V
REF
input.
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
FMS3110 100 Ms/s
FMS3115 150 Ms/s
Block Diagram
10 bit D/A
Converter
SYNC
10
SYNC
CLOCK
G9-0
COMP
+1.235V
Ref
IOG
BLANK
10 bit D/A
Converter
10
B9-0 IOB
10 bit D/A
Converter
10
R9-0 IOR
RREF
VREF
FMS3110/3115
Triple Video D/A Converters
3 x 10 bit, 150 Ms/s
FMS3110/3115 DATA SHEET
2
REV. 1.07 12/8/04
Functional Description
Within the FMS3110/3115 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB
7-0
are overridden by the BLANK input. SYNC
= H activates, sync current from I
OS
for sync-on-green video
signals.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes t
DO
after the rising
edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Figure 1. Nominal Output Levels
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R
REF
and GND.
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
The FMS3110/3115 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
R
REF
should be doubled.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3K
Ω
source resistance. An external
voltage reference may be connected to the V
REF
pin,
overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and V
DD
to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be connected
to V
DD
pins with 0.1 and 0.01 µF decoupling capacitors
placed adjacent to each V
DD
pin or pin pair.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic
distortion or reduced signal-to-noise performance. All
ground pins should be connected to a common solid ground
plane for best performance.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
DATA SHEET FMS3110/3115
Rev. 1.07 12/8/04
3
Table 1. Output Voltage Versus Input Code, SYNC and BLANK
V
REF
= 1.235 V, R
REF
= 590
Ω
, R
L
= 37.5
Ω
Pin Assignments
RGB
9-0
(MSB…LSB)
Blue and Red D/As Green D/A
SYNC BLANK V
OUT
SYNC BLANK V
OUT
11 1111 1111 X 1 0.7140 1 1 1.0000
11 1111 1111 X 1 0.7140 0 1 0.7140
11 1111 1110 X 1 0.7134 1 1 0.9994
11 1111 1101 X 1 0.7127 1 1 0.9987
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 0000 0000 X 1 0.3843 1 1 0.6703
01 1111 1111 X 1 0.3837 1 1 0.6697
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010 X 1 0.0553 1 1 0.3413
00 0000 0001 X 1 0.0546 1 1 0.3406
00 0000 0000 X 1 0.0540 1 1 0.3400
XX XXXX XXXX X 0 0.0000 1 0 0.2860
XX XXXX XXXX X 0 0.0000 0 0 0.0000
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
VDD
R2
R1
NC
RREF
VREF
COMP
IOG
IOR
OVDD
VDD
IOB
GND
GND
NC
G0
R9
R8
R7
R6
R5
R4
R3
NC
B0
B1
B2
B3
B4
B6
B5
NC
1
2
3
4
5
6
7
8
9
10
SYNC 11
12
36
35
34
33
32
31
30
29
28
27
CLOCK
26
25
13
14
15
16
17
18
19
20
21
22
B7
B8
B923
24
48
47
46
45
44
43
42
41
40
39
R0
38
37
LQFP
FMS3110/3115
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
VDD
R2
R1
NC
RREF
VREF
COMP
IOG
IOR
VDD
VDD
IOB
GND
GND
NC
G0
R9
R8
R7
R6
R5
R4
R3
NC
B0
B1
B2
B3
B4
B6
B5
NC
1
2
3
4
5
6
7
8
9
10
SYNC 11
12
36
35
34
33
32
31
30
29
28
27
CLOCK
26
25
13
14
15
16
17
18
19
20
21
22
B7
B8
B923
24
48
47
46
45
44
43
42
41
40
39
R0
38
37
LQFP
FMS3110/3115
FMS3110/3115 DATA SHEET
4
Rev. 1.07 12/8/04
Pin Descriptions
Pin Name Pin Number Value Description
Clock and Pixel I/O
CLK 26 TTL
Clock Input.
The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R
9-0
47-37 TTL
Red Pixel Data Inputs.
TTL-compatible Red Data Inputs are
registered on the rising edge of CLK.
G
9-0
48, 9–1 TTL
Green Pixel Data Inputs.
TTL-compatible Green Data Inputs are
registered on the rising edge of CLK.
B
9-0
23–14 TTL
Blue Pixel Data Inputs.
TTL-compatible Blue Data Inputs are
registered on the rising edge of CLK.
Controls
SYNC 11 TTL
Sync Pulse Input.
Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on the Green D/A converter
output. SYNC is registered on the rising edge of CLK with the same
pipeline latency as BLANK and pixel data. SYNC does not override
any other data and should be used only during the blanking interval.
Since this is a single-supply D/A and all signals are positive-going,
sync is added to the bottom of the Green D/A range. So turning SYNC
OFF means turning the current source ON. When a sync pulse is
desired, the current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC should be
connected to GND.
BLANK 10 TTL
Blanking Input.
When BLANK is LOW, pixel inputs are ignored and
the D/A converter outputs fall to the blanking level. BLANK is
registered on the rising edge of CLK and has the same pipeline
latency as SYNC.
Video Outputs
IO
R
33 0.714 V
p-p
Red Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
IO
G
32 1 V
p-p
Green Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines. Sync pulses may be
added to the Green D/A output.
IO
B
29 0.714 V
p-p
Blue Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
DATA SHEET FMS3110/3115
Rev. 1.07 12/8/04
5
Voltage Reference
V
REF
35 +1.235 V
Voltage Reference Output/Input.
An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt reference
may be applied here which overrides the internal reference.
Decoupling V
REF
to GND with a 0.1µF ceramic capacitor is required.
R
REF
36 560
Ω
Current-Setting Resistor.
Full-scale output current of each D/A
converter is determined by the value of the resistor connected
between R
REF
and GND. Nominal value of R
REF
is found from:
R
REF
= 9.1 (V
REF
/I
FS
)
where I
FS
is the full-scale (white) output current (in amps) from the
D/A converter (without sync). Sync is 0.4 * I
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the white voltage level and R
L
is the total resistive load
(in ohms) on each D/A converter. V
FS
is the blank to full-scale
voltage.
COMP 34 0.1 µF
Compensation Capacitor.
A 0.1 µF ceramic capacitor must be
connected between COMP and V
DD
to stabilize internal bias circuitry.
Power and Ground
V
DD
12, 30, 31 +5 V
Power Supply.
GND 27, 28 0.0V
Ground.
Pin Descriptions
(continued)
Pin Name Pin Number Value Description
Equivalent Circuits
Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit
Digital
Input
VDD
p
n
GND
VDD
VDD
np
GND
OUT
FMS3110/3115 DATA SHEET
6
REV. 1.07 12/8/04
Equivalent Circuits
(continued)
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Parameter Min Typ Max Unit
Power Supply Voltage
V
DD
(Measured to GND) -0.5 7.0 V
Inputs
Applied Voltage (measured to GND)
2
-0.5 V
DD
+ 0.5 V
Forced Current
3,4
-10.0 10.0 mA
Outputs
Applied Voltage (measured to GND)
2
-0.5 V
DD
+ 0.5 V
Forced Current
3,4
-60.0 60.0 mA
Short Circuit Duration (single output in HIGH state to ground) Infinite second
Temperature
Operating, Ambient -20 110 °C
Junction 150 °C
Lead Soldering (10 seconds) 300 °C
Vapor Phase Soldering (1 minute) 220 °C
Storage -65 150 °C
p
GND 27012B
RREF
VREF
VDD
p
DATA SHEET FMS3110/3115
Rev. 1.07 12/8/04 7
Operating Conditions
Electrical Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. Minimum/Maximum values with VDD = Max and TA = Min.
3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 540Ω
Parameter Min Nom Max Units
VDD Power Supply Voltage 4.75 5.0 5.25 V
fSConversion Rate FMS3110 100 Msps
FMS3115 150 Msps
tPWH CLK Pulsewidth, HIGH FMS3110 3.1 ns
FMS3115 2.5 ns
tPWL CLK Pulsewidth, LOW FMS3110 3.1 ns
FMS3115 2.5 ns
tWCLK Pulsewidth FMS3110 10 ns
FMS3115 6.6 ns
tSInput Data Setup Time 1.7 ns
thInput Date Hold Time 0 ns
VREF Reference Voltage, External 1.0 1.235 1.5 V
CCCompensation Capacitor 0.1 µF
RLOutput Load 37.5 Ω
VIH Input Voltage, Logic HIGH 2.0 VDD V
VIL Input Voltage, Logic LOW GND 0.8 V
TAAmbient Temperature, Still Air 0 70 °C
Parameter Conditions3Min Typ1Max Units
IDD Power Supply Current2VDD = Max 125 mA
PD Total Power Dissipation2VDD = Max 655 mW
ROOutput Resistance 100 kΩ
COOutput Capacitance IOUT = 0mA 30 pF
IIH Input Current, HIGH VDD = Max, VIN = 2.4V -5 µA
IIL Input Current, LOW VDD = Max, VIN = 0.4V 5 µA
IREF VREF Input Bias Current 0 ±100 µA
VREF Reference Voltage Output 1.235 V
VOC Output Compliance Referred to VDD -0.4 0 +1.5 V
CDI Digital Input Capacitance 4 10 pF
FMS3110/3115 DATA SHEET
8Rev. 1.07 12/8/04
Switching Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
System Performance Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 590Ω.
Timing Diagram
Parameter Conditions2Min Typ1Max Units
tDClock to Output Delay VDD = Min 10 15 ns
tSKEW Output Skew 1 2 ns
tROutput Risetime 10% to 90% of Full Scale 3 ns
tFOutput Falltime 90% to 10% of Full Scale 3 ns
Parameter Conditions2Min Typ1Max Units
ELI Integral Linearity Error VDD, VREF = Nom ±0.1 ±0.25 %/FS
ELD Differential Linearity Error VDD, VREF = Nom ±0.1 ±0.25 %/FS
EDM DAC to DAC Matching VDD, VREF = Nom 3 10 %
PSR Power Supply Rejection Ratio 0.05 %/%
CLK
PIXEL DATA
& CONTROLS
OUTPUT
DataN DataN+1 DataN+2
tPWL
tS
tH
50%
3%/FS
90%
10%
tDtSET tFtR
tPWH 1/fS
DATA SHEET FMS3110/3115
REV. 1.07 12/8/04 9
Applications Discussion
Figure 5 illustrates a typical FMS3110/3115 interface cir-
cuit. In this example, an optional 1.2 Volt bandgap reference
is
connected to the VREF output, overriding the internal volt-
age reference source.
Grounding
It is important that the FMS3110/3115 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video sig-
nals at the output of the circuit. The FMS3110/3115 has sep-
arate analog and digital circuits. To keep digital system noise
from the D/A converter, it is recommended that power supply
voltages (VDD) come from the system analog power source
and all ground connections (GND) be made to the analog
ground plane. Power supply pins should be individually
decoupled at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following sug-
gestions when doing the layout:
1. Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as possi-
ble from all digital signals. The FMS3110/3115 should
be located near the board edge, close to the analog out-
put connectors.
2. Power plane for the FMS3110/3115 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the VDD pins. If
the power supply for the FMS3110/3115 is the same as
that of the system's
digital circuitry, power to the FMS3110/3115 should be
decoupled with 0.1µF and 0.01µF capacitors and iso-
lated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3110/3115,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3110/3115 and its related analog circuitry can
have an adverse effect on performance.
5. CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Related Products
• FMS38XX Triple 8-bit 150 Msps D/A Converters
• FMS9884A 3 x 8-bit 140 Ms/s A/D Converter
Figure 5. Typical Interface Circuit
R9-0
G9-0
B9-0
+5V
0.1µF
10µF
VDD GND
FMS31XX
Triple 10-bit
D/A Converter
CLK
SYNC
BLANK
RED PIXEL
INPUT
GREEN PIXEL
INPUT
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
COMP
VREF
RREF
+5V
0.1µF
0.1µF
560Ω
3.3kΩ (not required without
external reference)
LM185-1.2
(Optional)
IOR
IOG
IOB
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
ZO=75Ω
Red
Green w/Sync
Blue
ZO=75Ω
ZO=75Ω
FMS3110/3115 DATA SHEET
10 REV. 1.07 12/8/04
Mechanical Dimensions
48-Lead LQFP Package
D
E1
E
e
PIN 1
IDENTIFIER
B
Base Plane
Seating Plane
See Lead Detail
C
0.063" Ref (1.60mm)
L
-C-
ccc C
LEAD COPLANARITY
A2
A
A1
α
A .055 .063 1.40 1.60
Symbol Inches
Min. Max. Min. Max.
Millimeters Notes
A1 .001 .005 .05 .15
.057 1.45
A2 .053 1.35
B .006 .010 .17 .27
D/E
D1/E1
.019 BSC
.346 .362 8.8 9.2
.268 .284 6.8 7.2
.50 BSC
e
L .017 .029 .45 .75 6
4
5
2
7
8
α0°7°0°7°
N48 48
12 12
ND
ccc .004 0.08
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
D1
All dimensions and tolerances conform to ANSI Y14.5M-1982.
Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
Pin 1 identifier is optional.
Dimension ND: Number of terminals.
Dimension ND: Number of terminals per package edge.
"L" is the length of terminal for soldering to a substrate.
Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
To be determined at seating place —C—
FMS3110/3115 DATA SHEET
2004 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Ordering Information
Product Number
Conversion
Rate
Lead
Free
Temperature
Range Screening Package
Package
Marking
FMS3110KRC 100 Ms/s 0°C to 70°C Commercial 48-Lead LQFP 3110KRC
FMS3110KRC_NL 100 Ms/s Yes 0°C to 70°C Commercial 48-Lead LQFP 3110KRC_NL
FMS3115KRC 150 Ms/s 0°C to 70°C Commercial 48-Lead LQFP 3115KRC
