Datasheet RL78/G14 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 RENESAS MCU True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 256 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology * 1.6 V to 5.5 V operation from a single supply * Stop (RAM retained): 0.24 A, (LVD enabled): 0.32 A * Halt (RTC + LVD): 0.60 A * Snooze: 0.70 mA (UART), 1.20 mA (ADC) * Operating: 66 A/MHz Data Transfer Controller (DTC) * 39 sources & 24 different settings * Transfer data: 8 bits/16 bits * Normal mode and repeat mode 16-bit RL78 CPU Core * Delivers 44 DMIPS at maximum operating frequency of 32 MHz * Instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles * CISC architecture (Harvard) with 3-stage pipeline * Multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle * MAC: 16 x 16 to 32-bit result in 2 clock cycles * 16-bit barrel shifter for shift & rotate in 1 clock cycle * 1-wire on-chip debug function Multiple Communication Interfaces * Up to 8 x I2C master * Up to 2 x I2C multi-master * Up to 8 x CSI/SPI (7-, 8-bit) * Up to 4 x UART (7-, 8-, 9-bit) * Up to 1 x LIN Code Flash Memory * Density: 16 KB to 256 KB * Block size: 1KB * On-chip single voltage flash memory with protection from block erase/writing * Self-programming with secure boot swap function and flash shield window function Data Flash Memory * Data flash with background operation * Data flash size: 4 KB to 8 KB size options * Erase cycles: 1 Million (typ.) * Erase/programming voltage: 1.8 V to 5.5 V RAM * 2.5 KB to 24 KB size options * Supports operands or instructions * Back-up retention in all modes High-speed On-chip Oscillator * 32 MHz with +/- 1% accuracy over voltage (1.8 V to 5.5 V) and temperature (-20C to 85C) * Pre-configured settings: 64 MHz,48 MHz,32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz * 64 MHz, 48 MHz for timer RD Reset and Supply Management * Power-on reset (POR) monitor/generator * Low voltage detection (LVD) with 14 setting options (Interrupt and/or reset function) General Purpose I/O * 5 V tolerant, high-current (up to 20 mA per pin) * Open-drain, on-chip pull-up resistor R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Event Link Controller (ELC) * Reduce interrupt intervention * Link 26 events to specified peripheral function Extended-Function Timers * Multi-function 16-bit timers: Up to 8 channels * Motor control timer (3 ph - complementary mode) * Timer with encoder function: 16-bit, 1 channel * Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function) * Interval timer: 12-bit, 1 channel * 15 kHz watchdog timer: 1 channel (window function) Rich Analog * ADC: Up to 20 channels, 10-bit resolution, 2.1 s conversion time * Supports 1.6 V * 2 x window comparators, with ELC connection * D/A converter: 2 channels, 8-bit resolution * Internal voltage reference (1.45 V) * On-chip temperature sensor Safety Features (IEC or UL 60730 compliance) * Flash memory CRC calculation * RAM parity error check * RAM write protection * SFR write protection * Illegal memory access detection * Clock stop/frequency detection * ADC self-test * I/O port read back function (echo) Operating Ambient Temperature * Standard: -40C to + 85C * Extended: -40C to + 105C Package Type and Pin Count From 4 mm x 4 mm to 14 mm x 20 mm QFP: 32, 44, 48, 52, 64, 80,100 QFN: 32, 40, 48 SSOP: 30 LGA: 36, 64 Page 1 of 187 RL78/G14 1. OUTLINE ROM, RAM capacities RL78/G14 Flash ROM 192 KB Data flash RAM 30 pins 32 pins 36 pins 40 pins 8 KB 20 KB -- -- -- R5F104EH 128 KB 8 KB 16 KB R5F104AG R5F104BG R5F104CG R5F104EG 96 KB 8 KB 12 KB R5F104AF R5F104BF R5F104CF R5F104EF 64 KB 4 KB 5.5 KB Note 1 R5F104AE R5F104BE R5F104CE R5F104EE 48 KB 4 KB 5.5 KB Note 1 R5F104AD R5F104BD R5F104CD R5F104ED 32 KB 4 KB 4 KB R5F104AC R5F104BC R5F104CC R5F104EC 16 KB 4 KB 2.5 KB R5F104AA R5F104BA R5F104CA R5F104EA Flash ROM Data flash RAM 44 pins 48 pins 52 pins 64 pins RL78/G14 256 KB 8 KB 24 KB Note 2 R5F104FJ R5F104GJ R5F104JJ R5F104LJ 192 KB 8 KB 20 KB R5F104FH R5F104GH R5F104JH R5F104LH 128 KB 8 KB 16 KB R5F104FG R5F104GG R5F104JG R5F104LG 96 KB 8 KB 12 KB R5F104FF R5F104GF R5F104JF R5F104LF R5F104FE R5F104GE R5F104JE R5F104LE 64 KB 4 KB 5.5 KB Note 1 5.5 KB Note 1 48 KB 4 KB R5F104FD R5F104GD R5F104JD R5F104LD 32 KB 4 KB 4 KB R5F104FC R5F104GC R5F104JC R5F104LC 16 KB 4 KB 2.5 KB R5F104FA R5F104GA -- -- Flash ROM Data flash RAM RL78/G14 80 pins Note 2 100 pins 256 KB 8 KB R5F104MJ R5F104PJ 192 KB 8 KB 20 KB R5F104MH R5F104PH 128 KB 8 KB 16 KB R5F104MG R5F104PG 96 KB 8 KB 12 KB R5F104MF R5F104PF 24 KB Note 1. This is about 4.5 KB when the self-programming function and data flash function are used. Note 2. This is about 23 KB when the self-programming function and data flash function are used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 2 of 187 RL78/G14 1.2 1. OUTLINE Ordering Information Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14 Part No. R 5 F 1 0 4 L E A x x x F B # V 0 Packaging specification #U0: Tray (HWQFN, WFLGA, FLGA) #V0: Tray (LFQFP, LQFP, LSSOP) #W0: Embossed Tape (HWQFN, WFLGA, FLGA) #X0: Embossed Tape (LFQFP, LQFP, LSSOP) Package type: SP: LSSOP, 0.65 mm pitch FP: LQFP, 0.80 mm pitch FA: LQFP, 0.65 mm pitch FB: LFQFP, 0.50 mm pitch NA:HWQFN, 0.50 mm pitch LA: WFLGA, 0.50 mm pitch Note LA: FLGA, 0.50 mm pitch Note ROM number (Omitted with blank products) Fields of application: A: Consumer applications, TA = -40 to +85 C D: Industrial applications, TA = -40 to +85 C G: Industrial applications, TA = -40 to +105 C ROM capacity: A: 16 KB C: 32 KB D: 48 KB E: 64 KB F: 96 KB G: 128 KB H: 192 KB J: 256 KB Pin count: A: 30-pin B: 32-pin C: 36-pin Note E: 40-pin F: 44-pin G: 48-pin J: 52-pin L: 64-pin M: 80-pin P: 100-pin RL78/G14 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Note Products only for "A: Consumer applications (TA = -40 to +85 C)" R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 3 of 187 RL78/G14 1. OUTLINE (1/5) Pin count 30 pins Package Fields of Application Ordering Part Number Note 30-pin plastic LSSOP A (7.62 mm (300), 0.65 mm pitch) R5F104AAASP#V0, R5F104ACASP#V0, R5F104ADASP#V0, R5F104AEASP#V0, R5F104AFASP#V0, R5F104AGASP#V0 R5F104AAASP#X0, R5F104ACASP#X0, R5F104ADASP#X0, R5F104AEASP#X0, R5F104AFASP#X0, R5F104AGASP#X0 D R5F104AADSP#V0, R5F104ACDSP#V0, R5F104ADDSP#V0, R5F104AEDSP#V0, R5F104AFDSP#V0, R5F104AGDSP#V0 R5F104AADSP#X0, R5F104ACDSP#X0, R5F104ADDSP#X0, R5F104AEDSP#X0, R5F104AFDSP#X0, R5F104AGDSP#X0 G R5F104AAGSP#V0, R5F104ACGSP#V0, R5F104ADGSP#V0, R5F104AEGSP#V0, R5F104AFGSP#V0, R5F104AGGSP#V0 R5F104AAGSP#X0, R5F104ACGSP#X0, R5F104ADGSP#X0, R5F104AEGSP#X0, R5F104AFGSP#X0, R5F104AGGSP#X0 32 pins 32-pin plastic HWQFN A (5 5 mm, 0.5 mm pitch) R5F104BAANA#U0, R5F104BCANA#U0, R5F104BDANA#U0, R5F104BEANA#U0, R5F104BFANA#U0, R5F104BGANA#U0 R5F104BAANA#W0, R5F104BCANA#W0, R5F104BDANA#W0, R5F104BEANA#W0, R5F104BFANA#W0, R5F104BGANA#W0 D R5F104BADNA#U0, R5F104BCDNA#U0, R5F104BDDNA#U0, R5F104BEDNA#U0, R5F104BFDNA#U0, R5F104BGDNA#U0 R5F104BADNA#W0, R5F104BCDNA#W0, R5F104BDDNA#W0, R5F104BEDNA#W0, R5F104BFDNA#W0, R5F104BGDNA#W0 G R5F104BAGNA#U0, R5F104BCGNA#U0, R5F104BDGNA#U0, R5F104BEGNA#U0, R5F104BFGNA#U0, R5F104BGGNA#U0 R5F104BAGNA#W0, R5F104BCGNA#W0, R5F104BDGNA#W0, R5F104BEGNA#W0, R5F104BFGNA#W0, R5F104BGGNA#W0 32-pin plastic LQFP A (7 7, 0.8 mm pitch) R5F104BAAFP#V0, R5F104BCAFP#V0, R5F104BDAFP#V0, R5F104BEAFP#V0, R5F104BFAFP#V0, R5F104BGAFP#V0 R5F104BAAFP#X0, R5F104BCAFP#X0, R5F104BDAFP#X0, R5F104BEAFP#X0, R5F104BFAFP#X0, R5F104BGAFP#X0 D R5F104BADFP#V0, R5F104BCDFP#V0, R5F104BDDFP#V0, R5F104BEDFP#V0, R5F104BFDFP#V0, R5F104BGDFP#V0 R5F104BADFP#X0, R5F104BCDFP#X0, R5F104BDDFP#X0, R5F104BEDFP#X0, R5F104BFDFP#X0, R5F104BGDFP#X0 G R5F104BAGFP#V0, R5F104BCGFP#V0, R5F104BDGFP#V0, R5F104BEGFP#V0, R5F104BFGFP#V0, R5F104BGGFP#V0 R5F104BAGFP#X0, R5F104BCGFP#X0, R5F104BDGFP#X0, R5F104BEGFP#X0, R5F104BFGFP#X0, R5F104BGGFP#X0 36 pins 36-pin plastic WFLGA (4 4 mm, 0.5 mm pitch) A R5F104CAALA#U0, R5F104CCALA#U0, R5F104CDALA#U0, R5F104CEALA#U0, R5F104CFALA#U0, R5F104CGALA#U0 R5F104CAALA#W0, R5F104CCALA#W0, R5F104CDALA#W0, R5F104CEALA#W0, R5F104CFALA#W0, R5F104CGALA#W0 Note Caution For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 4 of 187 RL78/G14 1. OUTLINE (2/5) Pin count 40 pins Package Fields of Application Ordering Part Number Note 40-pin plastic HWQFN A (6 6 mm, 0.5 mm pitch) R5F104EAANA#U0, R5F104ECANA#U0, R5F104EDANA#U0, R5F104EEANA#U0, R5F104EFANA#U0, R5F104EGANA#U0, R5F104EHANA#U0 R5F104EAANA#W0, R5F104ECANA#W0, R5F104EDANA#W0, R5F104EEANA#W0, R5F104EFANA#W0, R5F104EGANA#W0, R5F104EHANA#W0 D R5F104EADNA#U0, R5F104ECDNA#U0, R5F104EDDNA#U0, R5F104EEDNA#U0, R5F104EFDNA#U0, R5F104EGDNA#U0, R5F104EHDNA#U0 R5F104EADNA#W0, R5F104ECDNA#W0, R5F104EDDNA#W0, R5F104EEDNA#W0, R5F104EFDNA#W0, R5F104EGDNA#W0, R5F104EHDNA#W0 G R5F104EAGNA#U0, R5F104ECGNA#U0, R5F104EDGNA#U0, R5F104EEGNA#U0, R5F104EFGNA#U0, R5F104EGGNA#U0, R5F104EHGNA#U0 R5F104EAGNA#W0, R5F104ECGNA#W0, R5F104EDGNA#W0, R5F104EEGNA#W0, R5F104EFGNA#W0, R5F104EGGNA#W0, R5F104EHGNA#W0 44 pins 44-pin plastic LQFP A (10 10, 0.8 mm pitch) R5F104FAAFP#V0, R5F104FCAFP#V0, R5F104FDAFP#V0, R5F104FEAFP#V0, R5F104FFAFP#V0, R5F104FGAFP#V0, R5F104FHAFP#V0, R5F104FJAFP#V0 R5F104FAAFP#X0, R5F104FCAFP#X0, R5F104FDAFP#X0, R5F104FEAFP#X0, R5F104FFAFP#X0, R5F104FGAFP#X0, R5F104FHAFP#X0, R5F104FJAFP#X0 D R5F104FADFP#V0, R5F104FCDFP#V0, R5F104FDDFP#V0, R5F104FEDFP#V0, R5F104FFDFP#V0, R5F104FGDFP#V0, R5F104FHDFP#V0, R5F104FJDFP#V0 R5F104FADFP#X0, R5F104FCDFP#X0, R5F104FDDFP#X0, R5F104FEDFP#X0, R5F104FFDFP#X0, R5F104FGDFP#X0, R5F104FHDFP#X0, R5F104FJDFP#X0 G R5F104FAGFP#V0, R5F104FCGFP#V0, R5F104FDGFP#V0, R5F104FEGFP#V0, R5F104FFGFP#V0, R5F104FGGFP#V0, R5F104FHGFP#V0, R5F104FJGFP#V0 R5F104FAGFP#X0, R5F104FCGFP#X0, R5F104FDGFP#X0, R5F104FEGFP#X0, R5F104FFGFP#X0, R5F104FGGFP#X0, R5F104FHGFP#X0, R5F104FJGFP#X0 Note Caution For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 5 of 187 RL78/G14 1. OUTLINE (3/5) Pin count 48 pins Package Fields of Application Ordering Part Number Note 48-pin plastic LFQFP A (7 7 mm, 0.5 mm pitch) R5F104GAAFB#V0, R5F104GCAFB#V0, R5F104GDAFB#V0, R5F104GEAFB#V0, R5F104GFAFB#V0, R5F104GGAFB#V0, R5F104GHAFB#V0, R5F104GJAFB#V0 R5F104GAAFB#X0, R5F104GCAFB#X0, R5F104GDAFB#X0, R5F104GEAFB#X0, R5F104GFAFB#X0, R5F104GGAFB#X0, R5F104GHAFB#X0, R5F104GJAFB#X0 D R5F104GADFB#V0, R5F104GCDFB#V0, R5F104GDDFB#V0, R5F104GEDFB#V0, R5F104GFDFB#V0, R5F104GGDFB#V0, R5F104GHDFB#V0, R5F104GJDFB#V0 R5F104GADFB#X0, R5F104GCDFB#X0, R5F104GDDFB#X0, R5F104GEDFB#X0, R5F104GFDFB#X0, R5F104GGDFB#X0, R5F104GHDFB#X0, R5F104GJDFB#X0 G R5F104GAGFB#V0, R5F104GCGFB#V0, R5F104GDGFB#V0, R5F104GEGFB#V0, R5F104GFGFB#V0, R5F104GGGFB#V0, R5F104GHGFB#V0, R5F104GJGFB#V0 R5F104GAGFB#X0, R5F104GCGFB#X0, R5F104GDGFB#X0, R5F104GEGFB#X0, R5F104GFGFB#X0, R5F104GGGFB#X0, R5F104GHGFB#X0, R5F104GJGFB#X0 48-pin plastic HWQFN A (7 7 mm, 0.5 mm pitch) R5F104GAANA#U0, R5F104GCANA#U0, R5F104GDANA#U0, R5F104GEANA#U0, R5F104GFANA#U0, R5F104GGANA#U0, R5F104GHANA#U0, R5F104GJANA#U0 R5F104GAANA#W0, R5F104GCANA#W0, R5F104GDANA#W0, R5F104GEANA#W0, R5F104GFANA#W0, R5F104GGANA#W0, R5F104GHANA#W0, R5F104GJANA#W0 D R5F104GADNA#U0, R5F104GCDNA#U0, R5F104GDDNA#U0, R5F104GEDNA#U0, R5F104GFDNA#U0, R5F104GGDNA#U0, R5F104GHDNA#U0, R5F104GJDNA#U0 R5F104GADNA#W0, R5F104GCDNA#W0, R5F104GDDNA#W0, R5F104GEDNA#W0, R5F104GFDNA#W0, R5F104GGDNA#W0, R5F104GHDNA#W0, R5F104GJDNA#W0 G R5F104GAGNA#U0, R5F104GCGNA#U0, R5F104GDGNA#U0, R5F104GEGNA#U0, R5F104GFGNA#U0, R5F104GGGNA#U0, R5F104GHGNA#U0, R5F104GJGNA#U0 R5F104GAGNA#W0, R5F104GCGNA#W0, R5F104GDGNA#W0, R5F104GEGNA#W0, R5F104GFGNA#W0, R5F104GGGNA#W0, R5F104GHGNA#W0, R5F104GJGNA#W0 52 pins 52-pin plastic LQFP A (10 10 mm, 0.65 mm pitch) R5F104JCAFA#V0, R5F104JDAFA#V0, R5F104JEAFA#V0, R5F104JFAFA#V0, R5F104JGAFA#V0, R5F104JHAFA#V0, R5F104JJAFA#V0 R5F104JCAFA#X0, R5F104JDAFA#X0, R5F104JEAFA#X0, R5F104JFAFA#X0, R5F104JGAFA#X0, R5F104JHAFA#X0, R5F104JJAFA#X0 D R5F104JCDFA#V0, R5F104JDDFA#V0, R5F104JEDFA#V0, R5F104JFDFA#V0, R5F104JGDFA#V0, R5F104JHDFA#V0, R5F104JJDFA#V0 R5F104JCDFA#X0, R5F104JDDFA#X0, R5F104JEDFA#X0, R5F104JFDFA#X0, R5F104JGDFA#X0, R5F104JHDFA#X0, R5F104JJDFA#X0 G R5F104JCGFA#V0, R5F104JDGFA#V0, R5F104JEGFA#V0, R5F104JFGFA#V0, R5F104JGGFA#V0, R5F104JHGFA#V0, R5F104JJGFA#V0 R5F104JCGFA#X0, R5F104JDGFA#X0, R5F104JEGFA#X0, R5F104JFGFA#X0, R5F104JGGFA#X0, R5F104JHGFA#X0, R5F104JJGFA#X0 Note Caution For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 6 of 187 RL78/G14 1. OUTLINE (4/5) Pin count Package Fields of Application Ordering Part Number Note 64 pins 64-pin plastic LQFP A (12 12 mm, 0.65 mm pitch) R5F104LCAFA#V0, R5F104LDAFA#V0, R5F104LEAFA#V0, R5F104LFAFA#V0, R5F104LGAFA#V0, R5F104LHAFA#V0, R5F104LJAFA#V0 R5F104LCAFA#X0, R5F104LDAFA#X0, R5F104LEAFA#X0, R5F104LFAFA#X0, R5F104LGAFA#X0, R5F104LHAFA#X0, R5F104LJAFA#X0 D R5F104LCDFA#V0, R5F104LDDFA#V0, R5F104LEDFA#V0, R5F104LFDFA#V0, R5F104LGDFA#V0, R5F104LHDFA#V0, R5F104LJDFA#V0 R5F104LCDFA#X0, R5F104LDDFA#X0, R5F104LEDFA#X0, R5F104LFDFA#X0, R5F104LGDFA#X0, R5F104LHDFA#X0, R5F104LJDFA#X0 G R5F104LCGFA#V0, R5F104LDGFA#V0, R5F104LEGFA#V0, R5F104LFGFA#V0, R5F104LGGFA#V0, R5F104LHGFA#V0, R5F104LJGFA#V0 R5F104LCGFA#X0, R5F104LDGFA#X0, R5F104LEGFA#X0, R5F104LFGFA#X0, R5F104LGGFA#X0, R5F104LHGFA#X0, R5F104LJGFA#X0 64-pin plastic LFQFP A (10 10 mm, 0.5 mm pitch) R5F104LCAFB#V0, R5F104LDAFB#V0, R5F104LEAFB#V0, R5F104LFAFB#V0, R5F104LGAFB#V0, R5F104LHAFB#V0, R5F104LJAFB#V0 R5F104LCAFB#X0, R5F104LDAFB#X0, R5F104LEAFB#X0, R5F104LFAFB#X0, R5F104LGAFB#X0, R5F104LHAFB#X0, R5F104LJAFB#X0 D R5F104LCDFB#V0, R5F104LDDFB#V0, R5F104LEDFB#V0, R5F104LFDFB#V0, R5F104LGDFB#V0, R5F104LHDFB#V0, R5F104LJDFB#V0 R5F104LCDFB#X0, R5F104LDDFB#X0, R5F104LEDFB#X0, R5F104LFDFB#X0, R5F104LGDFB#X0, R5F104LHDFB#X0, R5F104LJDFB#X0 G R5F104LCGFB#V0, R5F104LDGFB#V0, R5F104LEGFB#V0, R5F104LFGFB#V0, R5F104LGGFB#V0, R5F104LHGFB#V0, R5F104LJGFB#V0 R5F104LCGFB#X0, R5F104LDGFB#X0, R5F104LEGFB#X0, R5F104LFGFB#X0, R5F104LGGFB#X0, R5F104LHGFB#X0, R5F104LJGFB#X0 64-pin plastic FLGA A (5 5 mm, 0.5 mm pitch) R5F104LCALA#U0, R5F104LDALA#U0, R5F104LEALA#U0, R5F104LFALA#U0, R5F104LGALA#U0, R5F104LHALA#U0, R5F104LJALA#U0 R5F104LCALA#W0, R5F104LDALA#W0, R5F104LEALA#W0, R5F104LFALA#W0, R5F104LGALA#W0, R5F104LHALA#W0, R5F104LJALA#W0 64-pin plastic LQFP A (14 14 mm, 0.8 mm pitch) R5F104LCAFP#V0, R5F104LDAFP#V0, R5F104LEAFP#V0, R5F104LFAFP#V0, R5F104LGAFP#V0, R5F104LHAFP#V0, R5F104LJAFP#V0 R5F104LCAFP#X0, R5F104LDAFP#X0, R5F104LEAFP#X0, R5F104LFAFP#X0, R5F104LGAFP#X0, R5F104LHAFP#X0, R5F104LJAFP#X0 D R5F104LCDFP#V0, R5F104LDDFP#V0, R5F104LEDFP#V0, R5F104LFDFP#V0, R5F104LGDFP#V0, R5F104LHDFP#V0, R5F104LJDFP#V0 R5F104LCDFP#X0, R5F104LDDFP#X0, R5F104LEDFP#X0, R5F104LFDFP#X0, R5F104LGDFP#X0, R5F104LHDFP#X0, R5F104LJDFP#X0 G R5F104LCGFP#V0, R5F104LDGFP#V0, R5F104LEGFP#V0, R5F104LFGFP#V0, R5F104LGGFP#V0, R5F104LHGFP#V0, R5F104LJGFP#V0 R5F104LCGFP#X0, R5F104LDGFP#X0, R5F104LEGFP#X0, R5F104LFGFP#X0, R5F104LGGFP#X0, R5F104LHGFP#X0, R5F104LJGFP#X0 Note Caution For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 7 of 187 RL78/G14 1. OUTLINE (5/5) Pin count Package Fields of Application Ordering Part Number NoteNote 80 pins 80-pin plastic LFQFP A (12 12 mm, 0.5 mm pitch) R5F104MFAFB#V0, R5F104MGAFB#V0, R5F104MHAFB#V0, R5F104MJAFB#V0 R5F104MFAFB#X0, R5F104MGAFB#X0, R5F104MHAFB#X0, R5F104MJAFB#X0 D R5F104MFDFB#V0, R5F104MGDFB#V0, R5F104MHDFB#V0, R5F104MJDFB#V0 R5F104MFDFB#X0, R5F104MGDFB#X0, R5F104MHDFB#X0, R5F104MJDFB#X0 G R5F104MFGFB#V0, R5F104MGGFB#V0, R5F104MHGFB#V0, R5F104MJGFB#V0 R5F104MFGFB#X0, R5F104MGGFB#X0, R5F104MHGFB#X0, R5F104MJGFB#X0 80-pin plastic LQFP A R5F104MFAFA#V0, R5F104MGAFA#V0, R5F104MHAFA#V0, R5F104MJAFA#V0 D R5F104MFDFA#V0, R5F104MGDFA#V0, R5F104MHDFA#V0, R5F104MJDFA#V0 (14 14 mm, 0.65 mm pitch) R5F104MFAFA#X0, R5F104MGAFA#X0, R5F104MHAFA#X0, R5F104MJAFA#X0 R5F104MFDFA#X0, R5F104MGDFA#X0, R5F104MHDFA#X0, R5F104MJDFA#X0 G R5F104MFGFA#V0, R5F104MGGFA#V0, R5F104MHGFA#V0, R5F104MJGFA#V0 R5F104MFGFA#X0, R5F104MGGFA#X0, R5F104MHGFA#X0, R5F104MJGFA#X0 100 pins 100-pin plastic LFQFP A (14 14 mm, 0.5 mm pitch) R5F104PFAFB#V0, R5F104PGAFB#V0, R5F104PHAFB#V0, R5F104PJAFB#V0 R5F104PFAFB#X0, R5F104PGAFB#X0, R5F104PHAFB#X0, R5F104PJAFB#X0 D R5F104PFDFB#V0, R5F104PGDFB#V0, R5F104PHDFB#V0, R5F104PJDFB#V0 R5F104PFDFB#X0, R5F104PGDFB#X0, R5F104PHDFB#X0, R5F104PJDFB#X0 G R5F104PFGFB#V0, R5F104PGGFB#V0, R5F104PHGFB#V0, R5F104PJGFB#V0 R5F104PFGFB#X0, R5F104PGGFB#X0, R5F104PHGFB#X0, R5F104PJGFB#X0 100-pin plastic LQFP A (14 20 mm, 0.65 mm pitch) R5F104PFAFA#V0, R5F104PGAFA#V0, R5F104PHAFA#V0, R5F104PJAFA#V0 R5F104PFAFA#X0, R5F104PGAFA#X0, R5F104PHAFA#X0, R5F104PJAFA#X0 D R5F104PFDFA#V0, R5F104PGDFA#V0, R5F104PHDFA#V0, R5F104PJDFA#V0 R5F104PFDFA#X0, R5F104PGDFA#X0, R5F104PHDFA#X0, R5F104PJDFA#X0 G R5F104PFGFA#V0, R5F104PGGFA#V0, R5F104PHGFA#V0, R5F104PJGFA#V0 R5F104PFGFA#X0, R5F104PGGFA#X0, R5F104PHGFA#X0, R5F104PJGFA#X0 Note Caution For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 8 of 187 RL78/G14 1.3 1. OUTLINE Pin Configuration (Top View) 1.3.1 30-pin products * 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3 P147/ANI18/VCOUT1 Note P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 9 of 187 RL78/G14 1.3.2 1. OUTLINE 32-pin products P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) * 32-pin plastic HWQFN (5 5 mm, 0.5 mm pitch) exposed die pad 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 P70 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P147/ANI18/VCOUT1 Note P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). Remark 3. It is recommended to connect an exposed die pad to VSS. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 10 of 187 RL78/G14 1. OUTLINE P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RxD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TxD0) * 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch) 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 P70 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P147/ANI18/VCOUT1 Note P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 11 of 187 RL78/G14 1.3.3 1. OUTLINE 36-pin products * 36-pin plastic WFLGA (4 x 4 mm, 0.5 mm pitch) Top View Bottom View 6 5 4 3 2 1 A B C D E F F E D C B A INDEX MARK A P60/SCLA0 B VDD C P121/X1 D P122/X2/EXCLK E P137/INTP0 F P40/TOOL0 6 5 6 P62/SSI00 P72/SO21 2 VSS REGC P120/ANI19/ RESET VCOUT0 Note P71/SI21/ P14/RxD2/SI20/ SDA21 SDA20/TRDIOD0/ INTP4/PCLBUZ0/ TRGCLKA/ (SCLA0) (TRJIO0) (TRJO0) RxD1/TRGCLKB/ TRJIO0 P50/INTP1/ SI00/RxD0/ TOOLRxD/ SDA00/TRGIOA/ (TRJO0) P70/SCK21/ SCL21 P15/PCLBUZ1/ SCK20/SCL20/ TRDIOB0/ (SDAA0) P22/ANI2/ P21/ANI1/ AVREFM P30/INTP3/ SCK00/SCL00/ TRJO0 P16/TI01/TO01/ INTP5/TRDIOC0/ P12/SO11/ TRDIOB1/ P24/ANI4 IVREF0 Note/ IVREF1 Note P11/SI11/ SDA11/ TRDIOC1 P10/SCK11/ SCL11/ TRDIOD1 P147/ANI18/ 4 3 P61/SDAA0 P31/TI03/TO03/ ANO0 Note P00/TI00/TxD1/ P20/ANI0/ AVREFP 5 P01/TO00/ 4 3 P23/ANI3/ ANO1 Note 2 (RXD0) 1 P51/INTP2/ SO00/TxD0/ TOOLTxD/ TRGIOB P17/TI02/TO02/ TRDIOA0/ TRDCLK/ P13/TxD2/ SO20/TRDIOA1/ IVCMP1 Note P25/ANI5 VCOUT1 Note 1 IVCMP0 Note/ (TXD0) A B C D Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). E F Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 12 of 187 RL78/G14 1.3.4 1. OUTLINE 40-pin products P147/ANI18/VCOUT1 Note P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB * 40-pin plastic HWQFN (6 6 mm, 0.5 mm pitch) 3029 28 27 26 25 24 23 22 21 20 31 exposed die pad 19 32 18 33 17 34 16 35 15 36 14 37 13 38 12 39 11 40 1 2 3 4 5 6 7 8 9 10 P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). Remark 3. It is recommended to connect an exposed die pad to VSS. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 13 of 187 RL78/G14 1.3.5 1. OUTLINE 44-pin products P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB * 44-pin plastic LQFP (10 x 10 mm, 0.8 mm pitch) 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 1011 P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 14 of 187 RL78/G14 1.3.6 1. OUTLINE 48-pin products P24/ANI4 P25/ANI5 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note P26/ANI6 P27/ANI7 P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P60/SCLA0 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 P61/SDAA0 P62/SSI00 P63 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130 P140/PCLBUZ0/INTP6 * 48-pin plastic LFQFP (7 7 mm, 0.5 mm pitch) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 15 of 187 RL78/G14 1. OUTLINE P24/ANI4 P25/ANI5 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note P26/ANI6 P27/ANI7 P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P60/SCLA0 36 35 34 33 32 31 30 29 28 27 26 25 24 37 exposed die pad 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 P61/SDAA0 P62/SSI00 P63 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130 P140/PCLBUZ0/INTP6 * 48-pin plastic HWQFN (7 7 mm, 0.5 mm pitch) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). Remark 3. It is recommended to connect an exposed die pad to VSS. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 16 of 187 RL78/G14 1.3.7 1. OUTLINE 52-pin products P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P12/SO11/TRDIOB1/IVREF1 Note P11/SI11/SDA11/TRDIOC1 P10/SCK11/SCL11/TRDIOD1 P146 P147/ANI18/VCOUT1 Note * 52-pin plastic LQFP (10 10 mm, 0.65 mm pitch) 39 38 37 36 35 34 33 32 31 30 29 28 27 24 P72/KR2/SO21 P24/ANI4 43 23 P73/KR3/SO01 P23/ANI3/ANO1 Note 44 22 P74/KR4/INTP8/SI01/SDA01 P22/ANI2/ANO0 Note 45 21 P75/KR5/INTP9/SCK01/SCL01 P21/ANI1/AVREFM 46 20 P76/KR6/INTP10/(RXD2) P20/ANI0/AVREFP 47 19 P77/KR7/INTP11/(TXD2) P130 48 18 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P03/ANI16/RxD1 49 17 P63 P02/ANI17/TxD1 50 16 P62/SSI00 P01/TO00/TRGCLKB/TRJIO0 51 15 P61/SDAA0 P00/TI00/TRGCLKA/(TRJO0) 52 14 P60/SCLA0 7 8 9 10 11 12 13 VDD 6 VSS 5 REGC 3 4 P121/X1 2 P40/TOOL0 1 P122/X2/EXCLK 42 P137/INTP0 P71/KR1/SI21/SDA21 P25/ANI5 P123/XT1 25 RESET P124/XT2/EXCLKS P70/KR0/SCK21/SCL21 41 P41/(TRJIO0) 26 P26/ANI6 P140/PCLBUZ0/INTP6 40 P120/ANI19/VCOUT0 Note P27/ANI7 Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 17 of 187 RL78/G14 1.3.8 1. OUTLINE 64-pin products * 64-pin plastic LQFP (14 14 mm, 0.8 mm pitch) * 64-pin plastic LQFP (12 12 mm, 0.65 mm pitch) P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/(INTP3) P53/(INTP2) P52/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) * 64-pin plastic LFQFP (10 10 mm, 0.5 mm pitch) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05/(INTP10) P06/(INTP11)/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 P120/ANI19/VCOUT0 Note P43/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 Note Mounted on the 96 KB or more code flash memory products. Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 18 of 187 RL78/G14 1. OUTLINE * 64-pin plastic FLGA (5 5 mm, 0.5 mm pitch) Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H H G F E D C B A INDEX MARK A 8 B EVSS0 EVDD0 C P121/X1 D P122/X2/ E P137/INTP0 F P123/XT1 P60/SCLA0 VSS VDD REGC RESET P61/SDAA0 P62/SSI00 P63 P40/TOOL0 P41/(TRJIO0) H P124/XT2/ P120/ANI19/ EXCLKS VCOUT0 Note P01/TO00/ P00/TI00/ P140/ TRGCLKB/ TRGCLKA/ PCLBUZ0/ TRJIO0 (TRJO0) INTP6 P02/ANI17/ P141/ SO10/TxD1 PCLBUZ1/ EXCLK 7 G P43/(INTP9) 6 8 7 6 INTP7 P77/KR7/ 5 P31/TI03/ P53/(INTP2) P42/(INTP8) INTP11/(TXD2) TO03/INTP4/ (PCLBUZ0)/ P03/ANI16/ P04/SCK10/ SI10/RxD1/ SCL10 P130 P20/ANI0/ AVREFP SDA10 5 (TRJIO0) 4 P75/KR5/ P76/KR6/ P16/TI01/ P21/ANI1/ P22/ANI2/ P23/ANI3/ INTP9/ INTP10/ TO01/INTP5/ AVREFM ANO0 Note ANO1 Note SCK01/ (RXD2) TRDIOC0/ P52/(INTP1) P54/(INTP3) SCL01 4 IVREF0 Note/ (SI00)/(RXD0) 3 P70/KR0/ P73/KR3/ P74/KR4/ P17/TI02/TO02/ P15/SCK20/ P12/SO11/ SCK21/ SO01 INTP8/SI01/ TRDIOA0/ SCL20/ TRDIOB1/ SDA01 TRDCLK/ TRDIOB0/ IVREF1 Note/ IVCMP0 Note/ (SDAA0) (INTP5) SCL21 P24/ANI4 P26/ANI6 3 (SO00)/(TXD0) 2 P30/INTP3/ P72/KR2/ P71/KR1/ P06/(INTP11)/ P14/RxD2/ P11/SI11/ RTC1HZ/ SO21 SI21/SDA21 (TRJIO0) SI20/SDA20/ SDA11/ TRDIOD0/ TRDIOC1 SCK00/ SCL00/TRJO0 P05/(INTP10) 1 P25/ANI5 P27/ANI7 2 (SCLA0) P50/INTP1/ P51/INTP2/ P55/ P13/TxD2/ P10/SCK11/ SI00/RxD0/ SO00/TxD0/ (PCLBUZ1)/ SO20/ SCL11/ TOOLRxD/ TOOLTxD/ (SCK00)/ TRDIOA1/ TRDIOD1 SDA00/ TRGIOB (INTP4) IVCMP1 Note P146 P147/ANI18/ VCOUT1 Note 1 TRGIOA/ (TRJO0) A Note B C D E F G H Mounted on the 96 KB or more code flash memory products. Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). Remark 4. It is recommended to connect an exposed die pad to VSS. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 19 of 187 RL78/G14 1.3.9 1. OUTLINE 80-pin products * 80-pin plastic LQFP (14 14 mm, 0.65 mm pitch) P153/ANI11 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146 P111 P110/(INTP11) P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/SCK31/SCL31/(INTP3) P53/SI31/SDA31/(INTP2) P52/SO31/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) * 80-pin plastic LFQFP (12 12 mm, 0.5 mm pitch) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05 P06/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00/SCLA1 P61/SDAA0 P60/SCLA0 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 20 of 187 RL78/G14 1.3.10 1. OUTLINE 100-pin products P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P87/(INTP9) P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO00/TxD0/TOOLTxD/TRGIOB P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) EVDD1 * 100-pin plastic LFQFP (14 14 mm, 0.5 mm pitch) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05 P06/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00/SCLA1 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P145 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 Caution 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 21 of 187 RL78/G14 1. OUTLINE P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145 P00/TI00/TRGCLKA/(TRJO0) P01/TO00/TRGCLKB/TRJIO0 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 P23/ANI3/ANO1 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 * 100-pin plastic LQFP (14 20 mm, 0.65 mm pitch) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0) P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO00/TxD0/TOOLTxD/TRGIOB P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P60/SCLA0 P61/SDAA0 P62/SSI00/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TxD2) P76/KR6/INTP10/(RxD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06/(TRJIO0) P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RxD1)/(SDA10) P82/(SO10)/(TxD1) P83 P84/(INTP6) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 EVDD1 P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 Caution 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0, 1 (PIOR0, 1). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 22 of 187 RL78/G14 1.4 1. OUTLINE Pin Identification ANI0 to ANI14,: Analog input ANI16 to ANI20 RxD0 to RxD3: Receive data SCK00, SCK01, SCK10,: Serial clock input/output ANO0, ANO1: Analog output SCK11, SCK20, SCK21, AVREFM: A/D converter reference SCK30, SCK31 potential ( side) input SCLA0, SCLA1,: Serial clock input/output A/D converter reference SCL00, SCL01, SCL10, SCL11,: Serial clock output AVREFP: potential (+ side) input SCL20, SCL21, SCL30, EVDD0, EVDD1: Power supply for port SCL31 EVSS0, EVSS1: Ground for port SDAA0, SDAA1, SDA00,: EXCLK: External clock input SDA01, SDA10, SDA11, (main system clock) SDA20, SDA21, SDA30, EXCLKS: External clock input SDA31 (subsystem clock) SI00, SI01, SI10, SI11,: External interrupt input SI20, SI21, SI30, SI31 IVCMP0, IVCMP1: Comparator input SO00, SO01, SO10,: IVREF0, IVREF1: Comparator reference input SO11, SO20, SO21, KR0 to KR7: Key return SO30, SO31 P00 to P06: Port 0 SSI00: Serial interface chip select input P10 to P17: Port 1 TI00 to TI03,: Timer input P20 to P27: Port 2 TI10 to TI13 P30, P31: Port 3 TO00 to TO03,: P40 to P47: Port 4 TO10 to TO13, TRJO0 P50 to P57: Port 5 TOOL0: Data input/output for tool P60 to P67: Port 6 TOOLRxD, TOOLTxD: Data input/output for external device P70 to P77: Port 7 TRDCLK, TRGCLKA,: Timer external input clock P80 to P87: Port 8 TRGCLKB P100 to P102: Port 10 TRDIOA0, TRDIOB0,: P110, P111: Port 11 TRDIOC0, TRDIOD0, P120 to P124: Port 12 TRDIOA1, TRDIOB1, P130, P137: Port 13 TRDIOC1, TRDIOD1, P140 to P147: Port 14 TRGIOA, TRGIOB, TRJIO0 P150 to P156: Port 15 TxD0 to TxD3: Transmit data PCLBUZ0, PCLBUZ1: Programmable clock VCOUT0, VCOUT1: Comparator output output/buzzer output VDD: Power supply REGC: Regulator capacitance VSS: Ground RESET: Reset X1, X2: Crystal oscillator (main system clock) RTC1HZ: Real-time clock correction XT1, XT2: Crystal oscillator (subsystem clock) INTP0 to INTP11: Serial data input/output Serial data input Serial data output Timer output Timer input/output clock (1 Hz) output R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 23 of 187 RL78/G14 1.5 1.5.1 1. OUTLINE Block Diagram 30-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P40 PORT 5 2 P50, P51 PORT 6 2 P60, P61 2 P120 P121, P122 TRJIO0/P01 TIMER RJ TRJO0/P30 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR PORT 12 PORT 13 PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 P137 12- BIT INTERVAL TIMER UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P31 CSI00 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL11/P10 SDA11/P11 IIC11 RL78 CPU CORE P147 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL TOOL0/P40 ON-CHIP DEBUG VDD VSS SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 UART2 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCL20/P15 SDA20/P14 IIC20 TOOLRxD/P50, TOOLTxD/P51 RESET X1/P121 X2/EXCLK/P122 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 VOLTAGE REGULATOR REGC BUZZER OUTPUT CLOCK OUTPUT CONTROL 2 PCLBUZ0/P31, PCLBUZ1/P15 RxD0/P50 (LINSEL) INTP0/P137 2 DATA TRANSFER CONTROL INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 EVENT LINK CONTROLLER BCD ADJUSTMENT D/A CONVERTER Note ANO0/P22 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 24 of 187 RL78/G14 1.5.2 1. OUTLINE 32-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG PORT 5 2 P50, P51 PORT 6 3 P60 to P62 TRJIO0/P01 WINDOW WATCHDOG TIMER PORT 7 PORT 12 P70 2 PORT 13 PORT 14 A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL11/P10 SDA11/P11 IIC11 P147 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR P120 P121, P122 P137 12- BIT INTERVAL TIMER REAL-TIME CLOCK RxD0/P50 TxD0/P51 P40 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 UART2 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCL20/P15 SDA20/P14 IIC20 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 VOLTAGE REGULATOR REGC BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL PCLBUZ0/P31, PCLBUZ1/P15 RxD0/P50 (LINSEL) INTP0/P137 2 DATA TRANSFER CONTROL INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 EVENT LINK CONTROLLER BCD ADJUSTMENT D/A CONVERTER Note ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 25 of 187 RL78/G14 1.5.3 1. OUTLINE 36-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 6 P20 to P25 PORT 3 2 P30, P31 PORT 4 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 3 P70 to P72 2 P120 P121, P122 TRJIO0/P01 WINDOW WATCHDOG TIMER PORT 12 PORT 13 P137 12- BIT INTERVAL TIMER PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 P40 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL11/P10 SDA11/P11 IIC11 P147 6 ANI0/P20 to ANI5/P25 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 UART2 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 CLOCK OUTPUT CONTROL SCL20/P15 SDA20/P14 IIC20 DATA TRANSFER CONTROL SCL21/P70 SDA21/P71 IIC21 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 VOLTAGE REGULATOR REGC BUZZER OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 RxD0/P50 (LINSEL) INTP0/P137 2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 EVENT LINK CONTROLLER BCD ADJUSTMENT D/A CONVERTER Note ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 26 of 187 RL78/G14 1.5.4 1. OUTLINE 40-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P00, P01 PORT 1 8 P10 to P17 PORT 2 7 P20 to P26 PORT 3 2 P30, P31 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 4 P70 to P73 4 P120 P121 to P124 TRJIO0/P01 WINDOW WATCHDOG TIMER PORT 12 PORT 13 P137 12- BIT INTERVAL TIMER PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 P40 TIMER RJ TRJO0/P30 RTC1HZ/P30 2 PORT 4 TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL11/P10 SDA11/P11 IIC11 P147 7 ANI0/P20 to ANI6/P26 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN 4 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR3/P73 POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 UART2 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 CLOCK OUTPUT CONTROL SCL20/P15 SDA20/P14 IIC20 DATA TRANSFER CONTROL SCL21/P70 SDA21/P71 IIC21 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 VOLTAGE REGULATOR REGC BUZZER OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 RxD0/P50 (LINSEL) INTP0/P137 2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 EVENT LINK CONTROLLER BCD ADJUSTMENT D/A CONVERTER Note ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 27 of 187 RL78/G14 1.5.5 1. OUTLINE 44-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 4 P70 to P73 4 P120 P121 to P124 TRJIO0/P01 WINDOW WATCHDOG TIMER RTC1HZ/P30 2 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 PORT 12 PORT 13 PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 P137 12- BIT INTERVAL TIMER UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL11/P10 SDA11/P11 IIC11 RL78 CPU CORE 2 P146, P147 8 ANI0/P20 to ANI7/P27 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN 4 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR3/P73 POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 UART2 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 CLOCK OUTPUT CONTROL SCL20/P15 SDA20/P14 IIC20 DATA TRANSFER CONTROL SCL21/P70 SDA21/P71 IIC21 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 VOLTAGE REGULATOR REGC BUZZER OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 RxD0/P50 (LINSEL) INTP0/P137 2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 EVENT LINK CONTROLLER BCD ADJUSTMENT D/A CONVERTER Note ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 28 of 187 RL78/G14 1.5.6 1. OUTLINE 48-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 6 P70 to P75 4 P120 P121 to P124 TRJIO0/P01 WINDOW WATCHDOG TIMER RTC1HZ/P30 2 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 PORT 12 PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 UART0 LINSEL RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK01/P75 SI01/P74 SO01/P73 CSI01 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 P137 3 P140, P146, P147 8 ANI0/P20 to ANI7/P27 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR KEY RETURN 6 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR5/P75 POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD SCL01/P75 SDA01/P74 IIC01 SCL11/P10 SDA11/P11 IIC11 VSS SCK21/P70 SI21/P71 SO21/P72 CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCLA0/P60 2 CLOCK OUTPUT CONTROL CSI20 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD0/P50 (LINSEL) INTP0/P137 BUZZER OUTPUT UART2 SCK20/P15 SI20/P14 SO20/P13 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 SDAA0/P61 SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 P130 PORT 13 12- BIT INTERVAL TIMER PCLBUZ0/P140, PCLBUZ1/P15 DATA TRANSFER CONTROL 2 INTERRUPT CONTROL 2 INTP5/P16 INTP6/P140 EVENT LINK CONTROLLER 2 BCD ADJUSTMENT INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 D/A CONVERTER Note INTP8/P74, INTP9/P75 ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 29 of 187 RL78/G14 1.5.7 1. OUTLINE 52-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P00 to P03 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 4 P120 P121 to P124 TRJIO0/P01 WINDOW WATCHDOG TIMER RTC1HZ/P30 4 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 PORT 12 PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 UART0 LINSEL RxD1/P03 TxD1/P02 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK01/P75 SI01/P74 SO01/P73 CSI01 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 P137 3 8 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR P140, P146, P147 KEY RETURN 8 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR7/P77 POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD SCL01/P75 SDA01/P74 IIC01 SCL11/P10 SDA11/P11 IIC11 VSS SCK21/P70 SI21/P71 SO21/P72 CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCLA0/P60 2 CLOCK OUTPUT CONTROL CSI20 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD0/P50 (LINSEL) INTP0/P137 BUZZER OUTPUT UART2 SCK20/P15 SI20/P14 SO20/P13 TOOLRxD/P50, TOOLTxD/P51 TOOL0/P40 SDAA0/P61 SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT1 (2ch) RxD2/P14 TxD2/P13 P130 PORT 13 12- BIT INTERVAL TIMER PCLBUZ0/P140, PCLBUZ1/P15 DATA TRANSFER CONTROL 2 INTERRUPT CONTROL 2 INTP5/P16 INTP6/P140 EVENT LINK CONTROLLER 4 BCD ADJUSTMENT INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 D/A CONVERTER Note INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23 COMPARATOR Note (2ch) Note COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 30 of 187 RL78/G14 1.5.8 1. OUTLINE 64-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 4 P40 to P43 PORT 5 6 P50 to P55 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 4 P120 P121 to P124 TRJIO0/P01 WINDOW WATCHDOG TIMER RTC1HZ/P30 7 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 PORT 12 PORT 14 REAL-TIME CLOCK A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 UART0 LINSEL RxD1/P03 TxD1/P02 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK01/P75 SI01/P74 SO01/P73 CSI01 SCK10/P04 SI10/P03 SO10/P02 CSI10 SCK11/P10 SI11/P11 SO11/P12 CSI11 IIC00 IIC01 SCL10/P04 SDA10/P03 IIC10 IIC11 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR P140, P141, P146, P147 8 RL78 CPU CORE KEY RETURN 8 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR7/P77 POR/LVD CONTROL RAM VDD, VSS, TOOLRxD/P50, EVDD0 EVSS0 TOOLTxD/P51 SDAA0/P61 SERIAL INTERFACE IICA0 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC SCLA0/P60 RxD0/P50 (LINSEL) INTP0/P137 2 CLOCK OUTPUT CONTROL TOOL0/P40 SYSTEM CONTROL BUZZER OUTPUT SERIAL ARRAY UNIT1 (2ch) Note 4 ON-CHIP DEBUG SCL01/P75 SDA01/P74 RxD2/P14 TxD2/P13 P137 RESET CONTROL SCL00/P30 SDA00/P50 SCL11/P10 SDA11/P11 P130 PORT 13 12- BIT INTERVAL TIMER 2 PCLBUZ0/P140, PCLBUZ1/P141 UART2 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 DATA TRANSFER CONTROL 2 INTP6/P140, INTP7/P141 4 INTP8/P74 to INTP11/P77 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 SCL20/P15 SDA20/P14 IIC20 COMPARATOR Note (2ch) SCL21/P70 SDA21/P71 IIC21 COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 EVENT LINK CONTROLLER D/A CONVERTER Note BCD ADJUSTMENT ANO0/P22 ANO1/P23 Mounted on the 96 KB or more code flash memory products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 31 of 187 RL78/G14 1.5.9 1. OUTLINE 80-pin products TIMER ARRAY UNIT0 (4ch) TI00/P00 TO00/P01 TIMER ARRAY UNIT1 (4ch) ch0 TI10/TO10/P64 ch1 TI11/TO11/P65 ch2 TI12/TO12/P66 ch3 TI13/TO13/P67 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG WINDOW WATCHDOG TIMER RTC1HZ/P30 12- BIT INTERVAL TIMER RxD0/P50 TxD0/P51 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 4 ANI8/P150 to ANI11/P153 5 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 AVREFP/P20 AVREFM/P21 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL RxD1/P03 TxD1/P02 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK01/P43 SI01/P44 SO01/P45 CSI01 SCK10/P04 SI10/P03 SO10/P02 CSI10 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL10/P04 SDA10/P03 IIC10 SCL11/P10 SDA11/P11 IIC11 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 6 P40 to P45 PORT 5 6 P50 to P55 PORT 6 8 P60 to P67 PORT 7 8 P70 to P77 TRJIO0/P01 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 PORT 10 PORT 11 PORT 12 P100 2 P110, P111 4 P121 to P124 P120 P130 PORT 13 P137 PORT 14 7 P140 to P144, P146, P147 PORT 15 4 P150 to P153 KEY RETURN 8 KR0/P70 to KR7/P77 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL RAM TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL VDD, VSS, TOOLRxD/P50, EVDD0 EVSS0 TOOLTxD/P51 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR XT1/P123 XT2/EXCLKS/P124 VOLTAGE REGULATOR SERIAL INTERFACE IICA0 SDAA0/P61 SERIAL INTERFACE IICA1 SDAA1/P63 REGC RxD0/P50 (LINSEL) INTP0/P137 SCLA0/P60 2 SERIAL ARRAY UNIT1 (4ch) RxD2/P14 TxD2/P13 SCLA1/P62 INTERRUPT CONTROL INTP5/P16 UART2 BUZZER OUTPUT RxD3/P143 TxD3/P144 UART3 SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 SCK30/P142 SI30/P143 SO30/P144 CSI30 SCK31/P54 SI31/P53 SO31/P52 CSI31 SCL20/P15 SDA20/P14 IIC20 2 CLOCK OUTPUT CONTROL DATA TRANSFER CONTROL EVENT LINK CONTROLLER PCLBUZ0/P140, PCLBUZ1/P141 D/A CONVERTER SCL21/P70 SDA21/P71 IIC21 IIC30 SCL31/P54 SDA31/P53 IIC31 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 2 INTP6/P140, INTP7/P141 4 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23 COMPARATOR (2ch) COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 BCD ADJUSTMENT SCL30/P142 SDA30/P143 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 Page 32 of 187 RL78/G14 1.5.10 1. OUTLINE 100-pin products TIMER ARRAY UNIT0 (4ch) TI00/P00 TO00/P01 TIMER ARRAY UNIT1 (4ch) ch0 TI10/TO10/P64 ch1 TI11/TO11/P65 ch2 TI12/TO12/P66 ch3 TI13/TO13/P67 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 (LINSEL) ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 TRGIOA/P50, TRGIOB/P51 2 TRGCLKA/P00, TRGCLKB/P01 TIMER RG WINDOW WATCHDOG TIMER RTC1HZ/P30 12- BIT INTERVAL TIMER RxD0/P50 TxD0/P51 UART0 LINSEL RxD1/P03 TxD1/P02 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCK01/P43 SI01/P44 SO01/P45 CSI01 SCK10/P04 SI10/P03 SO10/P02 CSI10 SCK11/P10 SI11/P11 SO11/P12 CSI11 SCL00/P30 SDA00/P50 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL10/P04 SDA10/P03 IIC10 SCL11/P10 SDA11/P11 IIC11 RxD3/P143 TxD3/P144 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 8 P40 to P47 PORT 5 8 P50 to P57 PORT 6 8 P60 to P67 PORT 7 8 P70 to P77 ANI0/P20 to ANI7/P27 7 ANI8/P150 to ANI14/P156 PORT 8 8 P80 to P87 5 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 PORT 10 3 P100 to P102 PORT 11 2 P110, P111 4 P120 P121 to P124 AVREFP/P20 AVREFM/P21 PORT 12 P130 PORT 13 P137 RL78 CPU CORE CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULITIPLYACCUMULATOR DATA FLASH MEMORY PORT 14 8 PORT 15 7 P150 to P156 8 KR0/P70 to KR7/P77 KEY RETURN POWER ON RESET/ VOLTAGE DETECTOR P140 to P147 POR/LVD CONTROL RAM RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SERIAL ARRAY UNIT1 (4ch) RxD2/P14 TxD2/P13 A/D CONVERTER 8 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) 7 TRJIO0/P01 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 VDD, VSS, TOOLRxD/P50, EVDD0, EVSS0, TOOLTxD/P51 EVDD1 EVSS1 SERIAL INTERFACE IICA0 SDAA0/P61 SERIAL INTERFACE IICA1 SDAA1/P63 SCLA0/P60 BUZZER OUTPUT SCK20/P15 SI20/P14 SO20/P13 CSI20 SCK21/P70 SI21/P71 SO21/P72 CSI21 SCK30/P142 SI30/P143 SO30/P144 CSI30 2 CLOCK OUTPUT CONTROL PCLBUZ0/P140, PCLBUZ1/P141 2 INTERRUPT CONTROL IIC20 SCL21/P70 SDA21/P71 IIC21 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 2 INTP1/P47, INTP2/P46 INTP3/P30, INTP4/P31 INTP5/P16 D/A CONVERTER 2 INTP6/P140, INTP7/P141 4 INTP8/P74 to INTP11/P77 ANO0/P22 ANO1/P23 COMPARATOR (2ch) BCD ADJUSTMENT SCL20/P15 SDA20/P14 REGC RxD0/P50 (LINSEL) INTP0/P137 EVENT LINK CONTROLLER CSI31 XT1/P123 XT2/EXCLKS/P124 VOLTAGE REGULATOR DATA TRANSFER CONTROL SCK31/P54 SI31/P53 SO31/P52 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR SCLA1/P62 UART2 UART3 SYSTEM CONTROL COMPARATOR0 VCOUT0/P120 IVCMP0/P17 IVREF0/P16 COMPARATOR1 VCOUT1/P147 IVCMP1/P13 IVREF1/P12 Page 33 of 187 RL78/G14 1.6 1. OUTLINE Outline of Functions [30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)] Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = A, C to E) R5F104Bx (x = A, C to E) R5F104Cx (x = A, C to E) R5F104Ex (x = A, C to E) Code flash memory (KB) 16 to 64 16 to 64 16 to 64 16 to 64 Data flash memory (KB) 4 4 4 4 2.5 to 5.5 Note 2.5 to 5.5 Note 2.5 to 5.5 Note 2.5 to 5.5 Note Item RAM (KB) Address space 1 MB Main system High-speed system clock clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), oscillator clock (fIH) HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock -- XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem -- clock: fSUB = 32.768 kHz operation) Instruction set I/O port * * * * * Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) Multiplication and Accumulation (16 bits 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 26 28 32 36 CMOS I/O 21 22 26 28 CMOS input 3 3 3 5 CMOS output -- -- -- -- N-ch open-drain I/O (6 2 3 3 3 V tolerance) Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 13 channels PWM outputs: 9 channels RTC output -- 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 34 of 187 RL78/G14 1. OUTLINE (2/2) Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = A, C to E) R5F104Bx (x = A, C to E) R5F104Cx (x = A, C to E) R5F104Ex (x = A, C to E) 2 2 2 2 Clock output/buzzer output [30-pin, 32-pin, 36-pin products] * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) [40-pin products] * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter Serial interface 8 channels 8 channels 8 channels 9 channels [30-pin, 32-pin products] * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products] * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus Data transfer controller (DTC) Event link controller (ELC) Vectored interrupt sources 1 channel 1 channel 1 channel 1 channel 28 sources 29 sources Event input: 19 Event input: 20 Event trigger output: 7 Event trigger output: 7 Internal 24 24 24 24 External 6 6 6 7 -- -- -- 4 Key interrupt Reset * * * * Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 35 of 187 RL78/G14 1. OUTLINE [30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = F, G) R5F104Bx (x = F, G) R5F104Cx (x = F, G) R5F104Ex (x = F to H) Code flash memory (KB) 96 to 128 96 to 128 96 to 128 96 to 192 Data flash memory (KB) 8 8 8 8 12 to 16 12 to 16 12 to 16 12 to 20 Item RAM (KB) Address space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), oscillator clock (fIH) HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock -- XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem -- clock: fSUB = 32.768 kHz operation) Instruction set I/O port * * * * * Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) Multiplication and Accumulation (16 bits 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 26 28 32 36 CMOS I/O 21 22 26 28 CMOS input 3 3 3 5 CMOS output -- -- -- -- N-ch open-drain I/O (6 2 3 3 3 V tolerance) Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 13 channels PWM outputs: 9 channels RTC output -- 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 36 of 187 RL78/G14 1. OUTLINE (2/2) Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = F, G) R5F104Bx (x = F, G) R5F104Cx (x = F, G) R5F104Ex (x = F to H) 2 2 2 2 Clock output/buzzer output [30-pin, 32-pin, 36-pin products] * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) [40-pin products] * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 8 channels 8 channels D/A converter 1 channel 2 channels Comparator 2 channels Serial interface 8 channels 9 channels [30-pin, 32-pin products] * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products] * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 30 sources 31 sources Event link controller (ELC) Event input: 21 Event input: 22 Event trigger output: 8 Vectored interrupt Internal sources External 24 Key interrupt Reset Event input: 21, Event trigger output: 9 * * * * 24 24 Event trigger output: 9 24 6 6 6 7 -- -- -- 4 Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 37 of 187 RL78/G14 1. OUTLINE [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)] Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 44-pin 48-pin 52-pin 64-pin R5F104Fx R5F104Gx R5F104Jx R5F104Lx (x = A, C to E) (x = A, C to E) (x = C to E) (x = C to E) Code flash memory (KB) 16 to 64 16 to 64 32 to 64 32 to 64 Data flash memory (KB) 4 4 4 4 Item RAM (KB) 2.5 to 5.5 Address space Note 2.5 to 5.5 Note 4 to 5.5 Note 4 to 5.5 Note 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), oscillator clock (fIH) LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set * Data transfer (8/16 bits) * Adder and subtractor/logical operation (8/16 bits) * Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) * Multiplication and Accumulation (16 bits 16 bits + 32 bits) * Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Timer Note Total 40 44 48 58 CMOS I/O 31 34 38 48 CMOS input 5 5 5 5 CMOS output -- 1 1 1 N-ch open-drain I/O (6 V tolerance) 4 4 4 4 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 13 channels PWM outputs: 9 channels RTC output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 38 of 187 RL78/G14 1. OUTLINE (2/2) 44-pin Item 48-pin 52-pin 64-pin R5F104Fx R5F104Gx R5F104Jx R5F104Lx (x = A, C to E) (x = A, C to E) (x = C to E) (x = C to E) 2 2 2 2 Clock output/buzzer output * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 10 channels Serial interface [44-pin products] 10 channels 12 channels 12 channels * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products] * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels 1 channel 1 channel Data transfer controller (DTC) 29 sources 30 sources Event link controller (ELC) Event input: 20 Event trigger output: 7 I2C bus Vectored interrupt sources 1 channel 1 channel 31 sources Internal 24 24 24 24 External 7 10 12 13 4 6 8 8 Key interrupt Reset * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: * Power-down-reset: 1.51 0.03 V 1.50 0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 39 of 187 RL78/G14 1. OUTLINE [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 44-pin 48-pin 52-pin 64-pin R5F104Fx R5F104Gx R5F104Jx R5F104Lx (x = F to H, J) (x = F to H, J) (x = F to H, J) (x = F to H, J) Code flash memory (KB) 96 to 256 96 to 256 96 to 256 96 to 256 Data flash memory (KB) 8 8 8 8 Item RAM (KB) 12 to 24 Address space Note 12 to 24 Note 12 to 24 Note 12 to 24 Note 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), oscillator clock (fIH) LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set * Data transfer (8/16 bits) * Adder and subtractor/logical operation (8/16 bits) * Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) * Multiplication and Accumulation (16 bits 16 bits + 32 bits) * Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Timer Note Total 40 44 48 58 CMOS I/O 31 34 38 48 CMOS input 5 5 5 5 CMOS output -- 1 1 1 N-ch open-drain I/O (6 V tolerance) 4 4 4 4 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 14 channels PWM outputs: 9 channels RTC output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 40 of 187 RL78/G14 1. OUTLINE (2/2) Item 44-pin 48-pin 52-pin 64-pin R5F104Fx (x = F to H, J) R5F104Gx (x = F to H, J) R5F104Jx (x = F to H, J) R5F104Lx (x = F to H, J) 2 2 2 2 Clock output/buzzer output * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 10 channels D/A converter 2 channels Comparator 2 channels Serial interface [44-pin products] 10 channels 12 channels 12 channels * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products] * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels * CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels 1 channel 1 channel Data transfer controller (DTC) 31 sources 32 sources Event link controller (ELC) Event input: 22 Event trigger output: 9 I2C bus Vectored interrupt sources 1 channel 1 channel 33 sources Internal 24 24 24 24 External 7 10 12 13 4 6 8 8 Key interrupt Reset * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: * Power-down-reset: Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85 C Note 1.51 0.03 V 1.50 0.03 V The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 41 of 187 RL78/G14 1. OUTLINE [80-pin, 100-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 80-pin 100-pin R5F104Mx R5F104Px (x = F to H, J) (x = F to H, J) Code flash memory (KB) 96 to 256 96 to 256 Data flash memory (KB) 8 8 Item RAM (KB) 12 to 24 Address space Note 12 to 24 Note 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), oscillator clock (fIH) LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set * Data transfer (8/16 bits) * Adder and subtractor/logical operation (8/16 bits) * Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) * Multiplication and Accumulation (16 bits 16 bits + 32 bits) * Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Timer Note Total 74 92 CMOS I/O 64 82 CMOS input 5 5 CMOS output 1 1 N-ch open-drain I/O (6 V tolerance) 4 4 16-bit timer 12 channels (TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 18 channels PWM outputs: 12 channels RTC output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 42 of 187 RL78/G14 1. OUTLINE (2/2) Item 80-pin 100-pin R5F104Mx (x = F to H, J) R5F104Px (x = F to H, J) 2 2 Clock output/buzzer output * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 17 channels 20 channels D/A converter 2 channels 2 channels Comparator 2 channels 2 channels Serial interface [80-pin, 100-pin products] * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels * CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels 2 channels 2 channels Data transfer controller (DTC) 39 sources 39 sources Event link controller (ELC) Event input: 26 Event trigger output: 9 I2C bus Vectored interrupt sources Internal 32 32 External 13 13 8 8 Key interrupt Reset * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: * Power-down-reset: Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85 C Note 1.51 0.03 V 1.50 0.03 V The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 43 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85 C)" and "D: Industrial applications (TA = -40 to +85 C)". Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. Caution 3. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 44 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.1 Absolute Maximum Ratings Absolute Maximum Ratings Parameter Supply voltage REGC pin input voltage (1/2) Symbols Conditions Ratings Unit -0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V VIREGC REGC -0.3 to +2.8 V VDD and -0.3 to VDD +0.3 Note 1 Input voltage VI1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, -0.3 to EVDD0 +0.3 V and -0.3 to VDD +0.3 Note 2 P110, P111, P120, P140 to P147 VI2 P60 to P63 (N-ch open-drain) VI3 P20 to P27, P121 to P124, P137, -0.3 to +6.5 -0.3 to VDD +0.3 V Note 2 V P150 to P156, EXCLK, EXCLKS, RESET Output voltage VO1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, -0.3 to EVDD0 +0.3 and -0.3 to VDD +0.3 V Note 2 P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Analog input voltage VO2 P20 to P27, P150 to P156 VAI1 ANI16 to ANI20 -0.3 to VDD +0.3 Note 2 -0.3 to EVDD0 +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 VAI2 ANI0 to ANI14 -0.3 to VDD +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 V V V Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 45 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Absolute Maximum Ratings Parameter Output current, high (2/2) Symbols IOH1 Conditions Ratings Unit -40 mA -70 mA -100 mA -0.5 mA -2 mA 40 mA Total of all P00 to P04, P40 to P47, P102, P120, P130, pins P140 to P145 70 mA 170 mA 100 mA 1 mA 5 mA -40 to +85 C -65 to +150 C Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Total of all P00 to P04, P40 to P47, P102, P120, P130, pins P140 to P145 -170 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 IOH2 Per pin P20 to P27, P150 to P156 Total of all pins Output current, low IOL1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 IOL2 Per pin P20 to P27, P150 to P156 Total of all pins Operating ambient temperature TA Storage temperature Tstg Caution In normal operation mode In flash memory programming mode Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 46 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.2 Oscillator Characteristics 2.2.1 X1, XT1 characteristics (TA = -40 to +85 C, 1.6 V VDD 5.5 V, VSS = 0 V) Resonator X1 clock oscillation frequency Resonator (fX) Note XT1 clock oscillation frequency (fXT) Note Note Conditions MIN. MAX. Unit Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 MHz crystal resonator 2.4 V VDD <2.7 V 1.0 16.0 1.8 V VDD < 2.4 V 1.0 8.0 1.6 V VDD < 1.8 V 1.0 4.0 Crystal resonator TYP. 32 32.768 35 kHz Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G14 User's Manual Hardware. 2.2.2 On-chip oscillator characteristics (TA = -40 to +85 C, 1.6 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions MAX. Unit 1 32 MHz -20 to +85 C 1.8 V VDD 5.5 V -1.0 +1.0 % 1.6 V VDD < 1.8 V -5.0 +5.0 % 1.8 V VDD < 5.5 V -1.5 +1.5 % 1.6 V VDD < 1.8 V -5.5 fIH MIN. TYP. Notes 1, 2 High-speed on-chip oscillator clock frequency accuracy -40 to -20 C Low-speed on-chip oscillator clock frequency Low-speed on-chip oscillator clock frequency accuracy fIL +5.5 15 -15 % kHz +15 % Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 47 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.3 2.3.1 DC Characteristics Pin characteristics (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output current, high Symbol Note 1 IOH1 Conditions Per pin for P00 to P06, (1/5) MIN. TYP. 1.6 V EVDD0 5.5 V P10 to P17, P30, P31, P40 to P47, P50 to P57, MAX. Unit -10.0 mA Note 2 P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 4.0 V EVDD0 5.5 V -55.0 mA 2.7 V EVDD0 < 4.0 V -10.0 mA 1.8 V EVDD0 < 2.7 V -5.0 mA 1.6 V EVDD0 < 1.8 V -2.5 mA Total of P05, P06, P10 to P17, 4.0 V EVDD0 5.5 V -80.0 mA P30, P31, P50 to P57, P64 to P67, P70 to P77, 2.7 V EVDD0 < 4.0 V -19.0 mA 1.8 V EVDD0 < 2.7 V -10.0 mA 1.6 V EVDD0 < 1.8 V -5.0 mA 1.6 V EVDD0 5.5 V -135.0 Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty 70% Note 3) P80 to P87, P100, P101, P110, P111, P146, P147 (When duty 70% Note 3) Total of all pins (When duty 70% Note 3) IOH2 Note 4 Per pin for P20 to P27, P150 to P156 1.6 V VDD 5.5 V Total of all pins 1.6 V VDD 5.5 V -0.1 mA mA Note 2 -1.5 mA (When duty 70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Note 4. Caution -100 mA for industrial applications (R5F104xxDxx). P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 48 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output current, low Note 1 Symbol IOL1 Conditions (2/5) MIN. TYP. MAX. Unit Per pin for P00 to P06, 20.0 mA P10 to P17, P30, P31, P40 to P47, P50 to P57, Note 2 P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Per pin for P60 to P63 15.0 mA Note 2 Total of P00 to P04, P40 to P47, 4.0 V EVDD0 5.5 V 70.0 mA P102, P120, P130, P140 to P145 2.7 V EVDD0 < 4.0 V 15.0 mA 1.8 V EVDD0 < 2.7 V 9.0 mA 1.6 V EVDD0 < 1.8 V 4.5 mA (When duty 70% Note 3) Total of P05, P06, P10 to P17, 4.0 V EVDD0 5.5 V 80.0 mA P30, P31, P50 to P57, 2.7 V EVDD0 < 4.0 V 35.0 mA P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 1.8 V EVDD0 < 2.7 V 20.0 mA 1.6 V EVDD0 < 1.8 V 10.0 mA 150.0 mA 0.4 mA (When duty 70% Note 3) Total of all pins (When duty 70% Note 3) IOL2 Per pin for P20 to P27, P150 to P156 Total of all pins Note 2 1.6 V VDD 5.5 V 5.0 mA (When duty 70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1, and VSS pins. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 49 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input voltage, high Symbol VIH1 Conditions MAX. Unit 0.8 EVDD0 EVDD0 V P01, P03, P04, P10, P14 to P17, TTL input buffer 2.2 EVDD0 V P30, P43, P44, P50, P53 to P55, 4.0 V EVDD0 5.5 V P80, P81, P142, P143 TTL input buffer 2.0 EVDD0 V 1.5 EVDD0 V 0.7 VDD VDD V P00 to P06, P10 to P17, P30, MIN. (3/5) Normal input buffer TYP. P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VIH2 3.3 V EVDD0 < 4.0 V TTL input buffer 1.6 V EVDD0 < 3.3 V Input voltage, low VIH3 P20 to P27, P150 to P156 VIH4 P60 to P63 0.7 EVDD0 6.0 V 0.8 VDD VDD V 0 0.2 EVDD0 V P01, P03, P04, P10, P14 to P17, TTL input buffer P30, P43, P44, P50, P53 to P55, 4.0 V EVDD0 5.5 V 0 0.8 V P80, P81, P142, P143 TTL input buffer 3.3 V EVDD0 < 4.0 V 0 0.5 V TTL input buffer 1.6 V EVDD0 < 3.3 V 0 0.32 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET VIL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, Normal input buffer P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VIL2 Caution VIL3 P20 to P27, P150 to P156 0 0.3 VDD V VIL4 P60 to P63 0 0.3 EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 50 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output voltage, high Symbol VOH1 Conditions P00 to P06, P10 to P17, P30, 4.0 V EVDD0 5.5 V, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, IOH1 = -10.0 mA 4.0 V EVDD0 5.5 V, P80 to P87, P100 to P102, P110, IOH1 = -3.0 mA P111, P120, P130, P140 to P147 1.8 V EVDD0 5.5 V, MIN. (4/5) TYP. MAX. Unit EVDD0 - 1.5 V EVDD0 - 0.7 V EVDD0 - 0.5 V EVDD0 - 0.5 V VDD - 0.5 V IOH1 = -1.5 mA 1.6 V EVDD0 < 1.8 V, IOH1 = -1.0 mA VOH2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V, IOH2 = -100 A Output voltage, low VOL1 P00 to P06, P10 to P17, P30, 4.0 V EVDD0 5.5 V, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, IOL1 = 20.0 mA 1.3 V 4.0 V EVDD0 5.5 V, P80 to P87, P100 to P102, P110, IOL1 = 8.5 mA P111, P120, P130, 2.7 V EVDD0 5.5 V, P140 to P147 IOL1 = 3.0 mA 0.7 V 0.6 V 2.7 V EVDD0 5.5 V, 0.4 V 0.4 V 0.4 V IOL1 = 1.5 mA 1.8 V EVDD0 5.5 V, IOL1 = 0.6 mA 1.6 V EVDD0 5.5 V, IOL1 = 0.3 mA VOL2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V, IOL2 = 400 A 0.4 V VOL3 P60 to P63 4.0 V EVDD0 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V EVDD0 5.5 V, 0.4 V 0.4 V 0.4 V 0.4 V IOL3 = 5.0 mA 2.7 V EVDD0 5.5 V, IOL3 = 3.0 mA 1.8 V EVDD0 5.5 V, IOL3 = 2.0 mA 1.6 V EVDD0 5.5 V, IOL3 = 1.0 mA Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 51 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input leakage Symbol ILIH1 current, high Conditions P00 to P06, P10 to P17, P30, (5/5) MIN. TYP. MAX. Unit VI = EVDD0 1 A VI = VDD 1 A 1 A 10 A VI = EVSS0 -1 A -1 A -1 A -10 A 100 k P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 ILIH2 P20 to P27, P137, P150 to P156, RESET ILIH3 P121 to P124 VI = VDD (X1, X2, EXCLK, XT1, XT2, EXCLKS) In input port or external clock input In resonator connection Input leakage current, low ILIL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, VI = VSS EXCLKS) In input port or external clock input In resonator connection On-chip pull-up RU resistance P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, VI = EVSS0, In input port 10 20 P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 52 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) Parameter Supply current Symbol IDD1 (1/2) Conditions Operating HS (high-speed main) mode mode Note 5 MIN. fHOCO = 64 MHz, fIH = 32 MHz Note 3 Basic operation TYP. VDD = 5.0 V 2.4 VDD = 3.0 V 2.4 MAX. Unit mA Note 1 fHOCO = 32 MHz, fIH = 32 MHz Note 3 HS (high-speed main) fHOCO = 64 MHz, mode Note 5 fIH = 32 MHz Note 3 fHOCO = 32 MHz, fIH = 32 MHz Note 3 fHOCO = 48 MHz, fIH = 24 MHz Note 3 fHOCO = 24 MHz, fIH = 24 MHz Note 3 fHOCO = 16 MHz, fIH = 16 MHz Note 3 LS (low-speed main) fHOCO = 8 MHz, mode Note 5 fIH = 8 MHz Note 3 Basic operation VDD = 5.0 V 2.1 VDD = 3.0 V 2.1 Normal operation VDD = 5.0 V 5.2 8.7 VDD = 3.0 V 5.2 8.7 Normal operation VDD = 5.0 V 4.8 8.1 VDD = 3.0 V 4.8 8.1 Normal operation VDD = 5.0 V 4.1 6.9 VDD = 3.0 V 4.1 6.9 Normal operation VDD = 5.0 V 3.8 6.3 VDD = 3.0 V 3.8 6.3 Normal operation VDD = 5.0 V 2.8 4.6 VDD = 3.0 V 2.8 4.6 Normal operation VDD = 3.0 V 1.3 2.0 VDD = 2.0 V 1.3 2.0 VDD = 3.0 V 1.3 1.8 VDD = 2.0 V 1.3 1.8 LV (low-voltage main) fHOCO = 4 MHz, mode Note 5 fIH = 4 MHz Note 3 Normal operation HS (high-speed main) fMX = 20 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 3.3 5.3 Resonator connection 3.5 5.5 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.3 5.3 Resonator connection 3.5 5.5 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.0 3.1 Resonator connection 2.1 3.2 fMX = 10 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 2.0 3.1 Resonator connection 2.1 3.2 fMX = 8 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.2 1.9 Resonator connection 1.2 2.0 fMX = 8 MHz Note 2, VDD = 2.0 V Normal operation Square wave input 1.2 1.9 Resonator connection 1.2 2.0 fSUB = 32.768 kHz Note 4 Normal operation TA = -40 C Square wave input 4.7 6.1 Resonator connection 4.7 6.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +25 C Square wave input 4.7 6.1 Resonator connection 4.7 6.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +50 C Square wave input 4.8 6.7 Resonator connection 4.8 6.7 Normal operation Square wave input 4.8 7.5 Resonator connection 4.8 7.5 fSUB = 32.768 kHz Note 4 Normal operation TA = +85 C Square wave input 5.4 8.9 Resonator connection 5.4 8.9 mode Note 5 LS (low-speed main) mode Note 5 Subsystem clock operation fSUB = 32.768 kHz TA = +70 C Note 4 mA mA mA mA mA A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 53 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD , EV DD0 or VSS , EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 54 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) Parameter Symbol Supply current IDD2 Note 1 (2/2) Conditions HALT mode Note 2 MIN. TYP. MAX. Unit mA HS (high-speed main) fHOCO = 64 MHz, VDD = 5.0 V 0.80 3.09 mode Note 7 VDD = 3.0 V 0.80 3.09 fHOCO = 32 MHz, VDD = 5.0 V 0.54 2.40 fIH = 32 MHz Note 4 VDD = 3.0 V 0.54 2.40 fHOCO = 48 MHz, VDD = 5.0 V 0.62 2.40 fIH = 24 MHz Note 4 VDD = 3.0 V 0.62 2.40 fHOCO = 24 MHz, VDD = 5.0 V 0.44 1.83 fIH = 24 MHz Note 4 VDD = 3.0 V 0.44 1.83 fHOCO = 16 MHz, VDD = 5.0 V 0.40 1.38 fIH = 16 MHz Note 4 VDD = 3.0 V 0.40 1.38 LS (low-speed main) fHOCO = 8 MHz, VDD = 3.0 V 260 710 mode Note 7 fIH = 8 MHz Note 4 VDD = 2.0 V 260 710 LV (low-voltage main) fHOCO = 4 MHz, VDD = 3.0 V 420 700 mode Note 7 VDD = 2.0 V 420 700 Square wave input 0.28 1.55 Resonator connection 0.49 1.74 1.55 fIH = 32 MHz Note 4 fIH = 4 MHz Note 4 HS (high-speed main) fMX = 20 MHz Note 3, mode Note 7 VDD = 5.0 V fMX = 20 MHz Note 3, VDD = 3.0 V fMX = 10 MHz Note 3, VDD = 5.0 V fMX = 10 MHz VDD = 3.0 V LS (low-speed main) mode Note 7 Subsystem clock operation Note 3, Square wave input 0.28 Resonator connection 0.49 1.74 Square wave input 0.19 0.86 Resonator connection 0.30 0.93 Square wave input 0.19 0.86 Resonator connection 0.30 0.93 fMX = 8 MHz Note 3, VDD = 3.0 V Square wave input 95 550 Resonator connection 145 590 fMX = 8 MHz Note 3, VDD = 2.0 V Square wave input 95 550 Resonator connection 145 590 fSUB = 32.768 kHz Note 5, Square wave input TA = -40 C Resonator connection 0.25 0.57 0.44 0.76 fSUB = 32.768 kHz Note 5, Square wave input TA = +25 C Resonator connection 0.30 0.57 0.49 0.76 fSUB = 32.768 kHz Note 5, Square wave input TA = +50 C Resonator connection 0.36 1.17 0.59 1.36 Square wave input 0.49 1.97 Resonator connection 0.72 2.16 fSUB = 32.768 kHz Note 5, Square wave input TA = +85 C Resonator connection 0.97 3.37 1.16 3.56 fSUB = 32.768 kHz TA = +70 C Note 5, IDD3 STOP mode TA = -40 C 0.18 0.51 Note 6 Note 8 TA = +25 C 0.24 0.51 TA = +50 C 0.29 1.10 TA = +70 C 0.41 1.90 TA = +85 C 0.90 3.30 A A mA A A A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 55 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD , EV DD0 or VSS , EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 56 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD1 Conditions (1/2) MIN. Operating HS (high-speed main) fHOCO = 64 MHz, mode mode Note 5 fIH = 32 MHz Note 3 TYP. MAX. Basic operation VDD = 5.0 V 2.6 VDD = 3.0 V 2.6 Basic operation VDD = 5.0 V 2.3 VDD = 3.0 V 2.3 Normal operation VDD = 5.0 V 5.8 10.2 VDD = 3.0 V 5.8 10.2 Normal operation VDD = 5.0 V 5.4 9.6 VDD = 3.0 V 5.4 9.6 Normal operation VDD = 5.0 V 4.5 7.8 VDD = 3.0 V 4.5 7.8 Normal operation VDD = 5.0 V 4.2 7.4 VDD = 3.0 V 4.2 7.4 Normal operation VDD = 5.0 V 3.1 5.3 VDD = 3.0 V 3.1 5.3 Normal operation VDD = 3.0 V 1.4 2.3 VDD = 2.0 V 1.4 2.3 Normal operation VDD = 3.0 V 1.4 1.9 VDD = 2.0 V 1.4 1.9 HS (high-speed main) fMX = 20 MHz Note 2, VDD = 5.0 V mode Note 5 Normal operation Square wave input 3.7 6.2 Resonator connection 3.9 6.4 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.7 6.2 Resonator connection 3.9 6.4 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.2 3.6 Resonator connection 2.3 3.7 Note 2, Normal operation Square wave input 2.2 3.6 Resonator connection 2.3 3.7 fMX = 8 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 1.3 2.2 Resonator connection 1.3 2.3 fMX = 8 MHz Note 2, VDD = 2.0 V Normal operation Square wave input 1.3 2.2 Resonator connection 1.3 2.3 fSUB = 32.768 kHz Note 4 Normal operation TA = -40 C Square wave input 5.0 7.1 Resonator connection 5.0 7.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +25 C Square wave input 5.0 7.1 Resonator connection 5.0 7.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +50 C Square wave input 5.1 8.8 Resonator connection 5.1 8.8 Normal operation Square wave input 5.5 10.5 Resonator connection 5.5 10.5 fSUB = 32.768 kHz Note 4 Normal operation TA = +85 C Square wave input 6.5 14.5 Resonator connection 6.5 14.5 Unit mA Note 1 fHOCO = 32 MHz, fIH = 32 MHz Note 3 HS (high-speed main) fHOCO = 64 MHz, mode Note 5 fIH = 32 MHz Note 3 fHOCO = 32 MHz, fIH = 32 MHz Note 3 fHOCO = 48 MHz, fIH = 24 MHz Note 3 fHOCO = 24 MHz, fIH = 24 MHz Note 3 fHOCO = 16 MHz, fIH = 16 MHz Note 3 LS (low-speed main) fHOCO = 8 MHz, mode Note 5 fIH = 8 MHz Note 3 LV (low-voltage main) fHOCO = 4 MHz, mode Note 5 fIH = 4 MHz Note 3 fMX = 10 MHz VDD = 3.0 V LS (low-speed main) mode Note 5 Subsystem clock operation fSUB = 32.768 kHz TA = +70 C Note 4 mA mA mA mA mA A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 57 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EV SS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 58 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol IDD2 current Note 1 Note 2 Supply Conditions HALT mode (2/2) MIN. TYP. MAX. Unit mA HS (high-speed main) fHOCO = 64 MHz, VDD = 5.0 V 0.88 3.32 mode Note 7 fIH = 32 MHz Note 4 VDD = 3.0 V 0.88 3.32 fHOCO = 32 MHz, VDD = 5.0 V 0.62 2.63 fIH = 32 MHz Note 4 VDD = 3.0 V 0.62 2.63 fHOCO = 48 MHz, VDD = 5.0 V 0.68 2.57 fIH = 24 MHz Note 4 VDD = 3.0 V 0.68 2.57 fHOCO = 24 MHz, VDD = 5.0 V 0.50 2.00 fIH = 24 MHz Note 4 VDD = 3.0 V 0.50 2.00 fHOCO = 16 MHz, VDD = 5.0 V 0.44 1.49 fIH = 16 MHz Note 4 VDD = 3.0 V 0.44 1.49 LS (low-speed main) fHOCO = 8 MHz, VDD = 3.0 V 290 800 mode Note 7 fIH = 8 MHz Note 4 VDD = 2.0 V 290 800 LV (low-voltage main) fHOCO = 4 MHz, VDD = 3.0 V 440 755 mode Note 7 fIH = 4 MHz Note 4 VDD = 2.0 V 440 755 HS (high-speed main) fMX = 20 MHz Note 3, VDD = 5.0 V Square wave input 0.31 1.63 Resonator connection 0.50 1.85 fMX = 20 MHz Note 3, VDD = 3.0 V Square wave input 0.31 1.63 Resonator connection 0.50 1.85 fMX = 10 MHz Note 3, VDD = 5.0 V Square wave input 0.21 0.89 Resonator connection 0.30 0.97 Note 3, Square wave input 0.21 0.89 Resonator connection 0.30 0.97 fMX = 8 MHz Note 3, VDD = 3.0 V Square wave input 110 580 Resonator connection 160 630 fMX = 8 MHz Note 3, VDD = 2.0 V Square wave input 110 580 Resonator connection 160 630 fSUB = 32.768 kHz Note 5, TA = -40 C Square wave input 0.28 0.66 Resonator connection 0.47 0.85 fSUB = 32.768 kHz Note 5, TA = +25 C Square wave input 0.34 0.66 Resonator connection 0.53 0.85 fSUB = 32.768 kHz Note 5, TA = +50 C Square wave input 0.37 2.35 Resonator connection 0.56 2.54 Note 5, Square wave input 0.61 4.08 Resonator connection 0.80 4.27 Square wave input 1.55 8.09 Resonator connection 1.74 8.28 mode Note 7 fMX = 10 MHz VDD = 3.0 V LS (low-speed main) mode Note 7 Subsystem clock operation fSUB = 32.768 kHz TA = +70 C fSUB = 32.768 kHz Note 5, TA = +85 C IDD3 STOP mode TA = -40 C 0.19 0.57 Note 6 Note 8 TA = +25 C 0.25 0.57 TA = +50 C 0.33 2.26 TA = +70 C 0.52 3.99 TA = +85 C 1.46 8.00 A A mA A A A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 59 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EV SS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 60 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (3) Peripheral Functions (Common to all products) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note 1 0.20 A RTC operating current IRTC Notes 1, 2, 3 0.02 A 12-bit interval timer operating current IIT Notes 1, 2, 4 0.02 A Watchdog timer operating current IWDT Notes 1, 2, 5 fIL = 15 kHz 0.22 A A/D converter operating current IADC Notes 1, 6 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter reference voltage current IADREF Note 1 75.0 A Temperature sensor operating current ITMPS Note 1 75.0 A D/A converter operating current IDAC Notes 1, 11, 13 Comparator operating current ICMP Notes 1, 12, 13 VDD = 5.0 V, Regulator output voltage = 2.1 V Window mode 12.5 A Comparator high-speed mode 6.5 A Comparator low-speed mode 1.7 A VDD = 5.0 V, Regulator output voltage = 1.8 V Window mode 8.0 A Comparator high-speed mode 4.0 A Comparator low-speed mode 1.3 A Per D/A converter channel 1.5 mA A LVD operating current ILVD Notes 1, 7 0.08 Self-programming operating current IFSP Notes 1, 9 2.50 12.20 mA BGO operating current IBGO Notes 1, 8 2.50 12.20 mA SNOOZE operating current ISNOZ Note 1 The mode is performed Note 10 0.50 0.60 mA The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V 1.20 1.44 CSI/UART operation 0.70 0.84 DTC operation 3.10 ADC operation Note 1. Current flowing to VDD. Note 2. When high speed on-chip oscillator and high-speed system clock are stopped. Note 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 61 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and Note 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and Note 8. Current flowing during programming of the data flash. Note 9. Current flowing during self-programming. Note 10. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/G14 User's Manual Hardware. Note 11. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and Note 12. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IADC when the A/D converter operates in an operation mode or the HALT mode. ILVD when the LVD circuit is in operation. IDAC when the D/A converter operates in an operation mode or the HALT mode. IDD3 and ICMP when the comparator circuit is in operation. Note 13. A comparator and D/A converter are provided in products with 96 KB or more code flash memory. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 62 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.4 AC Characteristics (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions (1/2) MIN. Main system HS (high-speed main) 2.7 V VDD 5.5 V 0.03125 (minimum instruction clock (fMAIN) mode 2.4 V VDD < 2.7 V execution time) operation LS (low-speed main) 1.8 V VDD 5.5 V LV (low-voltage main) 1.6 V VDD 5.5 V Instruction cycle TCY TYP. MAX. Unit 1 s 0.0625 1 s 0.125 1 s 0.25 1 s 31.3 s mode mode Subsystem clock (fSUB) operation 1.8 V VDD 5.5 V HS (high-speed main) 2.7 V VDD 5.5 V 28.5 30.5 0.03125 1 s programming mode 2.4 V VDD < 2.7 V 0.0625 1 s mode 1.8 V VDD 5.5 V 0.125 1 s LV (low-voltage main) 1.8 V VDD 5.5 V 0.25 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 MHz 1.8 V VDD < 2.4 V 1.0 8.0 MHz 1.6 V VDD < 1.8 V 1.0 4.0 MHz 32 35 kHz tEXH, 2.7 V VDD 5.5 V 24 ns tEXL 2.4 V VDD 2.7 V 30 ns 1.8 V VDD < 2.4 V 60 ns 1.6 V VDD < 1.8 V 120 ns 13.7 s 1/fMCK + 10 ns In the self- LS (low-speed main) mode mode External system clock frequency fEX fEXS External system clock input high-level width, low-level width tEXHS, tEXLS TI00 to TI03, TI10 to tTIH, tTIL TI13 input high-level width, low-level width Timer RJ input cycle Timer RJ input highlevel width, low-level width Note Note fC tTJIH, TRJIO TRJIO tTJIL 2.7 V EVDD0 5.5 V 100 ns 1.8 V EVDD0 < 2.7 V 300 ns 1.6 V EVDD0 < 1.8 V 500 ns 2.7 V EVDD0 5.5 V 40 ns 1.8 V EVDD0 < 2.7 V 120 ns 1.6 V EVDD0 < 1.8 V 200 ns The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V EVDD0 < 2.7 V: MIN. 125 ns 1.6 V EVDD0 < 1.8 V: MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 63 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions Timer RD input high-level tTDIH, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, width, low-level width tTDIL TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 Timer RD forced cutoff signal tTDSIL P130/INTP0 input low-level width 2MHz < fCLK 32 MHz fCLK 2 MHz Timer RG input high-level tTGIH, width, low-level width tTGIL TO00 to TO03, fTO TRGIOA, TRGIOB (2/2) MIN. TYP. MAX. Unit 3/fCLK ns 1 s 1/fCLK + 1 2.5/fCLK ns 4.0 V EVDD0 5.5 V 16 MHz TO10 to TO13, 2.7 V EVDD0 < 4.0 V 8 MHz TRJIO0, TRJO0, 1.8 V EVDD0 < 2.7 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz LS (low-speed main) mode 1.8 V EVDD0 5.5 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz LV (low-voltage main) mode 1.6 V EVDD0 5.5 V 2 MHz HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz 2.7 V EVDD0 < 4.0 V 8 MHz 1.8 V EVDD0 < 2.7 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz HS (high-speed main) mode TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRGIOA, TRGIOB output frequency PCLBUZ0, PCLBUZ1 output frequency fPCL LS (low-speed main) mode LV (low-voltage main) mode 1.8 V EVDD0 5.5 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz 1.8 V EVDD0 5.5 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz Interrupt input high-level width, low-level width tINTH, INTP0 1.6 V VDD 5.5 V 1 s tINTL INTP1 to INTP11 1.6 V EVDD0 5.5 V 1 s Key interrupt input low-level width tKR KR0 to KR7 1.8 V EVDD0 5.5 V 250 ns 1.6 V EVDD0 < 1.8 V 1 s RESET low-level width tRSL 10 s R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 64 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 65 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 TCY vs VDD (LS (low-speed main) mode) 10 When the high-speed on-chip oscillator clock is selected Cycle time TCY [s] 1.0 During self-programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] TCY vs VDD (LV (low-voltage main) mode) 10 Cycle time TCY [s] 1.0 When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.25 0.1 0.01 0 1.0 2.0 3.0 4.0 1.6 1.8 6.0 5.0 5.5 Supply voltage VDD [V] R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 66 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS EXCLK/EXCLKS TI/TO Timing tTIL tTIH TI00 to TI03, TI10 to TI13 1/fTO TO00 to TO03, TO10 to TO13, TRJIO0, TRJO0, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRGIOA, TRGIOB R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 67 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 tTJIH tTJIL TRJIO tTDIH tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 tTDSIL INTP0 tTGIL tTGIH TRGIOA, TRGIOB R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 68 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 69 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) LV (low-voltage main) Mode Mode Mode MIN. Transfer rate Note 1 2.4 V EVDD0 5.5 V MAX. MIN. MAX. MIN. Unit MAX. fMCK/6 Note 2 fMCK/6 fMCK/6 bps 5.3 1.3 0.6 Mbps fMCK/6 Note 2 fMCK/6 fMCK/6 bps 5.3 1.3 0.6 Mbps fMCK/6 Note 2 fMCK/6 Note 2 fMCK/6 bps 5.3 1.3 0.6 Mbps -- fMCK/6 Note 2 fMCK/6 bps -- 1.3 0.6 Mbps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.8 V EVDD0 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.7 V EVDD0 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.6 V EVDD0 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Note 2. The following conditions are required for low voltage interface when EVDD0 VDD. 2.4 V EVDD0 2.7 V: MAX. 2.6 Mbps 1.8 V EVDD0 2.4 V: MAX. 1.3 Mbps 1.6 V EVDD0 1.8 V: MAX. 0.6 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 70 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 UART mode connection diagram (during communication at same potential) Rx TxDq RL78 microcontroller User's device Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 71 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. 4.0 V EVDD0 5.5 V MAX. LS (low-speed main) mode MIN. LV (low-voltage main) mode MAX. MIN. Unit MAX. SCKp cycle time tKCY1 tKCY1 2/fCLK 83.3 SCKp high-/low-level width tKH1, tKL1 4.0 V EVDD0 5.5 V tKCY1/2 - 7 2.7 V EVDD0 5.5 V tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 ns SIp setup time (to SCKp) tSIK1 4.0 V EVDD0 5.5 V 23 110 110 ns 2.7 V EVDD0 5.5 V 33 110 110 ns tKSI1 2.7 V EVDD0 5.5 V 10 10 10 ns tKSO1 C = 20 pF Note 4 2.7 V EVDD0 5.5 V Note 1 SIp hold time (from 62.5 250 500 ns 250 500 ns tKCY1/2 - 50 tKCY1/2 - 50 ns SCKp) Note 2 Delay time from SCKp to 10 10 10 ns SOp output Note 3 Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. This value is valid only when CSI00's peripheral I/O redirect function is not used. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 72 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time SCKp high-/low-level width SIp setup time tKCY1 tKH1, tKL1 tSIK1 (to SCKp) Note 1 SIp hold time tKSI1 (from SCKp) Note 2 Delay time from SCKp to SOp output Note 3 tKSO1 MAX. LS (low-speed main) mode MIN. MAX. LV (low-voltage main) mode MIN. Unit MAX. 2.7 V EVDD0 5.5 V 125 500 1000 ns 2.4 V EVDD0 5.5 V 250 500 1000 ns 1.8 V EVDD0 5.5 V 500 500 1000 ns 1.7 V EVDD0 5.5 V 1000 1000 1000 ns 1.6 V EVDD0 5.5 V -- 1000 1000 ns 4.0 V EVDD0 5.5 V tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V EVDD0 5.5 V tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.4 V EVDD0 5.5 V tKCY1/2 - 38 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.8 V EVDD0 5.5 V tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.7 V EVDD0 5.5 V tKCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 ns 1.6 V EVDD0 5.5 V -- tKCY1/2 - 100 tKCY1/2 - 100 ns 4.0 V EVDD0 5.5 V 44 110 110 ns 2.7 V EVDD0 5.5 V 44 110 110 ns 2.4 V EVDD0 5.5 V 75 110 110 ns 1.8 V EVDD0 5.5 V 110 110 110 ns 1.7 V EVDD0 5.5 V 220 220 220 ns 1.6 V EVDD0 5.5 V -- 220 220 ns 1.7 V EVDD0 5.5 V 19 19 19 ns 1.6 V EVDD0 5.5 V -- 19 19 ns tKCY1 4/fCLK 1.7 V EVDD0 5.5 V C = 30 pF Note 4 25 25 25 ns 1.6 V EVDD0 5.5 V C = 30 pF Note 4 -- 25 25 ns Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 73 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. tKCY2 SCKp cycle SIp setup time (to SCKp) tSIK2 Note 1 SIp hold time (from SCKp) tKSI2 Note 2 Delay time from SCKp to SOp output tKSO2 Note 2. Note 3. Note 4. Note 5. Caution MIN. MAX. 8/fMCK -- -- ns fMCK 20 MHz 6/fMCK 6/fMCK ns 2.7 V EVDD0 5.5 V 16 MHz fMCK 8/fMCK -- -- ns 6/fMCK 6/fMCK 6/fMCK ns 2.4 V EVDD0 5.5 V 6/fMCK and 500 6/fMCK and 500 6/fMCK and 500 ns 1.8 V EVDD0 5.5 V 6/fMCK and 750 6/fMCK and 750 6/fMCK and 750 ns 1.7 V EVDD0 5.5 V 6/fMCK and 1500 6/fMCK and 1500 6/fMCK and 1500 ns 1.6 V EVDD0 5.5 V -- 6/fMCK and 1500 6/fMCK and 1500 ns 4.0 V EVDD0 5.5 V tKCY2/2 - 7 tKCY2/2 - 7 tKCY2/2 - 7 ns 2.7 V EVDD0 5.5 V tKCY2/2 - 8 tKCY2/2 - 8 tKCY2/2 - 8 ns 1.8 V EVDD0 5.5 V tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 ns 1.7 V EVDD0 5.5 V tKCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 ns 1.6 V EVDD0 5.5 V -- tKCY2/2 - 66 tKCY2/2 - 66 ns 2.7 V EVDD0 5.5 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V EVDD0 5.5 V 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1.7 V EVDD0 5.5 V 1/fMCK + 40 1/fMCK + 40 1/fMCK + 40 ns 1.6 V EVDD0 5.5 V -- 1/fMCK + 40 1/fMCK + 40 ns 1.8 V EVDD0 5.5 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns 1.7 V EVDD0 5.5 V 1/fMCK + 250 1/fMCK + 250 1/fMCK + 250 ns 1.6 V EVDD0 5.5 V -- C = 30 pF Note 4 Note 3 Note 1. MAX. Unit 6/fMCK fMCK 16 MHz tKH2, tKL2 MIN. LV (low-voltage main) mode 4.0 V EVDD0 5.5 V 20 MHz fMCK time Note 5 SCKp high-/ low-level width MAX. (1/2) LS (low-speed main) mode 1/fMCK + 250 1/fMCK + 250 ns 2.7 V EVDD0 5.5 V 2/fMCK + 44 2/fMCK + 110 2/fMCK + 110 ns 2.4 V EVDD0 5.5 V 2/fMCK + 75 2/fMCK + 110 2/fMCK + 110 ns 1.8 V EVDD0 5.5 V 2/fMCK + 100 2/fMCK + 110 2/fMCK + 110 ns 1.7 V EVDD0 5.5 V 2/fMCK + 220 2/fMCK + 220 2/fMCK + 220 ns 1.6 V EVDD0 5.5 V -- 2/fMCK + 220 2/fMCK + 220 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 74 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 75 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SSI00 setup time SSI00 hold time Caution tSSIK tKSSI MAX. LS (low-speed main) mode MIN. (2/2) LV (low-voltage main) mode MAX. MIN. Unit MAX. DAPmn = 0 2.7 V EVDD0 5.5 V 120 120 120 ns 1.8 V EVDD0 5.5 V 200 200 200 ns 1.7 V EVDD0 5.5 V 400 400 400 ns 1.6 V EVDD0 5.5 V -- 400 400 ns DAPmn = 1 2.7 V EVDD0 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns 1.8 V EVDD0 5.5 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 ns 1.7 V EVDD0 5.5 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 ns 1.6 V EVDD0 5.5 V -- 1/fMCK + 400 1/fMCK + 400 ns DAPmn = 0 2.7 V EVDD0 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns 1.8 V EVDD0 5.5 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 ns 1.7 V EVDD0 5.5 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 ns 1.6 V EVDD0 5.5 V -- 1/fMCK + 400 1/fMCK + 400 ns DAPmn = 1 2.7 V EVDD0 5.5 V 120 120 120 ns 1.8 V EVDD0 5.5 V 200 200 200 ns 1.7 V EVDD0 5.5 V 400 400 400 ns 1.6 V EVDD0 5.5 V -- 400 400 ns Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp SCK SO User's device SI CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) SCK00 SI00 RL78 microcontroller SO00 SSI00 SCK SO User's device SI SSO Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 76 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tKSSI tSSIK SSI00 (CSI00 only) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tSSIK tKSSI SSI00 (CSI00 only) Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 77 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (5) During communication at same potential (simplified I2C mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) HS (high-speed main) mode Parameter Symbol Conditions SCLr clock frequency fSCL 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 400 Note 1 400 Note 1 kHz 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 400 Note 1 400 Note 1 400 Note 1 kHz 1.8 V EVDD0 2.7 V, Cb = 100 pF, Rb = 5 k 300 Note 1 300 Note 1 300 Note 1 kHz 1.7 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k 250 Note 1 250 Note 1 250 Note 1 kHz 1.6 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k -- 250 Note 1 250 Note 1 kHz MIN. Hold time when SCLr = "L" Hold time when SCLr = "H" tLOW tHIGH MAX. LS (low-speed main) mode (1/2) MIN. MAX. LV (low-voltage main) mode MIN. Unit MAX. 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1150 1150 ns 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1150 1150 1150 ns 1.8 V EVDD0 2.7 V, Cb = 100 pF, Rb = 5 k 1550 1550 1550 ns 1.7 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k 1850 1850 1850 ns 1.6 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k -- 1850 1850 ns 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1150 1150 ns 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1150 1150 1150 ns 1.8 V EVDD0 2.7 V, Cb = 100 pF, Rb = 5 k 1550 1550 1550 ns 1.7 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k 1850 1850 1850 ns 1.6 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k -- 1850 1850 ns (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 78 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (5) During communication at same potential (simplified I2C mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter HS (high-speed main) mode Symbol Conditions tSU: DAT 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 85 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns 1.8 V EVDD0 2.7 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 ns 1.7 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns 1.6 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k -- 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 ns 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 0 355 0 355 0 355 ns 1.8 V EVDD0 2.7 V, Cb = 100 pF, Rb = 5 k 0 405 0 405 0 405 ns 1.7 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k 0 405 0 405 0 405 ns 0 405 0 405 ns MIN. Data setup time (reception) Data hold time (transmission) tHD: DAT 1.6 V EVDD0 1.8 V, Cb = 100 pF, Rb = 5 k MAX. LS (low-speed main) mode MIN. -- Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution (2/2) MAX. LV (low-voltage main) mode MIN. Unit MAX. Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 79 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14), h: POM number (h = 0, 1, 3 to 5, 7, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 80 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. Transfer rate reception 4.0 V EVDD0 5.5 V, MAX. LS (low-speed main) mode MIN. MAX. (1/2) LV (low-voltage main) mode MIN. Unit MAX. fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps 5.3 1.3 0.6 Mbps fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps 5.3 1.3 0.6 Mbps bps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate fMCK/6 fMCK/6 fMCK/6 Notes 1, 2, 3 Notes 1, 2 Notes 1, 2 5.3 1.3 0.6 Mbps fMCK = fCLK Note 4 Note 1. Note 2. Note 3. Note 4. Caution Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Use it with EVDD0 Vb. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 2.7 V: MAX. 2.6 Mbps 1.8 V EVDD0 2.4 V: MAX. 1.3 Mbps The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb [V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is 1. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 81 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. Transfer rate transmission 4.0 V EVDD0 5.5 V, MAX. (2/2) LS (low-speed main) mode MIN. MAX. LV (low-voltage main) mode MIN. Unit MAX. Note 1 Note 1 Note 1 bps 2.8 Note 2 2.8 Note 2 2.8 Note 2 Mbps Note 3 Note 3 Note 3 bps 1.2 Note 4 1.2 Note 4 1.2 Note 4 Mbps Notes 5, 6 Notes 5, 6 Notes 5, 6 bps 0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V 1 [bps] Maximum transfer rate = 2.2 {-Cb Rb In (1 )} 3 Vb 1 Transfer rate 2 - {-Cb Rb In (1 - 2.2 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. Note 3. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = [bps] {-Cb Rb In (1 - 2.0 Vb )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 2.0 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. Note 5. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. Use it with EVDD0 Vb. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 82 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = [bps] {-Cb Rb In (1 - 1.5 Vb )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 1.5 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 83 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78 microcontroller User's device Tx RxDq UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is 1. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 84 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V EVDD0 5.5 V, MAX. (1/2) LS (low-speed main) mode MIN. MAX. LV (low-voltage main) mode MIN. Unit MAX. 200 1150 1150 ns 300 1150 1150 ns tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns tKCY1/2 - 7 tKCY1/2 - 50 tKCY1/2 - 50 ns tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 ns 58 479 479 ns 121 479 479 ns 10 10 10 ns 10 10 10 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp high-level width tKH1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level width tKL1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time tSIK1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (to SCKp) Note 1 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (from SCKp) Note 1 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKpto SOp output Note 1 tKSO1 4.0 V EVDD0 5.5 V, 60 60 60 ns 130 130 130 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k (Notes, Caution, and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 85 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SIp setup time tSIK1 4.0 V EVDD0 5.5 V, MAX. LS (low-speed main) mode MIN. MAX. (2/2) LV (low-voltage main) mode MIN. Unit MAX. 23 110 110 ns 33 110 110 ns 10 10 10 ns 10 10 10 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (to SCKp) Note 2 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (from SCKp) Note 2 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp tKSO1 to SOp output Note 2 4.0 V EVDD0 5.5 V, 10 10 10 ns 10 10 10 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin Note 1. products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) Remark 4. This value is valid only when CSI00's peripheral I/O redirect function is not used. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 86 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time tKCY1 tKCY1 4/fCLK MAX. (1/3) LS (low-speed main) mode MIN. MAX. LV (low-voltage main) mode MIN. Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 300 1150 1150 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 500 1150 1150 ns 1.8 V EVDD0 < 3.3 V, 1150 1150 1150 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V EVDD0 < 3.3 V, tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.8 V EVDD0 < 3.3 V, tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.6 V Vb 2.0 V Note, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 1.6 V Vb 2.0 V Note, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 1.6 V Vb 2.0 V Note, Cb = 30 pF, Rb = 5.5 k Note Use it with EVDD0 Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 87 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SIp setup time tSIK1 (to SCKp) Note 1 MAX. LS (low-speed main) mode MIN. MAX. (2/3) LV (low-voltage main) mode MIN. Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 81 479 479 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 177 479 479 ns 1.8 V EVDD0 < 3.3 V, 479 479 479 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 19 19 19 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 19 ns 1.8 V EVDD0 < 3.3 V, 19 19 19 ns 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 (from SCKp) Note 1 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp tKSO1 to SOp output Note 1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 100 100 100 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 195 195 195 ns 1.8 V EVDD0 < 3.3 V, 483 483 483 ns 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Use it with EVDD0 Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin Note 1. products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 88 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SIp setup time tSIK1 (to SCKp) Note 1 MAX. LS (low-speed main) mode MIN. MAX. (3/3) LV (low-voltage main) mode MIN. Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 44 110 110 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 44 110 110 ns 1.8 V EVDD0 < 3.3 V, 110 110 110 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 19 19 19 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 19 ns 1.8 V EVDD0 < 3.3 V, 19 19 19 ns 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k SIp hold time tKSI1 (from SCKp) Note 1 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp tKSO1 to SOp output Note 1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 25 25 25 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 25 25 25 ns 1.8 V EVDD0 < 3.3 V, 25 25 25 ns 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Use it with EVDD0 Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin Note 1. products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 89 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 CSI mode connection diagram (during communication at different potential <Master> Vb Vb Rb SCKp RL78 microcontroller Rb SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 90 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 91 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Symbol tKCY2 Note 1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V tSIK2 MIN. MIN. MAX. MAX. MAX. ns 20 MHz fMCK 24 MHz 12/fMCK -- -- ns 8 MHz fMCK 20 MHz 10/fMCK -- -- ns 4 MHz fMCK 8 MHz 8/fMCK 16/fMCK -- ns fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 24 MHz fMCK 20/fMCK -- -- ns 20 MHz fMCK 24 MHz 16/fMCK -- -- ns 16 MHz fMCK 20 MHz 14/fMCK -- -- ns 8 MHz fMCK 16 MHz 12/fMCK -- -- ns 4 MHz fMCK 8 MHz 8/fMCK 16/fMCK -- ns fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 24 MHz fMCK 48/fMCK -- -- ns 20 MHz fMCK 24 MHz 36/fMCK -- -- ns 16 MHz fMCK 20 MHz 32/fMCK -- -- ns 8 MHz fMCK 16 MHz 26/fMCK -- -- ns 4 MHz fMCK 8 MHz 16/fMCK 16/fMCK -- ns fMCK 4 MHz 10/fMCK 10/fMCK 10/fMCK ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 12 tKCY2/2 - 50 tKCY2/2 - 50 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 18 tKCY2/2 - 50 tKCY2/2 - 50 ns 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns (to SCKp) Note 3 SIp hold time MIN. Unit -- Note 2 SIp setup time LV (low-voltage main) mode -- 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V tKH2, tKL2 LS (low-speed main) mode 14/fMCK 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V SCKp high-/ low-level width 24 MHz fMCK HS (high-speed main) mode tKSI2 (from SCKp) Note 4 Delay time from SCKp to SOp output Note 5 tKSO2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2/fMCK + 120 2/fMCK + 573 2/fMCK + 573 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 2/fMCK + 573 2/fMCK + 573 ns 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rv = 5.5 k 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns (Notes, Cautions, and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 92 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Note 3. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Use it with EVDD0 Vb. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when Note 4. DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when Note 5. DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from Note 1. Note 2. SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (when 64- to 100-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 93 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 94 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCLr clock frequency fSCL MAX. LS (low-speed main) mode MIN. MAX. (1/2) LV (low-voltage main) mode MIN. Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 300 Note 1 300 Note 1 kHz 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 300 Note 1 300 Note 1 kHz 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 400 Note 1 300 Note 1 300 Note 1 kHz 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 400 Note 1 300 Note 1 300 Note 1 kHz 1.8 V EVDD0 < 3.3 V, 300 Note 1 300 Note 1 300 Note 1 kHz 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 475 1550 1550 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 475 1550 1550 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1150 1550 1550 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1150 1550 1550 ns 1.8 V EVDD0 < 3.3 V, 1550 1550 1550 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 245 610 610 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 200 610 610 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 675 610 610 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 600 610 610 ns 1.8 V EVDD0 < 3.3 V, 610 610 610 ns 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 95 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. Data setup time (reception) tSU:DAT LS (low-speed main) mode MAX. MIN. MAX. (2/2) LV (low-voltage main) mode MIN. Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1.8 V EVDD0 < 3.3 V, 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Data hold time (transmission) tHD:DAT 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 355 0 355 0 355 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 355 0 355 0 355 ns 1.8 V EVDD0 < 3.3 V, 0 405 0 405 0 405 ns 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with EVDD0 Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and V IL , see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 96 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User's device SCL SCLr Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 97 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.5.2 Serial interface IICA (1) I2C standard mode (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Conditions Standard mode: fCLK 1 MHz HS (high-speed main) mode tSU: STA tHD: STA MAX. MIN. MAX. MIN. MAX. 0 100 0 100 0 100 kHz 1.8 V EVDD0 5.5 V 0 100 0 100 0 100 kHz 1.7 V EVDD0 5.5 V 0 100 0 100 0 100 kHz 0 100 0 100 kHz -- 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s 4.7 4.7 s 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s -- 1.6 V EVDD0 5.5 V Hold time when SCLA0 = "L" tLOW 4.0 4.0 s 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s -- 1.6 V EVDD0 5.5 V Hold time when SCLA0 = "H" tHIGH Unit MIN. 1.6 V EVDD0 5.5 V Hold time Note 1 LV (low-voltage main) mode 2.7 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V Setup time of restart condition LS (low-speed main) mode (1/2) 4.7 4.7 s 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s 4.0 4.0 s 1.6 V EVDD0 5.5 V -- -- (Notes, Cautions, and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 98 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (1) I2C standard mode (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. Data setup time (reception) tSU: DAT tHD: DAT Note 2 tSU: STO tBUF MIN. MAX. 250 250 ns 1.8 V EVDD0 5.5 V 250 250 250 ns 1.7 V EVDD0 5.5 V 250 250 250 ns -- 250 250 ns 2.7 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s 1.8 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s 1.7 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s 0 3.45 0 3.45 s -- 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s 1.6 V EVDD0 5.5 V Bus-free time MAX. Unit 250 1.6 V EVDD0 5.5 V Setup time of stop condition MIN. LV (low-voltage main) mode 2.7 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V Data hold time (transmission) MAX. LS (low-speed main) mode (2/2) 4.0 4.0 s 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s 1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s 4.7 4.7 s 1.6 V EVDD0 5.5 V -- -- Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 99 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) I2C fast mode (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions 2.7 V EVDD0 5.5 V HS (high-speed main) mode LS (low-speed main) mode LV (low-voltage main) mode Unit MIN. MAX. MIN. MAX. MIN. MAX. 0 400 0 400 0 400 kHz 0 400 0 400 0 400 kHz SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz Setup time of restart condition tSU: STA 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s 1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s Hold time Note 1 tHD: STA 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s 1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s Hold time when SCLA0 = "L" tLOW 2.7 V EVDD0 5.5 V 1.3 1.3 1.3 s 1.8 V EVDD0 5.5 V 1.3 1.3 1.3 s Hold time when SCLA0 = "H" tHIGH 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s 1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s Data setup time (reception) tSU: DAT 2.7 V EVDD0 5.5 V 100 100 100 ns 1.8 V EVDD0 5.5 V 100 Data hold time (transmission) tHD: DAT 2.7 V EVDD0 5.5 V 0 0.9 1.8 V EVDD0 5.5 V 0 0.9 Setup time of stop condition tSU: STO 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s 1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s Bus-free time tBUF 2.7 V EVDD0 5.5 V 1.3 1.3 1.3 s 1.8 V EVDD0 5.5 V 1.3 1.3 1.3 s Note 2 1.8 V EVDD0 5.5 V 100 100 0 0.9 0 0.9 ns 0 0.9 s 0 0.9 s Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 k R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 100 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (3) I2C fast mode plus (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions 2.7 V EVDD0 5.5 V SCLA0 clock frequency fSCL Fast mode plus: fCLK 10 MHz Setup time of restart condition tSU: STA 2.7 V EVDD0 5.5 V Hold time Note 1 tHD: STA 2.7 V EVDD0 5.5 V Hold time when SCLA0 = "L" HS (high-speed main) mode LS (low-speed main) mode LV (low-voltage main) mode MIN. MAX. MIN. MIN. 0 1000 MAX. Unit MAX. -- -- kHz 0.26 -- -- s 0.26 -- -- s tLOW 2.7 V EVDD0 5.5 V 0.5 -- -- s Hold time when SCLA0 = "H" tHIGH 2.7 V EVDD0 5.5 V 0.26 -- -- s Data setup time (reception) tSU: DAT 2.7 V EVDD0 5.5 V 50 Data hold time (transmission) tHD: DAT 2.7 V EVDD0 5.5 V 0 Setup time of stop condition tSU: STO 2.7 V EVDD0 5.5 V 0.26 Bus-free time tBUF 2.7 V EVDD0 5.5 V 0.5 0.45 -- -- ns -- -- s -- -- s -- -- s Note 2 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Note 3. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLAn tHD: DAT tHD: STA tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT SDAAn tBUF Stop condition Remark Start condition Restart condition Stop condition n = 0, 1 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 101 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel ANI0 to ANI14 Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Refer to 2.6.1 (1). ANI16 to ANI20 Refer to 2.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 2.6.1 (1). Reference voltage (+) = VDD Reference voltage (-) = VSS Refer to 2.6.1 (3). Reference voltage (+) = VBGR Reference voltage (-)= AVREFM Refer to 2.6.1 (4). -- (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85 C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Overall error Symbol Conditions MIN. RES Note 1 Conversion time AINL tCONV Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage EZS EFS ILE DLE VAIN MAX. Unit 10 bit 1.2 3.5 LSB 1.2 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 7.0 LSB 10-bit resolution Target pin: ANI2 to ANI14 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 2.375 39 s 3.5625 39 s 17 39 s 10-bit resolution 3.6 V VDD 5.5 V Target pin: Internal reference voltage, 2.7 V VDD 5.5 V and temperature sensor output voltage 2.4 V VDD 5.5 V (HS (high-speed main) mode) Zero-scale error Notes 1, 2 TYP. 8 10-bit resolution 1.8 V AVREFP 5.5 V 0.25 %FSR AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 0.50 %FSR 10-bit resolution 1.8 V AVREFP 5.5 V 0.25 %FSR AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V 0.50 %FSR 10-bit resolution 1.8 V AVREFP 5.5 V 2.5 LSB AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V 5.0 LSB Note 4 Note 4 10-bit resolution 1.8 V AVREFP 5.5 V 1.5 LSB AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 2.0 LSB AVREFP V ANI2 to ANI14 0 Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 5 V Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 5 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.). Note 5. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 102 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI20 (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, 1.6 V AVREFP VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Overall error Note 1 AINL Conditions tCONV Zero-scale error Notes 1, 2 EZS 10-bit resolution 10-bit resolution Target ANI pin: ANI16 to ANI20 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Full-scale error Notes 1, 2 EFS 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Integral linearity error Note 1 ILE 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Differential linearity error Note 1 DLE 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Analog input voltage VAIN TYP. MAX. Unit 10 bit 1.2 5.0 LSB 1.2 8.5 LSB 8 EVDD0 AVREFP = VDD Notes 3, 4 Conversion time MIN. 1.8 V AVREFP 5.5 V 1.6 V AVREFP 5.5 V Note 5 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 1.8 V AVREFP 5.5 V 0.35 %FSR 1.6 V AVREFP 5.5 V Note 5 0.60 %FSR 1.8 V AVREFP 5.5 V 0.35 %FSR 1.6 V AVREFP 5.5 V Note 5 0.60 %FSR 1.8 V AVREFP 5.5 V 3.5 LSB 1.6 V AVREFP 5.5 V Note 5 6.0 LSB 1.8 V AVREFP 5.5 V 2.0 LSB 1.6 V AVREFP 5.5 V Note 5 2.5 LSB AVREFP and EVDD0 V ANI16 to ANI20 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When EVDD0 AVREFP VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. When AVREFP < EVDD0 VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. Note 5. When the conversion time is set to 57 s (min.) and 95 s (max.). R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 103 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI0 to ANI14, ANI16 to ANI20, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Resolution Overall error Symbol Conditions MIN. TYP. MAX. 10 bit 1.8 V VDD 5.5 V 1.2 7.0 LSB 1.6 V VDD 5.5 V Note 3 1.2 10.5 LSB RES Note 1 Conversion time Zero-scale error AINL tCONV Notes 1, 2 Full-scale error Notes 1, 2 EZS EFS 8 10-bit resolution 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 1.8 V VDD 5.5 V 0.60 %FSR 1.6 V VDD 5.5 V Note 3 0.85 %FSR 1.8 V VDD 5.5 V 0.60 %FSR 0.85 %FSR 4.0 LSB 6.5 LSB 2.0 LSB 2.5 LSB VDD V EVDD0 V 10-bit resolution 1.6 V VDD 5.5 V Integral linearity error Note 1 ILE 10-bit resolution Note 3 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Differential linearity error Note 3 1.8 V VDD 5.5 V DLE 10-bit resolution VAIN ANI0 to ANI14 0 ANI16 to ANI20 0 Note 1 1.6 V VDD 5.5 V Note 3 Analog input voltage Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. When the conversion time is set to 57 s (min.) and 95 s (max.). Note 4. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Unit Page 104 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI14, ANI16 to ANI20 (TA = -40 to +85 C, 2.4 V VDD 5.5 V, 1.6 V EVDD = EVDD1 VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. TYP. RES Conversion time Zero-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MAX. 8 tCONV 8-bit resolution 2.4 V VDD 5.5 V EZS 8-bit resolution ILE DLE bit 39 s 2.4 V VDD 5.5 V 0.60 % FSR 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB VBGR Note 3 V VAIN 17 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. Note 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Unit Page 105 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic (TA = -40 to +85 C, 2.4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25 C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the temperature Operation stabilization wait time tAMP 2.6.3 TYP. MAX. 1.05 1.38 Unit V 1.45 1.5 V mV/C -3.6 s 5 D/A converter characteristics (TA = -40 to +85 C, 1.6 V EVSS0 = EVSS1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Resolution RES Overall error AINL Settling time tSET R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Conditions MAX. Unit 8 bit 1.8 V VDD 5.5 V 2.5 LSB Rload = 8 M 1.8 V VDD 5.5 V 2.5 LSB Cload = 20 pF 2.7 V VDD 5.5 V 3 s 1.6 V VDD < 2.7 V 6 s Rload = 4 M MIN. TYP. Page 106 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.6.4 Comparator (TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Input voltage range Conditions MIN. Ivref Ivcmp Output delay td VDD = 3.0 V Input slew rate > 50 mV/s MAX. Unit 0 TYP. EVDD0 - 1.4 V -0.3 EVDD0 + 0.3 V Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 s 5.0 s Comparator low-speed mode, standard mode 3.0 High-electric-potential reference voltage VTW+ Comparator high-speed mode, window mode 0.76 VDD V Low-electric-potential reference voltage VTW- Comparator high-speed mode, window mode 0.24 VDD V Operation stabilization wait time tCMP Internal reference voltage VBGR s 100 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V Note Note 2.6.5 Not usable in LS (low-speed main) mode, LV (low-voltage main) mode, sub-clock operation, or STOP mode. POR circuit characteristics (TA = -40 to +85 C, VSS = 0 V) Parameter Symbol Detection voltage VPOR VPDR Minimum pulse width Note 2 Conditions Power supply rise time Power supply fall time Note 1 TPW MIN. TYP. MAX. Unit 1.47 1.51 1.55 V 1.46 1.50 1.54 V s 300 Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics. Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 107 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.6.6 LVD circuit characteristics (1) LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85 C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width Detection delay time R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 tLW MIN. TYP. MAX. Unit Power supply rise time Conditions 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V s 300 300 s Page 108 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85 C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Interrupt and reset mode Symbol VLVDA0 Conditions VLVDA1 LVIS1, LVIS0 = 1, 0 VLVDA2 LVIS1, LVIS0 = 0, 1 VLVDA3 VLVDB0 LVIS1, LVIS0 = 0, 0 TYP. MAX. Unit 1.60 1.63 1.66 V Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage VLVDB1 LVIS1, LVIS0 = 1, 0 1.80 1.84 1.87 V Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V 2.05 2.09 2.13 V VLVDB2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage 2.00 2.04 2.08 V VLVDB3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V 2.40 2.45 2.50 V VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage VLVDC1 LVIS1, LVIS0 = 1, 0 VLVDC2 LVIS1, LVIS0 = 0, 1 VLVDC3 VLVDD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V 2.70 2.75 2.81 V 2.86 2.92 2.97 V VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V VLVDD3 2.6.7 MIN. VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage LVIS1, LVIS0 = 0, 0 Power supply voltage rising slope characteristics (TA = -40 to +85 C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol SVDD Conditions MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 109 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85 C, VSS = 0V)) Parameter Data retention supply voltage Symbol Conditions MIN. TYP. MAX. Unit 5.5 V 1.46 Note VDDDR The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is Note effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.8 Flash Memory Programming Characteristics (TA = -40 to +85 C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. System clock frequency fCLK 1.8 V VDD 5.5 V Number of code flash rewrites Cerwr Retained for 20 years TA = 85 C Number of data flash rewrites Retained for 1 year TA = 25 C Notes 1, 2, 3 Retained for 5 years TA = 85 C 100,000 Retained for 20 years TA = 85 C 10,000 TYP. 1 MAX. Unit 32 MHz 1,000 Times Notes 1, 2, 3 1,000,000 Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self-programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 2.9 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 110 of 187 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C) RL78/G14 2.10 Timing for Switching Flash Memory Programming Modes (TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 100 ms How long from when an external reset ends until the initial communication settings are specified tSUINIT POR and LVD reset must end before the external reset ends. How long from when the TOOL0 pin is placed at the low level until an external reset ends tSU POR and LVD reset must end before the external reset ends. 10 s How long the TOOL0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset must end before the external reset ends. 1 ms <1> <2> <3> <4> RESET 723 s + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 111 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105 C)". Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. Caution 3. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products. Caution 4. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105 C. Derating is the systematic reduction of load for the sake of improved reliability. There are following differences between the products "G: Industrial applications (TA = -40 to + 105 C)" and the products "A: Consumer applications, and D: Industrial applications". Parameter A: Consumer applications, D: Industrial applications G: Industrial applications Operating ambient temperature TA = -40 to +85 C TA = -40 to +105 C Operating mode Operating voltage range HS (high-speed main) mode only: HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz High-speed on-chip oscillator clock accuracy 1.8 V VDD 5.5 V: 2.4 V VDD 5.5 V: 1.0% @ TA = -20 to +85 C 2.0% @ TA = +85 to +105 C 1.5% @ TA = -40 to -20 C 1.0% @ TA = -20 to +85 C 1.5% @ TA = -40 to -20 C 1.6 V VDD < 1.8 V: 5.0% @ TA = -20 to +85 C 5.5% @ TA = -40 to -20 C Serial array unit IICA UART CSI: fCLK/2 (16 Mbps supported), fCLK/4 UART CSI: fCLK/4 Simplified I2C communication Simplified I2C communication Standard mode Fast mode Standard mode Fast mode Fast mode plus Voltage detector Remark * Rising: 1.67 V to 4.06 V (14 stages) * Falling: 1.63 V to 3.98 V (14 stages) * Rising: 2.61 V to 4.06 V (8 stages) * Falling: 2.55 V to 3.98 V (8 stages) The electrical characteristics of the products G: Industrial applications (TA = -40 to + 105 C) are different from those of the products "A: Consumer applications, and D: Industrial applications". For details, refer to 3.1 to 3.10. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 112 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.1 Absolute Maximum Ratings Absolute Maximum Ratings Parameter Supply voltage REGC pin input voltage (1/2) Symbols Conditions Ratings Unit -0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V VIREGC REGC -0.3 to +2.8 V VDD and -0.3 to VDD +0.3 Note 1 Input voltage Output voltage Analog input voltage VI1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VI2 P60 to P63 (N-ch open-drain) VI3 P20 to P27, P121 to P124, P137, P150 to P156, EXCLK, EXCLKS, RESET VO1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 VO2 P20 to P27, P150 to P156 VAI1 ANI16 to ANI20 -0.3 to EVDD0 +0.3 -0.3 to +6.5 -0.3 to VDD +0.3 V Note 2 -0.3 to EVDD0 +0.3 and -0.3 to VDD +0.3 ANI0 to ANI14 V V Note 2 -0.3 to VDD +0.3 Note 2 -0.3 to EVDD0 +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 VAI2 V and -0.3 to VDD +0.3 Note 2 -0.3 to VDD +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 V V V Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 113 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Absolute Maximum Ratings Parameter Output current, high (2/2) Symbols IOH1 IOH2 Conditions Ratings Unit P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 -40 mA Total of all P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 pins -170 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 -70 mA -100 mA Per pin -0.5 mA -2 mA P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 40 mA Total of all P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 pins 170 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 70 mA 100 mA 1 mA 5 mA -40 to +105 C -65 to +150 C Per pin P20 to P27, P150 to P156 Total of all pins Output current, low IOL1 IOL2 Per pin Per pin P20 to P27, P150 to P156 Total of all pins Operating ambient temperature TA Storage temperature Tstg Caution In normal operation mode In flash memory programming mode Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 114 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.2 3.2.1 Oscillator Characteristics X1, XT1 characteristics (TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = 0 V) Resonator X1 clock oscillation frequency Resonator (fX) Note XT1 clock oscillation frequency (fXT) Note Ceramic resonator/ crystal resonator Conditions MIN. MAX. Unit 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD <2.7 V 1.0 16.0 Crystal resonator 32 TYP. 32.768 35 kHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G14 User's Manual Hardware. 3.2.2 On-chip oscillator characteristics (TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions fIH MIN. MAX. Unit 1 TYP. 32 MHz Notes 1, 2 High-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator clock frequency Low-speed on-chip oscillator clock frequency accuracy -20 to +85 C 2.4 V VDD 5.5 V -1.0 +1.0 % -40 to -20 C 2.4 V VDD 5.5 V -1.5 +1.5 % +85 to +105 C 2.4 V VDD 5.5 V -2.0 +2.0 % fIL 15 -15 kHz +15 % Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 115 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.3 3.3.1 DC Characteristics Pin characteristics (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output current, high Symbol Note 1 IOH1 Conditions Per pin for P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, MIN. (1/5) TYP. 2.4 V EVDD0 5.5 V MAX. Unit -3.0 mA Note 2 P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty 70% Note 3) Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 4.0 V EVDD0 5.5 V -30.0 mA 2.7 V EVDD0 < 4.0 V -10.0 mA 2.4 V EVDD0 < 2.7 V -5.0 mA 4.0 V EVDD0 5.5 V -30.0 mA 2.7 V EVDD0 < 4.0 V -19.0 mA 2.4 V EVDD0 < 2.7 V -10.0 mA 2.4 V EVDD0 5.5 V -60.0 mA -0.1 mA (When duty 70% Note 3) Total of all pins (When duty 70% IOH2 Note 3) Per pin for P20 to P27, P150 to P156 2.4 V VDD 5.5 V Total of all pins 2.4 V VDD 5.5 V (When duty 70% Note 2 -1.5 mA Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 116 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output current, low Note 1 Symbol IOL1 Conditions (2/5) MIN. TYP. Per pin for P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 MAX. Unit 8.5 mA Note 2 Per pin for P60 to P63 15.0 mA Note 2 Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty 70% Note 3) Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 4.0 V EVDD0 5.5 V 40.0 mA 2.7 V EVDD0 < 4.0 V 15.0 mA 2.4 V EVDD0 < 2.7 V 9.0 mA 4.0 V EVDD0 5.5 V 40.0 mA 2.7 V EVDD0 < 4.0 V 35.0 mA 2.4 V EVDD0 < 2.7 V 20.0 mA 80.0 mA 0.4 mA (When duty 70% Note 3) Total of all pins (When duty 70% Note 3) IOL2 Per pin for P20 to P27, P150 to P156 Total of all pins Note 2 2.4 V VDD 5.5 V 5.0 mA (When duty 70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1, and VSS pins. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 117 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input voltage, high Input voltage, low Caution Symbol Conditions MIN. (3/5) TYP. MAX. Unit 0.8 EVDD0 EVDD0 V VIH1 Normal input buffer P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VIH2 P01, P03, P04, P10, P14 to P17, TTL input buffer P30, P43, P44, P50, P53 to P55, 4.0 V EVDD0 5.5 V P80, P81, P142, P143 TTL input buffer 3.3 V EVDD0 < 4.0 V 2.2 EVDD0 V 2.0 EVDD0 V TTL input buffer 2.4 V EVDD0 < 3.3 V 1.5 EVDD0 V 0.7 VDD VDD V 0.7 EVDD0 6.0 V 0.8 VDD VDD V VIH3 P20 to P27, P150 to P156 VIH4 P60 to P63 VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET VIL1 Normal input buffer P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 0 0.2 EVDD0 V VIL2 P01, P03, P04, P10, P14 to P17, TTL input buffer P30, P43, P44, P50, P53 to P55, 4.0 V EVDD0 5.5 V P80, P81, P142, P143 TTL input buffer 3.3 V EVDD0 < 4.0 V 0 0.8 V 0 0.5 V TTL input buffer 2.4 V EVDD0 < 3.3 V 0 0.32 V VIL3 P20 to P27, P150 to P156 0 0.3 VDD V VIL4 P60 to P63 0 0.3 EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V The maximum value of VIH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 118 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Output voltage, high Output voltage, low Caution Symbol VOH1 Conditions P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 4.0 V EVDD0 5.5 V, MIN. (4/5) TYP. MAX. Unit EVDD0 - 0.7 V 2.7 V EVDD0 5.5 V, IOH1 = -2.0 mA EVDD0 - 0.6 V 2.4 V EVDD0 5.5 V, IOH1 = -1.5 mA EVDD0 - 0.5 V VDD - 0.5 V IOH1 = -3.0 mA VOH2 P20 to P27, P150 to P156 2.4 V VDD 5.5 V, IOH2 = -100 A VOL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 4.0 V EVDD0 5.5 V, 0.7 V 2.7 V EVDD0 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V EVDD0 5.5 V, IOL1 = 1.5 mA 0.4 V 2.4 V EVDD0 5.5 V, IOL1 = 0.6 mA 0.4 V IOL1 = 8.5 mA VOL2 P20 to P27, P150 to P156 2.4 V VDD 5.5 V, IOL2 = 400 A 0.4 V VOL3 P60 to P63 4.0 V EVDD0 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V EVDD0 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V EVDD0 5.5 V, IOL3 = 3.0 mA 0.4 V 2.4 V EVDD0 5.5 V, IOL3 = 2.0 mA 0.4 V P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 119 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input leakage current, high Input leakage current, low On-chip pull-up resistance Remark Symbol Conditions (5/5) MIN. TYP. MAX. Unit ILIH1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VI = EVDD0 1 A ILIH2 P20 to P27, P137, P150 to P156, RESET VI = VDD 1 A ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VDD In input port or external clock input 1 A In resonator connection 10 A ILIL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VI = EVSS0 -1 A ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS -1 A ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VSS In input port or external clock input -1 A In resonator connection -10 A 100 k RU P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 VI = EVSS0, In input port 10 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 120 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +105 C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) Parameter Supply current IDD1 (1/2) Conditions Symbol Operating HS (high-speed main) mode mode Note 5 MIN. fHOCO = 64 MHz, fIH = 32 MHz Note 3 TYP. MAX. Basic operation VDD = 5.0 V 2.4 VDD = 3.0 V 2.4 Basic operation VDD = 5.0 V 2.1 VDD = 3.0 V 2.1 Normal operation VDD = 5.0 V 5.2 9.3 VDD = 3.0 V 5.2 9.3 Normal operation VDD = 5.0 V 4.8 8.7 VDD = 3.0 V 4.8 8.7 Normal operation VDD = 5.0 V 4.1 7.3 VDD = 3.0 V 4.1 7.3 Unit mA Note 1 fHOCO = 32 MHz, fIH = 32 MHz Note 3 HS (high-speed main) fHOCO = 64 MHz, mode Note 5 fIH = 32 MHz Note 3 fHOCO = 32 MHz, fIH = 32 MHz Note 3 fHOCO = 48 MHz, fIH = 24 MHz Note 3 fHOCO = 24 MHz, Normal operation VDD = 5.0 V 3.8 6.7 VDD = 3.0 V 3.8 6.7 Normal operation VDD = 5.0 V 2.8 4.9 fIH = 16 MHz Note 3 VDD = 3.0 V 2.8 4.9 fMX = 20 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 3.3 5.7 Resonator connection 3.5 5.8 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.3 5.7 Resonator connection 3.5 5.8 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.0 3.4 Resonator connection 2.1 3.5 Note 2, Normal operation Square wave input 2.0 3.4 Resonator connection 2.1 3.5 fSUB = 32.768 kHz Note 4 Normal operation TA = -40 C Square wave input 4.7 6.1 Resonator connection 4.7 6.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +25 C Square wave input 4.7 6.1 Resonator connection 4.7 6.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +50 C Square wave input 4.8 6.7 Resonator connection 4.8 6.7 Normal operation Square wave input 4.8 7.5 Resonator connection 4.8 7.5 fSUB = 32.768 kHz Note 4 Normal operation TA = +85 C Square wave input 5.4 8.9 Resonator connection 5.4 8.9 Normal operation Square wave input 7.2 21.0 Resonator connection 7.3 21.1 fIH = 24 MHz Note 3 fHOCO = 16 MHz, HS (high-speed main) mode Note 5 fMX = 10 MHz VDD = 3.0 V Subsystem clock operation fSUB = 32.768 kHz TA = +70 C fSUB = 32.768 kHz TA = +105 C Note 4 Note 4 mA mA A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 121 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 122 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +105 C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) Parameter Symbol Supply current IDD2 Note 1 (2/2) Conditions HALT mode Note 2 MIN. TYP. MAX. Unit mA HS (high-speed main) fHOCO = 64 MHz, VDD = 5.0 V 0.80 4.36 mode Note 7 VDD = 3.0 V 0.80 4.36 fHOCO = 32 MHz, VDD = 5.0 V 0.54 3.67 fIH = 32 MHz Note 4 VDD = 3.0 V 0.54 3.67 fHOCO = 48 MHz, VDD = 5.0 V 0.62 3.42 fIH = 24 MHz Note 4 VDD = 3.0 V 0.62 3.42 fHOCO = 24 MHz, VDD = 5.0 V 0.44 2.85 fIH = 24 MHz Note 4 VDD = 3.0 V 0.44 2.85 fHOCO = 16 MHz, VDD = 5.0 V 0.40 2.08 fIH = 16 MHz Note 4 VDD = 3.0 V 0.40 2.08 HS (high-speed main) fMX = 20 MHz Note 3, mode Note 7 VDD = 5.0 V Square wave input 0.28 2.45 Resonator connection 0.49 2.57 fMX = 20 MHz Note 3, VDD = 3.0 V Square wave input 0.28 2.45 Resonator connection 0.49 2.57 fMX = 10 MHz Note 3, VDD = 5.0 V Square wave input 0.19 1.28 Resonator connection 0.30 1.36 Note 3, Square wave input 0.19 1.28 Resonator connection 0.30 1.36 fSUB = 32.768 kHz Note 5, Square wave input TA = -40 C Resonator connection 0.25 0.57 0.44 0.76 fSUB = 32.768 kHz Note 5, Square wave input TA = +25 C Resonator connection 0.30 0.57 0.49 0.76 fSUB = 32.768 kHz Note 5, Square wave input TA = +50 C Resonator connection 0.36 1.17 0.59 1.36 Square wave input 0.49 1.97 Resonator connection 0.72 2.16 fSUB = 32.768 kHz Note 5, Square wave input TA = +85 C Resonator connection 0.97 3.37 1.16 3.56 Square wave input 3.20 17.10 Resonator connection 3.40 17.50 fIH = 32 MHz Note 4 fMX = 10 MHz VDD = 3.0 V Subsystem clock operation fSUB = 32.768 kHz TA = +70 C fSUB = 32.768 kHz TA = +105 C Note 5, Note 5, IDD3 STOP mode TA = -40 C 0.18 0.51 Note 6 Note 8 TA = +25 C 0.24 0.51 TA = +50 C 0.29 1.10 TA = +70 C 0.41 1.90 TA = +85 C 0.90 3.30 TA = +105 C 3.10 17.00 mA A A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 123 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD , EV DD0 or V SS , EVSS0 . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 124 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD1 Conditions (1/2) MIN. Operating HS (high-speed main) fHOCO = 64 MHz, mode mode Note 5 fIH = 32 MHz Note 3 Basic operation TYP. VDD = 5.0 V 2.6 VDD = 3.0 V 2.6 MAX. Unit mA Note 1 fHOCO = 32 MHz, fIH = 32 MHz Note 3 HS (high-speed main) fHOCO = 64 MHz, mode Note 5 fIH = 32 MHz Note 3 fHOCO = 32 MHz, Basic operation VDD = 5.0 V 2.3 VDD = 3.0 V 2.3 Normal operation VDD = 5.0 V 5.8 10.9 VDD = 3.0 V 5.8 10.9 VDD = 5.0 V 5.4 10.3 VDD = 3.0 V 5.4 10.3 Normal operation fIH = 32 MHz Note 3 fHOCO = 48 MHz, Normal operation fIH = 24 MHz Note 3 fHOCO = 24 MHz, fIH = 24 MHz Note 3 fHOCO = 16 MHz, fIH = 16 MHz Note 3 VDD = 5.0 V 4.5 8.2 VDD = 3.0 V 4.5 8.2 Normal operation VDD = 5.0 V 4.2 7.8 VDD = 3.0 V 4.2 7.8 Normal operation VDD = 5.0 V 3.1 5.6 VDD = 3.0 V 3.1 5.6 HS (high-speed main) fMX = 20 MHz Note 2, VDD = 5.0 V mode Note 5 Normal operation Square wave input 3.7 6.6 Resonator connection 3.9 6.7 fMX = 20 MHz Note 2, VDD = 3.0 V Normal operation Square wave input 3.7 6.6 Resonator connection 3.9 6.7 fMX = 10 MHz Note 2, VDD = 5.0 V Normal operation Square wave input 2.2 3.9 Resonator connection 2.3 4.0 Note 2, Normal operation Square wave input 2.2 3.9 Resonator connection 2.3 4.0 fSUB = 32.768 kHz Note 4 Normal operation TA = -40 C Square wave input 5.0 7.1 Resonator connection 5.0 7.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +25 C Square wave input 5.0 7.1 Resonator connection 5.0 7.1 fSUB = 32.768 kHz Note 4 Normal operation TA = +50 C Square wave input 5.1 8.8 Resonator connection 5.1 8.8 Normal operation Square wave input 5.5 10.5 Resonator connection 5.5 10.5 fSUB = 32.768 kHz Note 4 Normal operation TA = +85 C Square wave input 6.5 14.5 Resonator connection 6.5 14.5 Normal operation Square wave input 13.0 58.0 Resonator connection 13.0 58.0 fMX = 10 MHz VDD = 3.0 V Subsystem clock operation fSUB = 32.768 kHz TA = +70 C fSUB = 32.768 kHz TA = +105 C Note 4 Note 4 mA mA A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 125 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EV SS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 126 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply IDD2 current Note 1 Note 2 Conditions HALT mode (2/2) MIN. TYP. MAX. Unit mA HS (high-speed main) fHOCO = 64 MHz, VDD = 5.0 V 0.88 4.86 mode Note 7 fIH = 32 MHz Note 4 VDD = 3.0 V 0.88 4.86 fHOCO = 32 MHz, VDD = 5.0 V 0.62 4.17 fIH = 32 MHz Note 4 VDD = 3.0 V 0.62 4.17 fHOCO = 48 MHz, VDD = 5.0 V 0.68 3.82 fIH = 24 MHz Note 4 VDD = 3.0 V 0.68 3.82 fHOCO = 24 MHz, VDD = 5.0 V 0.50 3.25 fIH = 24 MHz Note 4 VDD = 3.0 V 0.50 3.25 fHOCO = 16 MHz, VDD = 5.0 V 0.44 2.28 fIH = 16 MHz Note 4 VDD = 3.0 V 0.44 2.28 fMX = 20 MHz Note 3, VDD = 5.0 V Square wave input 0.37 2.65 Resonator connection 0.50 2.77 fMX = 20 MHz Note 3, VDD = 3.0 V Square wave input 0.37 2.65 Resonator connection 0.50 2.77 fMX = 10 MHz Note 3, VDD = 5.0 V Square wave input 0.21 1.36 Resonator connection 0.30 1.46 Note 3, Square wave input 0.21 1.36 Resonator connection 0.30 1.46 Square wave input 0.28 0.66 Resonator connection 0.47 0.85 fSUB = 32.768 kHz Note 5, TA = +25 C Square wave input 0.34 0.66 Resonator connection 0.53 0.85 fSUB = 32.768 kHz Note 5, TA = +50 C Square wave input 0.37 2.35 Resonator connection 0.56 2.54 Note 5, Square wave input 0.61 4.08 Resonator connection 0.80 4.27 fSUB = 32.768 kHz Note 5, TA = +85 C Square wave input 1.55 8.09 Resonator connection 1.74 8.28 Note 5, Square wave input 6.00 51.00 Resonator connection 6.00 51.00 HS (high-speed main) mode Note 7 fMX = 10 MHz VDD = 3.0 V Subsystem clock operation fSUB = 32.768 kHz Note 5, TA = -40 C fSUB = 32.768 kHz TA = +70 C fSUB = 32.768 kHz TA = +105 C IDD3 STOP mode TA = -40 C 0.19 0.57 Note 6 Note 8 TA = +25 C 0.25 0.57 TA = +50 C 0.33 2.26 TA = +70 C 0.52 3.99 TA = +85 C 1.46 8.00 TA = +105 C 5.50 50.00 mA A A (Notes and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 127 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EV SS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 128 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (3) Peripheral Functions (Common to all products) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note 1 0.20 A RTC operating current IRTC Notes 1, 2, 3 0.02 A 12-bit interval timer operating current IIT Notes 1, 2, 4 0.02 A Watchdog timer operating current IWDT Notes 1, 2, 5 fIL = 15 kHz 0.22 A A/D converter operating current IADC Notes 1, 6 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter reference voltage current IADREF Note 1 75.0 A Temperature sensor operating current ITMPS Note 1 75.0 A D/A converter operating current IDAC Notes 1, 11, 13 Comparator operating current ICMP Notes 1, 12, 13 VDD = 5.0 V, Regulator output voltage = 2.1 V Window mode 12.5 A Comparator high-speed mode 6.5 A Comparator low-speed mode 1.7 A VDD = 5.0 V, Regulator output voltage = 1.8 V Window mode 8.0 A Comparator high-speed mode 4.0 A Comparator low-speed mode 1.3 A Per D/A converter channel 1.5 mA A LVD operating current ILVD Notes 1, 7 0.08 Self-programming operating current IFSP Notes 1, 9 2.50 12.20 mA BGO operating current IBGO Notes 1, 8 2.50 12.20 mA SNOOZE operating current ISNOZ Note 1 The mode is performed Note 10 0.50 1.10 mA The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V 1.20 2.04 CSI/UART operation 0.70 1.54 DTC operation 3.10 ADC operation Note 1. Current flowing to VDD. Note 2. When high speed on-chip oscillator and high-speed system clock are stopped. Note 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 129 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Note 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Note 8. Current flowing during programming of the data flash. Note 9. Current flowing during self-programming. Note 10. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/G14 User's Manual Hardware. Note 11. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IDAC when the D/A converter operates in an operation mode or the HALT mode. Note 12. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and ICMP when the comparator circuit is in operation. Note 13. A comparator and D/A converter are provided in products with 96 KB or more code flash memory. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25 C R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 130 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.4 AC Characteristics (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) (1/2) MIN. HS (high-speed main) 2.7 V VDD 5.5 V mode 2.4 V VDD < 2.7 V operation Unit 0.03125 1 s 0.0625 1 s 31.3 s 0.03125 1 s 0.0625 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 MHz 32 35 kHz Subsystem clock (fSUB) operation 2.4 V VDD 5.5 V TYP. MAX. HS (high-speed main) 2.7 V VDD 5.5 V In the selfprogramming mode 2.4 V VDD < 2.7 V mode 28.5 30.5 External system clock frequency fEX External system clock input high-level width, low-level width tEXH, 2.7 V VDD 5.5 V 24 ns tEXL 2.4 V VDD 2.7 V 30 ns 13.7 s 1/fMCK + 10 ns fEXS tEXHS, tEXLS TI00 to TI03, TI10 to TI13 input high-level width, low-level width tTIH, tTIL Timer RJ input cycle fC Timer RJ input highlevel width, low-level width Note Note tTJIH, TRJIO TRJIO tTJIL 2.7 V EVDD0 5.5 V 100 ns 2.4 V EVDD0 < 2.7 V 300 ns 2.7 V EVDD0 5.5 V 40 ns 2.4 V EVDD0 < 2.7 V 120 ns The following conditions are required for low voltage interface when EVDD0 < VDD 2.4 V EVDD0 < 2.7 V: MIN. 125 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 131 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions Timer RD input high-level width, low-level width tTDIH, tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 Timer RD forced cutoff signal input low-level width tTDSIL P130/INTP0 Timer RG input high-level width, low-level width TO00 to TO03, TO10 to TO13, tTGIH, TRGIOA, TRGIOB MIN. TYP. MAX. Unit 3/fCLK ns 1 s 1/fCLK + 1 2.5/fCLK ns tTGIL fTO HS (high-speed main) mode TRJIO0, TRJO0, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRGIOA, TRGIOB output frequency PCLBUZ0, PCLBUZ1 output 2MHz < fCLK 32 MHz fCLK 2 MHz (2/2) fPCL HS (high-speed main) mode frequency 4.0 V EVDD0 5.5 V 16 MHz 2.7 V EVDD0 < 4.0 V 8 MHz 2.4 V EVDD0 < 2.7 V 4 MHz 4.0 V EVDD0 5.5 V 16 MHz 2.7 V EVDD0 < 4.0 V 8 MHz 2.4 V EVDD0 < 2.7 V 4 MHz Interrupt input high-level width, low-level width tINTH, INTP0 2.4 V VDD 5.5 V tINTL INTP1 to INTP11 Key interrupt input low-level width tKR KR0 to KR7 RESET low-level width tRSL R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 1 s 2.4 V EVDD0 5.5 V 1 s 2.4 V EVDD0 5.5 V 250 ns 10 s Page 132 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 133 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS EXCLK/EXCLKS TI/TO Timing tTIL tTIH TI00 to TI03, TI10 to TI13 1/fTO TO00 to TO03, TO10 to TO13, TRJIO0, TRJO0, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1, TRGIOA, TRGIOB R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 134 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 tTJIH tTJIL TRJIO tTDIH tTDIL TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 tTDSIL INTP0 tTGIL tTGIH TRGIOA, TRGIOB R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 135 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 136 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note 1 2.4 V EVDD0 5.5 V MAX. fMCK/12 Note 2 bps 2.6 Mbps Theoretical value of the maximum transfer rate fMCK = Unit fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Note 2. The following conditions are required for low voltage interface when EVDD0 VDD. 2.4 V EVDD0 2.7 V: MAX. 1.3 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq RL78 microcontroller User's device Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 137 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time tKCY1 SCKp high-/low-level width tKH1, tKL1 tKCY1 4/fCLK 2.7 V EVDD0 5.5 V 2.4 V EVDD0 5.5 V SIp setup time (to SCKp) tSIK1 Note 1 Delay time from SCKp to SOp output Note 3 tKSO1 MAX. 250 ns 500 ns 4.0 V EVDD0 5.5 V tKCY1/2 - 24 ns 2.7 V EVDD0 5.5 V tKCY1/2 - 36 ns 2.4 V EVDD0 5.5 V tKCY1/2 - 76 ns 4.0 V EVDD0 5.5 V 66 ns 2.7 V EVDD0 5.5 V 66 ns 2.4 V EVDD0 5.5 V 113 ns 38 ns tKSI1 SIp hold time (from SCKp) Note 2 Unit C = 30 pF Note 4 50 ns Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 138 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. SCKp cycle time tKCY2 Note 5 4.0 V EVDD0 5.5 V tKH2, tKL2 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 tSIK2 MAX. 16/fMCK ns fMCK 20 MHz 12/fMCK ns 16 MHz fMCK 16/fMCK ns fMCK 16 MHz 12/fMCK ns 2.4 V EVDD0 5.5 V 12/fMCK and 1000 ns 4.0 V EVDD0 5.5 V tKCY2/2 - 14 ns 2.7 V EVDD0 5.5 V tKCY2/2 - 16 ns 2.4 V EVDD0 5.5 V tKCY2/2 - 36 ns 2.7 V EVDD0 5.5 V 1/fMCK + 40 ns 2.4 V EVDD0 5.5 V 1/fMCK + 60 ns 1/fMCK + 62 ns tKSI2 Delay time from SCKp to SOp output Note 3 tKSO2 Unit 20 MHz fMCK 2.7 V EVDD0 5.5 V SCKp high-/low-level width (1/2) HS (high-speed main) mode C = 30 pF Note 4 2.7 V EVDD0 5.5 V 2/fMCK + 66 ns 2.4 V EVDD0 5.5 V 2/fMCK + 113 ns Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 139 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. SSI00 setup time DAPmn = 0 tSSIK DAPmn = 1 SSI00 hold time DAPmn = 0 tKSSI DAPmn = 1 Caution (2/2) HS (high-speed main) mode Unit MAX. 2.7 V EVDD0 5.5 V 240 ns 2.4 V EVDD0 5.5 V 400 ns 2.7 V EVDD0 5.5 V 1/fMCK + 240 ns 2.4 V EVDD0 5.5 V 1/fMCK + 400 ns 2.7 V EVDD0 5.5 V 1/fMCK + 240 ns 2.4 V EVDD0 5.5 V 1/fMCK + 400 ns 2.7 V EVDD0 5.5 V 240 ns 2.4 V EVDD0 5.5 V 400 ns Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp SCK SO User's device SI CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) SCK00 SI00 RL78 microcontroller SO00 SSI00 SCK SO User's device SI SSO Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 140 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tKSSI tSSIK SSI00 (CSI00 only) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tSSIK tKSSI SSI00 (CSI00 only) Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 141 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (4) During communication at same potential (simplified I2C mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Data hold time (transmission) fSCL tLOW tHIGH tSU: DAT tHD: DAT 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 2.4 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 100 Note 1 kHz 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 4600 ns 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 4600 ns 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 220 Note 2 ns 2.4V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 580 Note 2 ns 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.4 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 0 1420 ns Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Unit MAX. Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 142 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User's device SCL SCLr Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14), h: POM number (h = 0, 1, 3 to 5, 7, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 143 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. Transfer rate reception (1/2) HS (high-speed main) mode 4.0 V EVDD0 5.5 V, Unit MAX. fMCK/12 Note 1 bps 2.6 Mbps fMCK/12 Note 1 bps 2.6 Mbps fMCK/12 Notes 1, 2 bps 2.6 Mbps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Note 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 2.7 V: MAX. 1.3 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb [V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is 1. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 144 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions (2/2) HS (high-speed main) mode MIN. Transfer rate transmission Unit MAX. 4.0 V EVDD0 5.5 V, Note 1 bps 2.6 Note 2 Mbps Note 3 bps 1.2 Note 4 Mbps Note 5 bps 0.43 Note 6 Mbps 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = [bps] 2.2 )} 3 {-Cb Rb In (1 Vb 1 Transfer rate 2 - {-Cb Rb In (1 - 2.2 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V 1 [bps] Maximum transfer rate = {-Cb Rb In (1 - 2.0 )} 3 Vb 1 Transfer rate 2 - {-Cb Rb In (1 - 2.0 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 145 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = [bps] {-Cb Rb In (1 - 1.5 Vb )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 1.5 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 6. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 146 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78 microcontroller User's device Tx RxDq UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is 1. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 147 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time SCKp high-level width SCKp low-level width Caution tKCY1 tKH1 tKL1 tKCY1 4/fCLK (1/3) Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 600 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1000 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 2300 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 150 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 340 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 916 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 24 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 36 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 100 ns Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 148 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SIp setup time (to SCKp) Note SIp hold time (from SCKp) Note Delay time from SCKp to SOp output Note tSIK1 tKSI1 tKSO1 (2/3) Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 162 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 354 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 958 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 38 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 38 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 38 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 200 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 390 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 966 ns Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 149 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SIp setup time (to SCKp) Note SIp hold time (from SCKp) Note Delay time from SCKp to SOp output Note tSIK1 tKSI1 tKSO1 (3/3) Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 88 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 88 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 220 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 38 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 38 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 38 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 50 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 50 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 50 ns Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 150 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 CSI mode connection diagram (during communication at different potential <Master> Vb Vb Rb SCKp RL78 microcontroller Rb SCK SIp SO SOp SI User's device Remark 5. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 6. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 7. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) Remark 8. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 151 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 152 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time Note 1 tKCY2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V 24 MHz fMCK 28/fMCK ns 20 MHz fMCK 24 MHz 24/fMCK ns 8 MHz fMCK 20 MHz 20/fMCK ns 4 MHz fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 24 MHz fMCK 40/fMCK ns 20 MHz fMCK 24 MHz 32/fMCK ns 16 MHz fMCK 20 MHz 28/fMCK ns 8 MHz fMCK 16 MHz 24/fMCK ns 4 MHz fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 24 MHz fMCK 96/fMCK ns 20 MHz fMCK 24 MHz 72/fMCK ns 16 MHz fMCK 20 MHz 64/fMCK ns 8 MHz fMCK 16 MHz 52/fMCK ns 4 MHz fMCK 8 MHz 32/fMCK ns fMCK 4 MHz SCKp high-/low-level width SIp setup time tKH2, tKL2 tSIK2 (to SCKp) Note 2 SIp hold time Unit MAX. 20/fMCK ns tKCY2/2 - 24 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 36 ns 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V tKCY2/2 - 100 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 40 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 40 ns 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V 1/fMCK + 60 ns 1/fMCK + 62 ns tKSI2 (from SCKp) Note 3 Delay time from SCKp tKSO2 to SOp output Note 4 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2/fMCK + 240 ns 2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 428 ns 2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rv = 5.5 k 2/fMCK + 1146 ns (Notes, Cautions, and Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 153 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (when 64- to 100-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 154 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 155 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 fSCL tLOW tHIGH (1/2) Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 100 Note 1 kHz 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 100 Note 1 kHz 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 100 Note 1 kHz 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 4600 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 4600 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 4650 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 620 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 500 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2700 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2400 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 1830 ns Page 156 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT (2/2) Unit MAX. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 Note 2 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 Note 2 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 760 Note 2 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 760 Note 2 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 570 Note 2 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 1420 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 1420 ns 2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k 0 1215 ns Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and V IL , see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 157 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User's device SCL SCLr Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 158 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.5.2 Serial interface IICA (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Standard mode Fast mode: fCLK 3.5 MHz Unit Fast mode MIN. MAX. MIN. MAX. -- -- 0 400 kHz 0 100 -- -- kHz SCLA0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 0.6 s Hold time Note 1 tHD: STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s Data setup time (reception) tSU: DAT 250 Data hold time (transmission) Note 2 tHD: DAT 0 Setup time of stop condition tSU: STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Standard mode: fCLK 1 MHz Note 1. Note 2. 100 3.45 0 ns 0.9 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLAn tHD: DAT tHD: STA tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT SDAAn tBUF Stop condition Remark Start condition Restart condition Stop condition n = 0, 1 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 159 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Input channel ANI0 to ANI14 Refer to 3.6.1 (1). ANI16 to ANI20 Refer to 3.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 3.6.1 (1). Reference voltage (+) = VDD Reference voltage (-) = VSS Refer to 3.6.1 (3). Reference voltage (+) = VBGR Reference voltage (-)= AVREFM Refer to 3.6.1 (4). -- (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105 C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Overall error Note 1 AINL Conditions MIN. TYP. MAX. Unit 10 bit 3.5 LSB 39 s 8 2.4 V AVREFP 5.5 V 10-bit resolution 1.2 AVREFP = VDD Note 3 Conversion time Zero-scale error tCONV Notes 1, 2 EZS 10-bit resolution Target pin: ANI2 to ANI14 3.6 V VDD 5.5 V 2.125 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 2.4 V AVREFP 5.5 V 0.25 %FSR 2.4 V AVREFP 5.5 V 0.25 %FSR 2.4 V AVREFP 5.5 V 2.5 LSB 2.4 V AVREFP 5.5 V 1.5 LSB AVREFP V AVREFP = VDD Note 3 Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Note 3 Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 Analog input voltage VAIN ANI2 to ANI14 0 Internal reference voltage output (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 160 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI20 (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, 2.4 V AVREFP VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Overall error Note 1 AINL Conditions MIN. TYP. MAX. Unit 10 bit 5.0 LSB 8 2.4 V AVREFP 5.5 V 10-bit resolution 1.2 EVDD0 AVREFP = VDD Notes 3, 4 Conversion time Zero-scale error tCONV Notes 1, 2 EZS 10-bit resolution Target ANI pin: ANI16 to ANI20 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 2.4 V AVREFP 5.5 V 0.35 %FSR 2.4 V AVREFP 5.5 V 0.35 %FSR 2.4 V AVREFP 5.5 V 3.5 LSB 2.4 V AVREFP 5.5 V 2.0 LSB AVREFP and EVDD0 V EVDD0 AVREFP = VDD Notes 3, 4 Full-scale error Notes 1, 2 EFS 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Integral linearity error Note 1 ILE 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Differential linearity error Note 1 DLE 10-bit resolution EVDD0 AVREFP = VDD Notes 3, 4 Analog input voltage VAIN ANI16 to ANI20 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When EVDD0 AVREFP VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. When AVREFP < EVDD0 VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 161 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI0 to ANI14, ANI16 to ANI20, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Resolution Overall error Symbol Conditions MIN. RES Note 1 Conversion time TYP. MAX. 10 bit 1.2 7.0 LSB 8 Unit AINL 10-bit resolution 2.4 V VDD 5.5 V tCONV 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR Integral linearity error Note 1 ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB Differential linearity error DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB VAIN ANI0 to ANI14 0 VDD V ANI16 to ANI20 0 EVDD0 V Zero-scale error Full-scale error Notes 1, 2 Notes 1, 2 Note 1 Analog input voltage Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 162 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI14, ANI16 to ANI20 (TA = -40 to +105 C, 2.4 V VDD 5.5 V, 1.6 V EVDD = EVDD1 VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. TYP. RES Conversion time Zero-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MAX. 8 tCONV 8-bit resolution 2.4 V VDD 5.5 V EZS 8-bit resolution ILE DLE bit 39 s 2.4 V VDD 5.5 V 0.60 % FSR 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB VBGR Note 3 V VAIN 17 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. Note 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Unit Page 163 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic (TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25 C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the 3.6.3 MAX. 1.05 1.38 1.45 1.5 V mV/C s 5 tAMP Unit V -3.6 temperature Operation stabilization wait time TYP. D/A converter characteristics (TA = -40 to +105 C, 2.4 V EVSS0 = EVSS1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 bit Resolution RES Overall error AINL Rload = 4 M 2.4 V VDD 5.5 V 2.5 LSB Rload = 8 M 2.4 V VDD 5.5 V 2.5 LSB Settling time tSET Cload = 20 pF 2.7 V VDD 5.5 V 3 s 2.4 V VDD < 2.7 V 6 s R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 164 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.6.4 Comparator (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Input voltage range Conditions MIN. Ivref Ivcmp Output delay VDD = 3.0 V Input slew rate > 50 mV/s td MAX. Unit 0 TYP. EVDD0 - 1.4 V -0.3 EVDD0 + 0.3 V Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 s 5.0 s Comparator low-speed mode, standard mode 3.0 High-electric-potential reference voltage VTW+ Comparator high-speed mode, window mode 0.76 VDD V Low-electric-potential reference voltage VTW- Comparator high-speed mode, window mode 0.24 VDD V Operation stabilization wait time tCMP Internal reference voltage VBGR s 100 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V Note Note 3.6.5 Not usable in sub-clock operation or STOP mode. POR circuit characteristics (TA = -40 to +105 C, VSS = 0 V) Parameter Symbol Detection voltage VPOR VPDR Minimum pulse width Note 1. Note 2 Conditions Power supply rise time Power supply fall time Note 1 TPW MIN. TYP. MAX. Unit 1.45 1.51 1.57 V 1.44 1.50 1.56 V s 300 However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics. Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 165 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.6.6 LVD circuit characteristics (1) LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +105 C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Detection delay time R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 tLW MIN. TYP. MAX. Unit Power supply rise time Conditions 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.67 3.81 V Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V Power supply rise time 2.70 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V s 300 300 s Page 166 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +105 C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and VLVDD0 reset mode VLVDD1 Conditions VLVDD2 VLVDD3 3.6.7 MIN. TYP. MAX. Unit 2.64 2.75 2.86 V Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V Rising release reset voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V Rising release reset voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 Power supply voltage rising slope characteristics (TA = -40 to +105 C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol SVDD Conditions MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 3.4 AC Characteristics. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 167 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +105 C, VSS = 0V)) Parameter Data retention supply voltage Symbol Conditions MIN. TYP. MAX. Unit 5.5 V 1.44 Note VDDDR The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is Note effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.8 Flash Memory Programming Characteristics (TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. System clock frequency fCLK 2.4 V VDD 5.5 V Number of code flash rewrites Cerwr Retained for 20 years TA = 85 C Number of data flash rewrites Retained for 1 year TA = 25 C Notes 1, 2, 3 Retained for 5 years TA = 85 C 100,000 Retained for 20 years TA = 85 C 10,000 TYP. 1 MAX. Unit 32 MHz 1,000 Times Notes 1, 2, 3 1,000,000 Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self-programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 3.9 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 168 of 187 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C) RL78/G14 3.10 Timing for Switching Flash Memory Programming Modes (TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol How long from when an external reset ends until the tSUINIT Conditions MIN. POR and LVD reset must end TYP. MAX. Unit 100 ms before the external reset ends. initial communication settings are specified How long from when the TOOL0 pin is placed at the tSU POR and LVD reset must end 10 s 1 ms before the external reset ends. low level until an external reset ends How long the TOOL0 pin must be kept at the low tHD POR and LVD reset must end before the external reset ends. level after an external reset ends (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET 723 s + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 169 of 187 RL78/G14 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 170 of 187 RL78/G14 4.1 4. PACKAGE DRAWINGS 30-pin products R5F104AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP, R5F104AFASP, R5F104AGASP R5F104AADSP, R5F104ACDSP, R5F104ADDSP, R5F104AEDSP, R5F104AFDSP, R5F104AGDSP R5F104AAGSP, R5F104ACGSP, R5F104ADGSP, R5F104AEGSP, R5F104AFGSP, R5F104AGGSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M K ITEM A MILLIMETERS 9.85p0.15 B 0.45 MAX. C 0.65 (T.P.) NOTE D 0.24 0.08 0.07 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.1p0.05 F 1.3p0.1 G 1.2 H 8.1p0.2 I 6.1p0.2 J 1.0p0.2 K 0.17p0.03 L 0.5 M 0.13 N 0.10 P 3o 5o 3o T 0.25 U 0.6p0.15 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 171 of 187 RL78/G14 4.2 4. PACKAGE DRAWINGS 32-pin products R5F104BAANA, R5F104BCANA, R5F104BDANA, R5F104BEANA, R5F104BFANA, R5F104BGANA R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA, R5F104BFDNA, R5F104BGDNA R5F104BAGNA, R5F104BCGNA, R5F104BDGNA, R5F104BEGNA, R5F104BFGNA, R5F104BGGNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-4 0.06 D DETAIL OF A PART E S A A S Referance Symbol y S D2 A EXPOSED DIE PAD 1 Min Nom Max D 4.95 5.00 5.05 E 4.95 5.00 5.05 A 0.70 0.75 0.80 b 0.18 0.25 0.30 e Lp 8 0.50 0.30 0.40 0.50 x 0.05 y 0.05 9 32 Dimension in Millimeters B E2 ITEM 25 16 EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 3.45 3.50 3.55 3.45 3.50 3.55 17 24 Lp e b R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 x M S AB 2012 Renesas Electronics Corporation. All rights reserved. Page 172 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP, R5F104BFAFP, R5F104BGAFP R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP, R5F104BFDFP, R5F104BGDFP R5F104BAGFP, R5F104BCGFP, R5F104BDGFP, R5F104BEGFP, R5F104BFGFP, R5F104BGGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2 HD 2 D 17 16 24 25 detail of lead end 1 E c HE 32 8 1 L 9 e (UNIT:mm) 3 b x M A A2 ITEM D DIMENSIONS 7.000.10 E 7.000.10 HD 9.000.20 HE 9.000.20 A 1.70 MAX. A1 0.100.10 A2 y A1 1.40 b 0.370.05 c 0.145 0.055 L 0.500.20 0 to 8 e 0.80 1.Dimensions " 1" and " 2" do not include mold flash. x 0.20 2.Dimension " 3" does not include trim offset. y 0.10 NOTE R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 173 of 187 RL78/G14 4.3 4. PACKAGE DRAWINGS 36-pin products R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA, R5F104CFALA, R5F104CGALA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 32x b S AB e ZE w S A M A ZD D x 6 5 B 4 E 3 2.90 2 C INDEX MARK y1 D w S B S 1 F E D C B A E 2.90 A S y S DETAIL C DETAIL E DETAIL D R0.17p 0.05 0.70 p0.05 0.55 p0.05 R0.12 p0.05 0.75 0.55 (UNIT:mm) R0.17 p0.05 0.70 p0.05 R0.12 p0.05 0.55 p0.05 0.75 0.55 Fb (LAND PAD) F 0.34p0.05 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.55p0.05 0.70p 0.05 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 0.55 0.75 0.55p0.05 R0.275p0.05 R0.35p0.05 ITEM D DIMENSIONS E 4.00p0.10 w 0.20 4.00p0.10 e 0.50 A 0.69p0.07 b 0.24p0.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 0.70p0.05 Page 174 of 187 RL78/G14 4.4 4. PACKAGE DRAWINGS 40-pin products R5F104EAANA, R5F104ECANA, R5F104EDANA, R5F104EEANA, R5F104EFANA, R5F104EGANA, R5F104EHANA R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA, R5F104EFDNA, R5F104EGDNA, R5F104EHDNA R5F104EAGNA, R5F104ECGNA, R5F104EDGNA, R5F104EEGNA, R5F104EFGNA, R5F104EGGNA, R5F104EHGNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-4 0.09 D DETAIL OF A PART E S A A S y Referance Symbol S D2 A 1 EXPOSED DIE PAD 10 Min Nom Max D 5.95 6.00 6.05 E 5.95 6.00 6.05 A 0.70 0.75 0.80 b 0.18 0.25 0.30 e Lp 11 40 Dimension in Millimeters 0.50 0.30 0.40 0.50 x 0.05 y 0.05 B E2 ITEM 31 20 21 30 Lp EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 4.45 4.50 4.55 4.45 4.50 4.55 e b x R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 M S AB 2012 Renesas Electronics Corporation. All rights reserved. Page 175 of 187 RL78/G14 4.5 4. PACKAGE DRAWINGS 44-pin products R5F104FAAFP, R5F104FCAFP, R5F104FDAFP, R5F104FEAFP, R5F104FFAFP, R5F104FGAFP, R5F104FHAFP, R5F104FJAFP R5F104FADFP, R5F104FCDFP, R5F104FDDFP, R5F104FEDFP, R5F104FFDFP, R5F104FGDFP, R5F104FHDFP, R5F104FJDFP R5F104FAGFP, R5F104FCGFP, R5F104FDGFP, R5F104FEGFP, R5F104FFGFP, R5F104FGGFP, R5F104FHGFP, R5F104FJGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 HD D detail of lead end A3 23 22 33 34 c Q E L Lp HE L1 (UNIT:mm) 12 11 44 1 ZE e ZD b x M S A A2 S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 DIMENSIONS 10.00p0.20 E 10.00p0.20 HD 12.00p0.20 HE 12.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 A3 0.25 b S y ITEM D c L 0.37 0.08 0.07 0.145 0.055 0.045 0.50 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.80 x 0.20 y 0.10 ZD 1.00 ZE 1.00 Page 176 of 187 RL78/G14 4.6 4. PACKAGE DRAWINGS 48-pin products R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB, R5F104GFAFB, R5F104GGAFB, R5F104GHAFB, R5F104GJAFB R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB, R5F104GFDFB, R5F104GGDFB, R5F104GHDFB, R5F104GJDFB R5F104GAGFB, R5F104GCGFB, R5F104GDGFB, R5F104GEGFB, R5F104GFGFB, R5F104GGGFB, R5F104GHGFB, R5F104GJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 37 A3 24 c Q E L Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.00p0.20 E 7.00p0.20 HD 9.00p0.20 HE 9.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 A3 b A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 0.25 0.22p0.05 0.145 0.055 0.045 0.50 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 Page 177 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA, R5F104GFANA, R5F104GGANA, R5F104GHANA, R5F104GJANA R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA, R5F104GFDNA, R5F104GGDNA, R5F104GHDNA, R5F104GJDNA R5F104GAGNA, R5F104GCGNA, R5F104GDGNA, R5F104GEGNA, R5F104GFGNA, R5F104GGGNA, R5F104GHGNA, R5F104GJGNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A P48K8-50-5B4-5 0.13 D DETAIL OF E S A PART A A S y S Referance Symbol D2 A EXPOSED DIE PAD 1 12 Min Nom Max D 6.95 7.00 7.05 E 6.95 7.00 7.05 A 0.70 0.75 0.80 b 0.18 0.25 0.30 e 13 48 Dimension in Millimeters Lp B 0.50 0.30 0.40 0.50 x 0.05 y 0.05 E2 ITEM 37 24 36 25 Lp EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 5.45 5.50 5.55 5.45 5.50 5.55 e b R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 x M S AB Page 178 of 187 RL78/G14 4.7 4. PACKAGE DRAWINGS 52-pin products R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F104JFAFA, R5F104JGAFA, R5F104JHAFA, R5F104JJAFA R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA, R5F104JGDFA, R5F104JHDFA, R5F104JJDFA R5F104JCGFA, R5F104JDGFA, R5F104JEGFA, R5F104JFGFA, R5F104JGGFA, R5F104JHGFA, R5F104JJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3 HD D 2 27 39 40 detail of lead end 26 c 1 E HE 52 L 14 1 13 e (UNIT:mm) 3 b x M A A2 y NOTE ITEM D DIMENSIONS 10.000.10 E 10.000.10 HD 12.000.20 HE 12.000.20 A 1.70 MAX. A1 0.100.05 A2 A1 1.40 b 0.320.05 c 0.145 0.055 L 0.500.15 1.Dimensions " 1" and " 2" do not include mold flash. 0 to 8 2.Dimension " 3" does not include trim offset. e 0.65 x 0.13 y 0.10 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 179 of 187 RL78/G14 4.8 4. PACKAGE DRAWINGS 64-pin products R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA, R5F104LGAFA, R5F104LHAFA, R5F104LJAFA R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA, R5F104LGDFA, R5F104LHDFA, R5F104LJDFA R5F104LCGFA, R5F104LDGFA, R5F104LEGFA, R5F104LFGFA, R5F104LGGFA, R5F104LHGFA, R5F104LJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51 HD D detail of lead end 48 33 49 32 A3 c Q E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A ITEM D DIMENSIONS 12.00p0.20 E 12.00p0.20 HD 14.00p0.20 HE 14.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 A3 0.25 0.32 0.08 0.07 0.145 0.055 0.045 0.50 b A2 c L S y S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.65 x 0.13 y 0.10 ZD 1.125 ZE 1.125 Page 180 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB, R5F104LGAFB, R5F104LHAFB, R5F104LJAFB R5F104LCDFB, R5F104LDDFB, R5F104LEDFB, R5F104LFDFB, R5F104LGDFB, R5F104LHDFB, R5F104LJDFB R5F104LCGFB, R5F104LDGFB, R5F104LEGFB, R5F104LFGFB, R5F104LGGFB, R5F104LHGFB, R5F104LJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 HD D detail of lead end 48 33 49 A3 32 c Q E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S ITEM D DIMENSIONS 10.00p0.20 E 10.00p0.20 HD 12.00p0.20 HE 12.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 A3 b A A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 0.25 0.22p0.05 0.145 0.055 0.045 0.50 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 Page 181 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA, R5F104LGALA, R5F104LHALA, R5F104LJALA 64-PIN PLASTIC FLGA (5x5) 60x b x M S AB A D w S A ZD e 8 ZE 7 6 B 5 E 4 3.90 3 2 C D INDEX MARK w S B 1 H G F E D C B E A 3.90 y1 A S S y S DETAIL C DETAIL E DETAIL D R0.17o0.015 0.70o0.03 0.55o0.04 R0.125o 0.02 0.75 0.55 R0.17o0.015 0.70o0.03 R0.125o0.02 0.55o0.04 0.75 0.55 b (LAND PAD) 0.34o0.03 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.55o0.04 0.70o0.03 R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 0.55 0.75 0.55o0.04 0.70o0.03 R0.275o0.02 R0.35o0.015 (UNIT:mm) ITEM D DIMENSIONS 5.00o0.10 E 5.00o0.10 w 0.20 e A 0.50 0.69o0.07 b 0.25o0.04 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 P64FC-50-AN5 Page 182 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104LCAFP, R5F104LDAFP, R5F104LEAFP, R5F104LFAFP, R5F104LGAFP, R5F104LHAFP, R5F104LJAFP R5F104LCDFP, R5F104LDDFP, R5F104LEDFP, R5F104LFDFP, R5F104LGDFP, R5F104LHDFP, R5F104LJDFP R5F104LCGFP, R5F104LDGFP, R5F104LEGFP, R5F104LFGFP, R5F104LGGFP, R5F104LHGFP, R5F104LJGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-14x14-0.80 PLQP0064GA-A P64GC-80-GBW-1 0.7 HD D 2 48 49 33 32 detail of lead end c 1 E HE L 17 16 64 1 (UNIT:mm) e 3 b x M A A2 y NOTE 1.Dimensions " 1" and " 2" do not include mold flash. 2.Dimension " 3" does not include trim offset. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 ITEM D DIMENSIONS 14.000.10 E 14.000.10 HD 16.000.20 HE 16.000.20 A 1.70 MAX. A1 0.100.10 A2 1.40 b 0.37 c L +0.08 -0.05 +0.05 0.125 -0.02 0.500.20 0 to 8 e 0.80 x 0.20 y 0.10 Page 183 of 187 RL78/G14 4.9 4. PACKAGE DRAWINGS 80-pin products R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB R5F104MFGFB, R5F104MGGFB, R5F104MHGFB, R5F104MJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.53 HD D detail of lead end 41 60 61 A3 40 c Q E L Lp HE L1 (UNIT:mm) 21 80 1 20 ZE e ZD b x M S E 12.00p0.20 HD 14.00p0.20 HE 14.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 c L A2 S S DIMENSIONS 12.00p0.20 A3 b A y ITEM D A1 0.25 0.22p0.05 0.145 0.055 0.045 0.50 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 Page 184 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA R5F104MFGFA, R5F104MGGFA, R5F104MHGFA, R5F104MJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP80-14x14-0.65 PLQP0080JB-E P80GC-65-UBT-2 0.69 HD detail of lead end D L1 A A3 c 60 61 41 40 L Lp B E HE Referance Symbol 80 1 21 20 Dimension in Millimeters Min Nom Max D 13.80 14.00 14.20 14.20 E 13.80 14.00 HD 17.00 17.20 17.40 HE 17.00 17.20 17.40 A1 0.05 0.125 0.20 A2 1.35 1.40 1.45 bp 0.26 0.32 0.38 c 0.10 0.145 0.20 Lp 0.736 0.886 1.036 L1 1.40 1.60 1.80 Q 0n 3n 8n A ZE e ZD 1.70 A3 bp x M S AB L A A2 S e y 0.25 0.80 0.65 x S R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 0.13 y 0.10 ZD 0.825 ZE 0.825 Page 185 of 187 RL78/G14 4.10 4. PACKAGE DRAWINGS 100-pin products R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB R5F104PFGFB, R5F104PGGFB, R5F104PHGFB, R5F104PJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP100-14x14-0.50 PLQP0100KE-A P100GC-50-GBR-1 0.69 HD D detail of lead end A L1 75 76 51 50 A3 c B L E HE Lp (UNIT:mm) 26 25 100 1 ITEM D DIMENSIONS 14.00p0.20 E 14.00p0.20 HD 16.00p0.20 HE 16.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p 0.05 A3 ZE e b ZD x M S AB A 0.22 p0.05 c 0.145 0.055 0.045 0.50 L A2 Lp 0.60p0.15 L1 e 1.00p0.20 3o 5o 3o 0.50 x 0.08 y 0.08 ZD 1.00 ZE 1.00 S y R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 S A1 0.25 b Page 186 of 187 RL78/G14 4. PACKAGE DRAWINGS R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA R5F104PFGFA, R5F104PGGFA, R5F104PHGFA, R5F104PJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92 HD D detail of lead end A A3 51 50 80 81 c B E HE L Lp 100 1 L1 31 30 (UNIT:mm) ZE e ZD b x M S AB A A2 S ITEM D DIMENSIONS 20.00 0.20 E 14.00 0.20 HD 22.00 0.20 HE 16.00 0.20 A 1.60 MAX. A1 0.10 0.05 A2 1.40 0.05 A3 0.25 0.08 0.32 0.07 0.145 0.055 0.045 0.50 b c y S R01DS0053EJ0200 Rev. 2.00 Oct 25, 2013 A1 L Lp 0.60 0.15 L1 e 1.00 0.20 3 5 3 0.65 x 0.13 y 0.10 ZD 0.575 ZE 0.825 Page 187 of 187 REVISION HISTORY Rev. Date Description Page 0.01 Feb 10, 2011 -- 0.02 May 01, 2011 1 to 2 3 4 to 13 14 0.03 Jul 28, 2011 1.00 Feb 21, 2012 2.00 Oct 25, 2013 RL78/G14 Datasheet Summary First Edition issued 1.1 Features revised 1.2 Ordering Information revised 1.3 Pin Configuration (Top View) revised 1.4 Pin Identification revised 15 to 17 1.5.1 30-pin products to 1.5.3 36-pin products revised 23 to 26 1.6 Outline of Functions revised 1 1.1 Features revised 1 to 40 1. OUTLINE revised 41 to 97 2. ELECTRICAL SPECIFICATIONS added 1 3 to 8 Modification of 1.1 Features Modification of 1.2 Ordering Information 9 to 22 Modification of package type in 1.3 Pin Configuration (Top View) 34 to 43 Modification of description of subsystem clock in 1.6 Outline of Functions 34 to 43 Modification of description of timer output in 1.6 Outline of Functions 34 to 43 Modification of error of data transfer controller in 1.6 Outline of Functions 34 to 43 Modification of error of event link controller in 1.6 Outline of Functions 45, 46 Modification of description of Tables in 2.1 Absolute Maximum Ratings 47 Modification of Tables, notes, cautions, and remarks in 2.2 Oscillator Characteristics 48 Modification of error of conditions of high level input voltage in 2.3.1 Pin characteristics 49 Modification of error of conditions of low level output voltage in 2.3.1 Pin characteristics 53 to 62 Modification of Notes and Remarks in 2.3.2 Supply current characteristics 65, 66 Addition of Minimum Instruction Execution Time during Main System Clock Operation 67 to 69 Addition of AC Timing Test Points 70 to 97 Addition of LS mode and LV mode characteristics in 2.5.1 Serial array unit 98 to 101 Addition of LS mode and LV mode characteristics in 2.5.2 Serial interface IICA 102 to 105 Addition of characteristics about conversion of internal reference voltage and temperature sensor in 2.6.1 A/D converter characteristics 107 Addition of characteristic in 2.6.4 Comparator 107 Deletion of detection delay in 2.6.5 POR circuit characteristics 109 Modification of 2.6.7 Power supply voltage rising slope characteristics 110 Modification of 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics 110 Addition of characteristic in 2.8 Flash Memory Programming Characteristics 111 Addition of description in 2.10 Timing for Switching Flash Memory Programming Modes C-1 REVISION HISTORY Rev. Date 2.00 Oct 25, 2013 RL78/G14 Datasheet Description Page 112 to 169 Summary Addition of CHAPTER 3 ELECTRICAL SPECIFICATIONS 171 to 187 Modification of 4.1 30-pin products to 4.10 100-pin products SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. C-2 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. 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"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. 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