FN7642 Rev 2.00 Page 1 of 20
September 22, 2011
FN7642
Rev 2.00
September 22, 2011
ISL9230
High Power Li-Ion Charger W/I-Path Management
DATASHEET
The ISL9230 is a fully integrated high input voltage single-cell
Li-ion battery charger with power path management function.
This charger performs the CC/CV charge function required by
Li-ion batteries. The charger can withstand an input voltage up
to 26V but is disabled when the input voltage exceeds 6.6V
OVP threshold. The input current limit and charge current are
programmable with external resistors. When the battery
voltage is lower than 3.0V, the charger preconditions the
battery with 10% of the programmed charge current. When
the charge current reduces to the end-of-charge (EOC) current
level during the CV charge phase, the EOC indicator (CHG) will
toggle to a logic high to indicate the end-of-charge condition.
The ISL9230 uses separate power paths to supply the system
load and the battery. This feature allows the system to
immediately operate with a completely discharged battery.
This feature also allows the charge to terminate when the
battery is full while continuing to supply the system power
from the input source, thus minimizing unnecessary
charge/discharge cycles and prolonging the battery life.
Two indication pins (PG and CHG) allow simple interface to a
microprocessor or LEDs.
Features
• Complete Charger for Single-Cell Li-ion/Polymer Batteries
• Current Path Management Optimize for Charge and System
Currents
• Intelligent Timeout Interval Based on Actual Charge Current
• 1% Charger Output Voltage Accuracy
• Programmable Input Current Limit
• Programmable Charge Current
•NTC Thermistor Input
• Complies with USB Charger
• Charge Current Thermal Foldback for Thermal Protection
• Trickle Charge for Fully Discharged Batteries
• 26V Maximum Voltage at VIN Pin
• Power Presence and Charge Indications
• Ambient Temperature Range: -40°C to +85°C
• 16 Ld 3x3 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Mobile Phones
• Blue-Tooth Devices
•PDAs
• MP3 Players
• Stand-Alone Chargers
• Other Handheld Devices
PART DESCRIPTION
C14.7µF X5R ceramic capacitor
C21µF X5R ceramic capacitor
C3 4.7µF X5R ceramic capacitor
RIREF (Application specific)
RTIME (Application specific)
RILIM (Application specific)
R1, R2300 to 1k, 5% resistor
D1, D2LEDs for indication
ISL9230
VIN
VBAT
VOUT
IREF
ILIM CHG
TIME
TO SYS
INPUT
PG
RTIME
RIREF
R1R2
T
D1
GND MODE
C1
C2
C3
BATT
CHGEN
RILIM
FROM µP
CONT
AC/USB }
FROM
µP
}
NTC
FIGURE 1. TYPICAL APPLICATION CIRCUIT
ISL9230
FN7642 Rev 2.00 Page 2 of 20
September 22, 2011
Block Diagram
CHG
PUMP
VIN
S
R
Q
VIN
VBAT
IOUT
IBAT
CLK
DIE TEMP
125°C
VBATREF
VBAT
IBATREF
IBAT
IREF
ILIMREF
VOUT
VOUTREF
DIE TEMP
155°C
IOUT
IBAT
VIN
ILIM
TIME
AC/USB
MODE
CONT
PG
CHG
NTC
IREF
VBAT
VOUT
GND
CHGEN
ISL9230 VOUT
VBAT
HITEMP
LOTEMP
Q1
Q2
ISL9230
FN7642 Rev 2.00 Page 3 of 20
September 22, 2011
Pin Configuration
ISL9230
(16 LD QFN)
TOP VIEW
1
2
3
56
11
10
8
7
12 ILIM
GND
NTC
VIN
AC/USB
VOUT
CONT
9
IREF
4
TIME
VOUT
PG
CHG
13141516
VBAT
VBAT
CHGEN
MODE
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
1 NTC The NTC pin sources a current to develop a voltage across the battery pack NTC resistor. Placing a 10kNTC thermistor
will check if the battery’s temperature is out of the safe temperature window. If the temperature is out of the safe
operating window, the charger is suspended. For applications that do not require the use of the NTC function, connect
a 10kfixed resistor from NTC to GND to maintain a valid voltage level on the NTC pin.
2, 3 VBAT Charger output pin. Connect this pin to the battery. A 1µF or larger X5R ceramic capacitor is recommended for
decoupling and stability purposes.
4CHGEN
Battery charger enable pin. The CHGEN pin is a logic input pin to provide external charge control. An internal 670k
pull-down resistor is connected to this pin. Drive the pin HIGH to disable the charger during charging. When CHGEN is
high, VOUT is still active and the battery power remains available at VOUT. To ensure proper operation, do not leave this
pin unconnected.
5 AC/USB Selects between Adapter and USB input power. Pull high for selecting adapter power and pull low for USB power. An
internal 670k pull-down resistor is connected to this pin. To ensure proper operation, do not leave this pin
unconnected.
6 MODE In combination with the AC/USB pin, this pin selects the input current limit levels. If AC/USB pin is low, a low on the
Mode pin sets the USB current to 100mA, and a high selects the 500mA limit. If the AC/USB pin is high, a low on the
mode pin selects the ILIM programmed current and a high will put the ISL9230 into a suspend state. An internal
280k pull-down resistor is connected to this pin. To ensure proper operation, do not leave this pin unconnected.
7PG
Open-drain power good indication. The open-drain MOSFET turns on when the input voltage is above the POR threshold
but below the OVP threshold. This pin is capable of sinking 5mA (minimum) to drive a LED. The maximum voltage rating
for this pin is 6.5V and it is recommended to use VOUT as the pull-up voltage.
8 GND Connect to ground.
9CHG
Open-drain charge indication pin. This pin outputs a logic LOW when a charge cycle starts and goes Hi-Z when an
end-of-charge (EOC) condition is qualified. This pin is capable of sinking 5mA min. to drive an LED. When the charger
is disabled, the CHG is also in a Hi-Z state.
10, 11 VOUT Output connection to the system. When a valid input power is present, this pin provides a 3.4V regulated voltage for the
system during trickle charge and is maintained at VBAT + 225mV during fast charging. A 4.7µF or larger X5R ceramic
capacitor is recommended for decoupling and stability purposes.
12 ILIM Input current limit programming pin. Connect a resistor between this pin and the GND to set the input current limit
determined by Equation 1 when AC/USB = 1, MODE = 0
Where RILIM is in k
If the ILIM pin is left unconnected, all input current is disabled.
ILIM
1610
RILIM
-------------- mA 200mA ILIM 1.5A=(EQ. 1)
ISL9230
FN7642 Rev 2.00 Page 4 of 20
September 22, 2011
13 VIN Power input. The absolute maximum input voltage is 26V. A 4.7µF or larger value capacitor is recommended to be
placed very close to the input pin for decoupling purposes. Additional capacitance may be required to provide a stable
input voltage.
14 TIME Timing resistor pin. The TIME pin determines the oscillation period by connecting a timing resistor between this pin and
GND. The oscillator also provides a time reference for the charger calculated in Equation 2. Equation 3 provides the
formula for finding the Pre-conditioning time, which is 1/10 of the Fast Charge timer. Leaving the TIME pin unconnected
sets the timer to the default values of 30 minutes for pre-conditioning and 5 hours for fast charge.
Where RTIME is in k
15 CONT Active high overrides the end-of-charge (EOC) or timer termination. By pulling the continuous charge CONT pin high, the
device will continue to charge the battery when the current has fallen below IEOC or the safety timer has timed out. The
status of this pin can not be changed after POR. The CONT pin is internally pulled down to GND by a 280k resistor,
but to ensure proper operation, do not leave the CONT pin floating.
16 IREF Charge current program and monitoring pin. Connect a resistor between this pin and the GND pin to set the charge
current limit determined by Equation 4:
Where RIREF is in k. The IREF pin voltage also monitors the actual charge current during the entire charge cycle,
including the trickle, constant-current, and constant-voltage phases. When disabled, VIREF = 0V.
- EPAD Exposed pad. Connect as much copper as possible to this pad either on the component layer or other layers through
thermal vias to enhance the thermal performance.
Pin Descriptions (Continued)
PIN NUMBER SYMBOL DESCRIPTION
tFAST 8R
TIME
Min=(EQ. 2)
tPRE 0.8 RTIME
Min=(EQ. 3)
IFAST
890
RIREF
--------------- mA=(EQ. 4)
TABLE 1. INPUT CURRENT LIMIT SELECTION
AC/USB MODE DESCRIPTION
0 0 USB 100mA limit
0 1 USB 500mA limit
10R
ILIM current programming
11Suspend mode
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL9230IRZ DLBB -40 to +85 16 Ld 3x3 QFN L16.3x3E
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9230. For more information on MSL please see techbrief TB363.
ISL9230
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September 22, 2011
Absolute Maximum Ratings (Referenced to GND) Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 26V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
IVIN (Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.6A
IO Output Current (Continuous)
IVOUT (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A
IVBAT (Discharge Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A
IVBAT (Charging Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5A
Output Sink Current CHG, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . . . 41 3.0
Maximum Junction Temperature (Plastic Package) . . . .-40°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Maximum Supply Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
Operating Supply Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . 4.3V to 6.25V
Programmed Fast Charge Current . . . . . . . . . . . . . . . . .300mA to 1500mA
IVIN Input current, VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5A
IVOUT Current, VOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5A
IVBAT Current, VBAT Pin (Discharging) . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5A
IVBAT Current, BAT Pin (Charging). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5A
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . 1000V
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Typical values are tested at VIN = 5V, VBAT = 3.6V and the ambient temperature at +25°C. MIN/MAX
limits are across the operating conditions, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to
+85°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
POWER-ON RESET
Rising POR Threshold VPOR_R VBAT = 3.0V, use PG to indicate the comparator output 3.2 3.36 3.5 V
Falling POR Threshold VPOR_F 2.92 3.05 3.18 V
POR Deglitch Time tPG VIN >VPOR to PG Low 1.2 ms
VIN-BAT OFFSET VOLTAGE
Rising Threshold VOS_R VBAT = 3.6V, VIN ramps from 3.5V to 4V 50 80 130 mV
Falling Threshold VOS_F VBAT = 3.6V, VIN ramps from 4V to 3.5V 20 60 mV
VIN OVERVOLTAGE PROTECTION
Overvoltage Protection Threshold VOVP 6.25 6.6 6.9 V
OVP Threshold Hysteresis VOVP_HYS 110 mV
Input Overvoltage Blanking tOVP_BLK 50 µs
Input OVP Recovery Time tOVP-REC 1.2 ms
BATTERY DETECTION
Battery Detection Current IDET VBAT = 2.5V (Note 7) -5 -7.5 -10 mA
Detection Timer tDET 250 ms
ILIM, IREF SHORT CIRCUIT DETECTION (CHECKED DURING START-UP)
Current Source ISC VIN > VPOR and VIN > VBAT + VOS 1.4 mA
ISL9230
FN7642 Rev 2.00 Page 6 of 20
September 22, 2011
Short-Circuit Detection threshold VSC VIN > VPOR and VIN > VBAT + VOS 510 mV
SHORT CIRCUIT DETECTION
Battery Short Circuit Detection Current IBSC VBAT = 1.5V 35.5 8mA
Battery Short Circuit Threshold VBSC 1.6 1.8 2.0 V
Output Short Circuit Detection at Valid VIN VOSC1 VIN > VPOR
VIN > VBAT + VOS
0.8 0.9 1.0 V
Output Short Circuit Detection, Load
Sharing Mode (Note 7)
VOSC2 Referenced to VBAT
VIN > VPOR
VIN > VBAT + VOS
-200 -250 -300 mV
Blanking Time for VSC2 BTOSC2 250 s
Recovery Time for VSC2 RTOSC2 60 ms
OPERATING CURRENT
BAT Pin Supply Current IVBAT No supply at VIN, CHGEN = LOW 6.5 µA
VIN Pin Suspend Current IVIN Charger enabled, AC/USB = Mode = 1 200 µA
VIN Pin Supply Current IVIN Charger enabled 1.5 mA
VOLTAGE REGULATION
Output Voltage VO_REG VIN > VOUT + VDO_Q1, VBAT > 3.2V
System current + charge current = 15mA
VBAT +
0.150
VBAT +
0.225
VBAT +
0.270
V
VIN > VOUT + VDO_Q1, VBAT < 3.2V
System current + charge current = 15mA
3.3 3.4 3.5
Charger Output Voltage VB_REG Charge current = 10mA, TA = +25°C 4.185 4.20 4.215 V
Charge current = 10mA 4.16 4.20 4.23
IREF Pin Voltage VIREF VBAT = 3.8V 1.8 2.24 2.55 V
POWER PATH
Output DPPM Threshold Voltage VDPPM Output voltage threshold where charge current starts to
reduce. Referenced to regulated VOUT
-200 -100 -50 mV
Input DPM Threshold Voltage VIN-DPM Input voltage threshold where the input current starts
to reduce, AC/USB = 0, MODE = X
4.36 V
Battery Supply Enter Threshold VBSUP_ON Referenced to VBAT, VBAT = 3.6V -40 mV
Battery Supply Exit Threshold VBSUP_OFF Referenced to VBAT, VBAT = 3.6V -20 mV
DROPOUT VOLTAGE
Q1 Dropout Voltage (VIN-VOUT)
(Note 7)
VDO_Q1 VOUT = 4.3V, IIN = 1A, VBAT = 4.2V 300 475 mV
Q2 Dropout Voltage
(VBAT-VOUT)
VDO_Q2 VIN = 0V, VBAT > 3V, IOUT = 1A 40 80 mV
RECHARGE THRESHOLD
Recharge Voltage Threshold VRCH Referenced to VB_REG -215 -120 -50 mV
Recharge Deglitch Time tRCH tRCH includes tDET (CONT = 0) 300 ms
Delay Time, Input Power Loss to VOUT
LDO Turn-Off
tNO-IN VBAT = 3.6V Time is measure from VIN: 5V to 3V at 1µs
fall time
20 ms
CURRENT REGULATION (Note 6)
Input Current Limit Range ILIM_RNG AC/USB = 1, Mode = 0 200 1500 mA
Electrical Specifications Typical values are tested at VIN = 5V, VBAT = 3.6V and the ambient temperature at +25°C. MIN/MAX
limits are across the operating conditions, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL9230
FN7642 Rev 2.00 Page 7 of 20
September 22, 2011
Input Current Limit Accuracy ILIM_AC1 RILIM = 1.62k955 1000 1045 mA
ILIM_AC2 RILIM = 4.32k340 375 410 mA
ILIM_100 AC/USB = 0, Mode = 0 78 88 98 mA
ILIM_500 AC/USB = 0, Mode = 1 380 440 500 mA
Fast Charge Current Range IFAST VBAT < 4.2V, AC/USB = 1, Mode = 0 300 1500 mA
Fast Charge Current RIREF = 1.78k450 500 550 mA
RIREF = 887900 1000 1100 mA
Trickle Charge Current ITRK AC/USB, MODE not equal to (1, 1)
RIREF = 1.78kITRK88RIREF)
39 49 58 mA
End Of Charge Current IEOC_USB100 AC/USB = 0, Mode = 0, RIREF = 88713 29 46 mA
IEOC_USB500 AC/USB = 0, Mode = 1, RIREF = 88770 96 125 mA
IEOC_AC RIREF = 88776 96 116 mA
End Of Charge Deglitch Time tEOC 25 ms
PRECONDITIONING VOLTAGE THRESHOLD
Preconditioning Threshold Voltage VMIN VIN > VPOR and VIN > VBAT + VOS 2.9 3.0 3.1 V
Trickle Charge to Fast Charge Deglitch
Time
tCHG_LH 25 ms
Fast Charge to Trickle Charge Deglitch
Time
tCHG_HL 25 ms
CHARGING TIMERS (Note 7)
Fast Charge Timer tFAST RTIME = 30k180 240 300 Min
RTIME = Floating 240 300 360
Trickle Charge Timer tPRE RTIME = 30k24 Min
RTIME = Floating 24 30 36
INTERNAL TEMPERATURE MONITORING
Charger Current Thermal Foldback
Threshold
TFOLD 125 °C
Thermal Shutdown Threshold TSD TJ rising 155 °C
Thermal Shutdown Hysteresis TSD_HYS 20 °C
EXTERNAL TEMPERATURE MONITORING
Thermistor Bias Current ITVIN >VPOR and VIN > VBAT + VOS 72 75 78 A
High Temperature Threshold VTMAX VNTC falling 240 295 340 mV
High Temperature Hysteresis VTMAX_H VNTC rising after reaching VTMAX 30 mV
Low Temperature Threshold VTMIN VNTC rising 2000 2100 2200 mV
Low Temperature Hysteresis VTMIN_H VNTC falling after reaching VTMIN 300 mV
Temperature Trip Deglitch Time tT_DG Measured from NTC fault to charger disabled 50 ms
NTC Pin Disable Threshold VDIS_NTC Referenced to VIN, NTC unconnected -300 mV
LOGIC INPUT AND OUTPUTS
CHGEN, CONT, MODE, AC/USB Logic
Input High
1.4 V
Electrical Specifications Typical values are tested at VIN = 5V, VBAT = 3.6V and the ambient temperature at +25°C. MIN/MAX
limits are across the operating conditions, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL9230
FN7642 Rev 2.00 Page 8 of 20
September 22, 2011
CHGEN, CONT, MODE, AC/USB Logic
Input Low
0.4 V
CHGEN and AC/USB Pin Internal
Pull-Down Resistance
570 670 770 k
CONT and MODE Pin Internal Pull-Down
Resistance
220 280 340 k
PG, CHG
Driving Capability when LOW Pin Voltage = 0.4V 5mA
Leakage Current when HIGH Pin Voltage = 5V, VOUT = VBAT = 5V 1µA
NOTES:
6. The input current charge current can be affected by the thermal foldback function if the IC under the test setup cannot dissipate the heat.
7. Limits established by characterization and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Typical values are tested at VIN = 5V, VBAT = 3.6V and the ambient temperature at +25°C. MIN/MAX
limits are across the operating conditions, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL9230
FN7642 Rev 2.00 Page 9 of 20
September 22, 2011
Typical Characteristics VIN = 5V, VBAT = 3.6V, AC/USB = 1, MODE = 0, TA = +25°C, unless otherwise
specified.
FIGURE 2. DESCRIPTION OF CHARGING MODES AS VBAT VARIES FIGURE 3. ADAPTER PLUG-IN WITH BATTERY CONNECTED
FIGURE 4. BATTERY DETECTION - BATTERY REMOVED FIGURE 5. BATTERY DETECTION - BATTERY INSERTED/REMOVED
FIGURE 6. CHARGER ON/OFF BY CHGEN (ROUT = 10ΩFIGURE 7. CHARGER ON/OFF CHGEN (ROUT = 10, VBAT = 3.6V)
VOUT
VBAT
CHG
IBAT
2V/DIV
200mA/DIV
2V/DIV
2V/DIV
200s/DIV
END OF CHARGE OCCURS
WHEN IBAT < IEOC
FROM THE CV THRESHOLD
RECHARGE OCCURS WHEN
VBAT FALLS BELOW 100mV
END OF CHARGE OCCURS
AGAIN WHEN VBAT > 4.2V
FAST CHARGE BEGINS
WHEN VBAT > 3V
VBAT RAMPING UP CV CHARGE OCCURS
WHEN VBAT REACHES
4.2V
FROM 0V
TRICKLE CHARGE
BEGINS WHEN
VBAT > 1.8V
2V/DIV
200mA/DIV
2V/DIV
5V/DIV
VIN
IBAT
CHG
VOUT
10ms/DIV
VIN
VBAT
CHG
VOUT
200ms/DIV
BATTERY DETECTION MODE
2V/DIV
1V/DIV
1V/DIV
5V/DIV
VOUT
VBAT
CHG
IBAT
2V/DIV
2V/DIV
5V/DIV
500mA/DIV
200ms/DIV
TRICKLE CHARGE
BATTERY INSERTED
BATTERY REMOVED
BATTERY NOT PRESENT
CHGEN
IBAT
IOUT
VOUT
5V/DIV
500mA/DIV
500mA/DIV
5V/DIV
4ms/DIV
ISL9230
FN7642 Rev 2.00 Page 10 of 20
September 22, 2011
FIGURE 8. OVP FAULT VIN = 5V TO 15V, ROUT = 10ΩFIGURE 9. ENTERING AND EXITING DPPM MODE
FIGURE 10. VOUT SHORTED WITH BATTERY CONNECTED FIGURE 11. VBAT TOGGLE FROM 4.3V TO 3.8V (NO OUTPUT)
FIGURE 12. SHUTDOWN CURRENT CHGEN = 1 FIGURE 13. VIN PIN SUPPLY CURRENT CHGEN = 0
Typical Characteristics VIN = 5V, VBAT = 3.6V, AC/USB = 1, MODE = 0, TA = +25°C, unless otherwise
specified. (Continued)
VIN
VBAT
PG
VOUT
5V/DIV
5V/DIV
10ms/DIV
5V/DIV
2V/DIV
VBAT
VOUT
IOUT
IBAT
2V/DIV
500mA/DIV
20s/DIV
2V/DIV
500mA/DIV
IVIN
VBAT
VOUT
IOUT
5V/DIV
5V/DIV
2A/DIV
10A/DIV
200µs/DIV
CHG
VBAT
VOUT
IBAT
2V/DIV
5V/DIV
500mA/DIV
2V/DIV
100ms/DIV
0
100
200
300
400
500
600
0 2 4 6 8 1012141618202224
VIN (V)
SHUTDOWN CURRENT (µA)
1.0
1.1
1.2
1.3
1.4
-50 -25 0 25 50 75 100 125
TEMPERATURE (°C)
IVIN (mA)
ISL9230
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September 22, 2011
FIGURE 14. DROPOUT VOLTAGE (Q1) vs TEMPERATURE FIGURE 15. DROPOUT VOLTAGE (Q2) vs TEMPERATURE
FIGURE 16. DROPOUT VOLTAGE (Q2) vs VBAT FIGURE 17. THERMAL REGULATION OF IBAT
FIGURE 18. BATTERY VOLTAGE REGULATION vs TEMPERATURE FIGURE 19. OUTPUT VOLTAGE REGULATION vs TEMPERATURE
Typical Characteristics VIN = 5V, VBAT = 3.6V, AC/USB = 1, MODE = 0, TA = +25°C, unless otherwise
specified. (Continued)
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
ILOAD = 1A
VDO-Q1 (mV)
TEMPERATURE (°C)
0
10
20
30
40
50
60
70
80
-50-250 255075100125
TEMPERATURE (°C)
ILOAD = 1A
VIN = 0V
VBAT = 3.6V
VDO-Q2 (mV)
33
35
37
39
41
43
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
DO-Q2
(mV)
VBAT (V)
ILOAD = 1A
VIN = 0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
100 105 110 115 120 125 130 135 140 145 150
IBAT (A)
TEMPERATURE (°C)
4.15
4.17
4.19
4.21
4.23
-50 -25 0 25 50 75 100 125
TEMPERATURE (°C)
IBAT = 10mA
VBAT VOLTAGE (V)
4.39
4.40
4.41
4.42
4.43
4.44
4.45
-50 -25 0 25 50 75 100 125
IOUT = 10mA
VOUT VOLTAGE (V)
TEMPERATURE (°C)
ISL9230
FN7642 Rev 2.00 Page 12 of 20
September 22, 2011
FIGURE 20. TRICKLE CHARGE vs TEMPERATURE FIGURE 21. BATTERY VOLTAGE vs INPUT VOLTAGE
FIGURE 22. BATTERY VOLTAGE vs CHARGE CURRENT (CV MODE) FIGURE 23. OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 24. VBAT AND VOUT vs CHARGE CURRENT (CV MODE) FIGURE 25. BATTERY VOLTAGE vs CHARGE CURRENT (CC MODE)
Typical Characteristics VIN = 5V, VBAT = 3.6V, AC/USB = 1, MODE = 0, TA = +25°C, unless otherwise
specified. (Continued)
48
49
50
51
52
53
54
-50 -25 0 25 50 75 100 125
ILOAD = 1A
RIREF = 1.82kΩ
VBAT = 2V
ITRK (mA)
TEMPERATURE (°C)
4.200
4.202
4.204
4.206
4.208
4.210
4.212
4.214
4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5
VIN (V)
IBAT = 100mA
VBAT (V)
4.2050
4.2055
4.2060
4.2065
4.2070
4.2075
4.2080
4.2085
4.2090
4.2095
4.2100
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
IBAT (A)
VBAT (V)
4.410
4.415
4.420
4.425
4.430
4.435
4.440
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
IOUT (A)
VOUT (V)
V
BAT
is FLOATING
4.10
4.15
4.20
4.25
4.30
4.35
4.40
4.45
4.50
0.10.30.50.70.91.11.31.5
IBAT (A)
VBAT
VOUT
VBAT AND VOUT (V)
VOUT IS FLOATING
0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VBAT (V)
IBAT (A)
ISL9230
FN7642 Rev 2.00 Page 13 of 20
September 22, 2011
FIGURE 26. CHARGE CURRENT vs INPUT VOLTAGE FIGURE 27. INPUT VOLTAGE POR THRESHOLD vs TEMPERATURE
Typical Characteristics VIN = 5V, VBAT = 3.6V, AC/USB = 1, MODE = 0, TA = +25°C, unless otherwise
specified. (Continued)
0
0.2
0.4
0.6
0.8
1.0
1.2
3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
VIN (V)
IBAT (A)
3.20
3.25
3.30
3.35
3.40
3.45
3.50
-50 -25 0 25 50 75 100 125
TEMPERATURE (°C)
POR THRESHOLD (V)
T < BTOSC2 RTOSC2 RTOSC2
BTOSC2
BTOSC2
SHORT
REMOVED
Q2 OFF
Q2 ON
Q2 OFF
VBAT-VOUT
TIME
SHORT
OCCURED
SHORT
REMOVED
SHORT
OCCURED
= ISC X RDSON (Q2)
VOUT IS SHORTED, Q2 IS ON
BTOSC2
Q2 ON
= VBAT
(VOUT = ~ 0V)
Q2 IS OFF
= IOUT X RDSON (Q2)
IOUT = NORMAL,
Q2 IS ON
= 0V
IOUT = 0,
Q2 IS ON,
VOUT = VBAT
VOSC2
FIGURE 28. VOUT SHORT CIRCUIT CHARACTERISTIC AT SUPPLEMENTAL MODE
ISL9230
FN7642 Rev 2.00 Page 14 of 20
September 22, 2011
Theory of Operation
When a valid input voltage is applied at VIN, the ISL9230 first
regulates VOUT at 3.4V or at VBAT plus 225mV, depending on the
battery voltage. If the battery voltage is below 3.2V, the ISL9230
regulates VOUT at 3.4V. If the battery voltage is higher than 3.2V,
VOUT will be regulated at VBAT plus 225mV. The charge current is
also dependent on the battery voltage. When VBAT is less than
3.0V, the ISL9230 trickle charges the battery at a reduced
current, as specified in the "Electrical Specifications" table on
page 7. Once VBAT reaches 3.0V, the fast charge phase starts.
When the system exceeds the maximum available current, either
limited by the IC or by the input power supply, the charger FET Q2
is operated in a reverse mode, i.e. it provides battery current to
the system instead of charging.
The charger function is similar to other Li-ion battery chargers,
i.e., it charges the battery at a constant current (CC) or a constant
voltage (CV) depending on the battery terminal voltage. The
constant current IFAST is set by the external resistor RIREF.
Depending on the combination of the AC/USB and the MODE pin
status, the actual charge current may be reduced by the input
current limit. When the battery voltage reaches the final voltage
of 4.2V, the charger enters the CV mode and regulates the
battery voltage at 4.2V to fully charge the battery without the risk
of overcharging. Upon reaching an end-of-charge (EOC) current,
the CHG will turn to high impedance to indicate a charge
complete state and if CONT is low, Q2 will be turned off to
terminate charging. Figure 29 shows the typical charge profile
with the EOC recharge events when CONT is low.
The EOC current level is internally set at 10% of the fast charge
current as set by RIREF for AC adapter input and USB500 input
types. For USB100 input, the EOC current is set at 3.3% of the
fast charge current as set by RIREF. The CHG signal pulls low
when the trickle charge starts and turns to high impedance at an
EOC event.
A thermal foldback function reduces the charge current anytime
when the die temperature reaches typically +125°C. This function
guarantees safe operation when the printed-circuit board (PCB) is
not capable of dissipating the heat generated by the linear charger.
The ISL9230 can withstand an input voltage up to 26V but will be
disabled when the input voltage exceeds the OVP threshold, 6.6V
typical, to protect against unqualified or faulty AC adapters.
PG Indication
The PG pin is an open-drain output to indicate the presence of a
good supply voltage on the VIN pin. If VIN is higher than the POR
threshold and lower than the OVP threshold, an internal open-drain
FET is turned on. If VIN suddenly falls below the POR falling
threshold or rises above the OVP rising threshold, the open-drain FET
will turn off. When turned on, the PG pin should be able to sink at
least 5mA current under all operating conditions.
The PG pin can be used to drive a LED or to interface with a
microprocessor.
Power-Good Range
The power-good range is defined by the following three conditions:
1. VIN > VPOR
2. VIN - VBAT > VOS
3. VIN < VOVP
where VOS is the offset voltage between the input and charger
output. The VOVP is the overvoltage protection threshold given in
the “Electrical Specifications” table on page 5. All VPOR, VOS, and
VOVP have hysteresis.
CHG Indication
The CHG is an open-drain output. The open drain FET turns on
when the charger starts to charge and turns off when the EOC
condition is qualified. Once the EOC condition is qualified, the
CHG signal is latched in a Hi-Z state. The EOC condition is
qualified when both of the following conditions are satisfied:
1. VBAT > VRCH
2. IBAT < IEOC
After being turned off, even if the battery is being automatically
recharged later, the CHG indication will not be turned on again
until one of the following events is encountered:
1. Input power being re-cycled
2. CHGEN signal being toggled
3. The battery is removed and re-inserted
The CHG signal can be interfaced either with a microprocessor
GPIO or a LED for indication. A de-glitch delay of 25ms for both
edges is implemented to prevent nuisance triggering during
some short transient conditions.
Charge Termination, Recharge and Timeout
When an EOC condition is reached, the CHG pin changes to Hi-Z to
indicate the end-of-charge condition and the charging is terminated
if the CONT pin is in logic low. When a recharge condition is met, the
safety timer will be reset to zero and the charging re-starts.
In the event a timeout interval has elapsed before the EOC
condition is reached, a timeout fault condition is triggered. The
timeout fault condition is indicated by the CHG pin being toggled
between HI and LO every 0.5s. The timeout fault condition can be
cleared by removing and reapplying the input power to the IC.
Under the EOC, timeout and timeout fault conditions, the power
delivery to VOUT is not impacted. The battery continues to supply
current to VOUT if needed, as described in “Dynamic Power Path
Management” on page 15.
FIGURE 29. TYPICAL CHARGING CYCLE FOR CONT = L
I
CC CV
I
TIME
CHG
CHARGE
CURRENT
CHARGE
VOLTAGE
CHG INDICATION
VRCH
TRICKLE
3.0V
.42V
ITRK
FAST
EOC
ISL9230
FN7642 Rev 2.00 Page 15 of 20
September 22, 2011
The charge termination current is calculated as follows:
For AC or USB500 input:
USB100 input:
Where IFAST is the fast charge current set by RIREF.
Disabling the Charge Termination Option
By setting the CONT pin low, the charge termination option will
occur when either IBAT < IEOC or the safety timer times out. This
function can be disabled by selecting the CONT pin high but
choosing the correct charge termination function needs to be
done prior to POR. When CONT is high, the safety timers are
suspended. For EOC detection, CHG status is not affected by the
state of the CONT pin, i.e. when IBAT < IEOC, the CHG will turn to
high impedance regardless of the status of CONT.
ILIM Pin Function
The ILIM pin is provided to control the maximum current drawn
by the ISL9230 at the VIN pin to supply the system and charge
the battery. This enables the system designer to ensure that the
IC does not draw more than the source can provide.
IREF Pin Function
The IREF pin has the two functions as described in the "Pin
Descriptions" on page 4. The fast charge current can be
programmed by the RIREF over the range of 300mA to 1500mA
for AC adapter input. The second function of the IREF pin is for
monitoring the charge current by measuring the voltage at this
pin, which is proportional to the charge current.
Dynamic Power Path Management
The power path management function of the ISL9230 controls
the charge current and the system current when charging the
battery with system load. The available input current, which is
either limited by the ISL9230 or by the input power source,
whichever is smaller, is properly split into two paths, one to the
battery and the other to the system. The priority is given to the
system. When the output voltage drops to the DPPM threshold,
which is the regulated output voltage minus 100mV, the
Dynamic Power Path Management (DPPM) starts to function.
The DPPM control will first allocate the available current to
satisfy the system needs, using the remaining current to charge
the battery. If the total available current is not enough to supply
the system need, when the output voltage drops to 40mV below
the battery voltage, the DPPM control will turn on the charge
control FET, allowing the battery to supply current to the system
load. Thus, when DPPM occurs, the battery may be charged at a
current smaller than the programmed constant current.
Input DPM Mode (VIN-DPM)
VIN-DPM is a special feature that is designed for current-limited
USB ports. VIN-DPM is engaged when the ISL9230 is configured
for USB100 (AC/USB = 0, MODE = 0) or USB500 (AC/USB = 0,
MODE = 1) modes. During operation of VIN-DPM, the input
voltage is monitored and if VIN drops to the threshold of
VIN-DPM, the input current is reduced to keep the input voltage
from dropping further. Therefore, the VIN-DPM feature prevents
the USB port from crashing.
Short Circuit Detection and Battery Presence
By setting CHGEN = LO, the ISL9230 first checks to see if there is
a short-circuit on the VBAT pin. During the short circuit detection,
a current of 5.5mA is sourced from VBAT to the battery. If VBAT is
above VBSC after the test, charging current ITRK begins. During
battery detection, a current sink of a duration tDET is used to
detect if a battery has been installed or removed while power is
applied to the VIN pin. A pulsed switch sinks a 7.5mA current
from VBAT. If VBAT is above VMIN after the sink test, charging
current begins. If the voltage drops below VMIN within tDET, it
indicates the battery may have been removed or the battery
safety circuit is open. The IC will then apply ITRK for tDET to close,
if possible, the battery safety circuit. If the voltage rises above
VRCH, this indicates a missing battery condition. If the VBAT
voltage is within VMIN < VBAT < VRCH, it is determined that a
battery has been installed and charging is initiated.
Intelligent Timer
The internal timer in the ISL9230 provides a time reference for
the maximum charge time limit. The nominal clock cycle for the
reference time is set by the external resistor connected between
the TIME pin and GND and is given by Equations 2 and 3.
The nominal maximum charge time interval is calculated based on
the assumption that the programmed charge current is always
available during the entire charging cycle. However, due to the PPM
control, the current limit of the input source, or thermal foldback,
the actual charge current maybe reduced during the constant
current charge period. Under such conditions, the Intelligent Timer
control will increase the timeout interval accordingly to allow
approximately the same mAh product as the original timeout
interval at the programmed current. The Intelligent Timer is
suspended when CONT is asserted high.
Thermistor Interface
To ensure a safe charging temperature range, the ISL9230
incorporates a NTC pin to interface with the NTC thermistor in the
battery pack to monitor the battery temperature. A constant current
source is provided at this pin. The temperature range is determined
by the external negative temperature coefficient (NTC) thermistor.
The voltage thresholds and the current source value of the ISL9230
are optimized for the 103AT type industry standard thermister.
The ISL9230 uses a window comparator to set the valid
temperature window. When the NTC pin voltage is out of the
window anytime during charging, indicating either the
temperature is too hot or too cold to charge, the ISL9230 stops
charging. The CHG, however will stay low to indicate a "charging"
condition. When such an invalid temperature condition is
encountered, the safety timer will stop counting. When the
temperature returns to the set range, the charging resumes and
the timer resumes counting from where it stopped.
When the CONT is high, the temperature sensing function can be
disabled by pulling the NTC pin to a voltage level above the VDIS_NTC,
as shown on the “Electrical Specifications” table on page 7.
IEOC 0.1XIFAST
=(EQ. 5)
IEOC 0.033XIFAST
=(EQ. 6)
ISL9230
FN7642 Rev 2.00 Page 16 of 20
September 22, 2011
Thermal Foldback
The thermal foldback function starts to reduce the charge current
when the internal temperature reaches a typical value of +125°C.
When thermal foldback is encountered, the charge current will be
reduced to a value where the die temperature stops rising.
Figure 31 shows the thermal foldback concept whereas the
current signals at the summing node of the current error
amplifier CA are shown in Figure 30. IR is the reference. IT is the
temperature tracking current generated from the Temperature
Monitoring block. The IT has no impact on the charge current
until the internal temperature reaches approximately +125°C;
then IT starts to rise. In the meantime, as IT rises, ISEN will fall at
the same rate (as the sum is a constant current IR). As a result,
the charging current, which is proportional to ISEN, also
decreases, keeping the die temperature constant at +125°C.
The system output current, however, is not impacted by the thermal
foldback. Thus, when the charge current is reduced to zero, if the die
temperature still rises, the IC will shut down at ~155°C to prevent
damage to the IC.
Applications Information
Input Bypass Capacitor
The input capacitor is required to suppress the power supply
transient response during transitions. Typically, a 4.7µF capacitor
should be sufficient to suppress the power supply noise.
Due to the inductance of the power leads of the wall adapter or
USB source, the input capacitor value must be properly selected
to prevent high voltage transient during a hot-plug event. Also, for
increase reliability to high dv/dt, a 10µF or more is preferable on
the input.
VOUT and VBAT Capacitor Selection
The criteria for selecting the capacitor at the VOUT and VBAT pins is
to maintain the stability as well as to bypass any transient load
current. The recommended capacitance is a 4.7µF X5R ceramic
capacitor for VOUT and 1µF for VBAT. The actual capacitance
connected to the output is dependent on the actual application
requirement.
Layout Guidance
The ISL9230 uses a thermally-enhanced QFN package that has
an exposed thermal pad at the bottom side of the package. The
layout should connect as much copper to the pad as possible.
Typically, the component layer is more effective in dissipating
heat. The thermal impedance can be further reduced by using
other layers of copper connecting to the exposed pad through a
thermal via array. Each thermal via is recommended to have
0.3mm diameter and 1mm distance from other thermal vias.
Input Power Sources
The input power source is typically a well-regulated wall cube
with 1m length wire or a USB port. The recommended input
voltage ranges from 4.3V to 6.4V. The ISL9230 can withstand up
to 26V on the input without damaging the IC. If the input voltage
is higher than the OVP threshold, the IC is disabled.
VOUT
X3
X3
VIN
IR
TEMPERATURE
MONITORING
IT
X3 VBAT
+
-VREF
VA
+
-CA
ISEN
IREF
CONTROL
IREF
REF
Q1
Q2
FIGURE 30. CHARGE CURRENT THERMAL FOLDBACK CONTROL
TEMPERATURE
+125°C
IT
IR
ISEN
-40mA/°C
FIGURE 31. THERMAL FOLDBACK CONCEPT
ISL9230
FN7642 Rev 2.00 Page 17 of 20
September 22, 2011
State Diagram
The state diagram is shown in Figure 32. There are 15 states to
cover all the operation modes, including the Power Down, Sleep,
Standby, ILIM, IREF check, VOUT check, Idle, VBAT check, Trickle
Charge, CC/CV charge, Charge Complete, Battery Detect-1,
Battery Detect-2, Battery Detect-3, Fault and Charging and
Suspend states.
The IC flow chart starts by checking the voltage applied at VIN. If
VPOR < VIN < VBAT + VOS, the IC stays in the Sleep state. If VBAT +
VOS < VIN < VOVP, the IC pulls the PG pin low and moves into the
ILIM, IREF check state where the ILIM and IREF pins are being
checked for short circuit condition. If there is no short at either
pin, the regulator FET Q1 will regulate VOUT with 100mA current
limit. Following this, the IC moves to the VOUT check state where
VOUT is checked for short circuit condition. If VOUT is below 0.9V,
indicating a VOUT short condition, the IC will stay at the VOUT
check state. If VOUT is above 0.9V, the IC will set the input current
limit according to the setting on the AC/USB and the MODE pins.
The IC then checks the status of the CHGEN pin.
If the CHGEN is low, the IC moves to the VBAT short circuit check
state where a 5.5mA current is sourced at the VBAT pin and the
voltage is checked against the 1.8V threshold. If VBAT is above
1.8V, the IC moves to the trickle charge state where the trickle
charge timer starts, the charge current is set to ITRK and CHG is
turned on to indicate charging is in progress.
When VBAT reaches the VMIN threshold (3.0V typ), the fast charge
starts where the charge current is set by RIREF or by the IC’s input
current limit, whichever is smaller. When VBAT reaches the VBAT
regulated voltage (4.2V typ), the charger moves to constant
voltage mode where VBAT is regulated at 4.2V. If the charge
current drops to below the EOC threshold, the CHG turns off to
indicate a charge complete condition. The charge current will be
terminated if the CONT pin is at logic low status. Recharge will
occur when VBAT drops below the recharge threshold which is
120mV below the regulated VBAT voltage.
There are 3 scenarios for fast charge depending on the output
current. When the sum of the output current and the fast charge
current is smaller than the input current limit, the IC enters the
Fast Charge state with the charge current set by RIREF. When the
sum of the output current and the fast charge current are greater
than the input current limit, the IC will enter the DPPM mode,
where the charging current is reduced to a point such that the
sum of output current and the charging current equals to the
input current limit. If the output current by itself is greater than
the programmed input current limit, the IC enters the battery
supplemental mode, where the battery is discharged to the
system to aid in meeting the output demand.
The output voltage, depending on VBAT, is regulated at either
VBAT + 225mV (when VBAT > 3.2V) or regulated at 3.4V (when
VBAT < 3.2V).
During the constant voltage mode, the output voltage is
regulated at VBAT + 225mV if the DPPM event is not
encountered.
If the timeout limit is reached before reaching the Charge
Complete state, the IC enters the Charger Fault state, where PG
is LO, CHG is blinking once in 0.5S, VOUT is regulated as
described above and the charger is OFF. This state is latched until
the input power is removed and re-applied to start a new cycle.
At any time during the operation, if the die temperature reaches the
OTP threshold, the IC will enter the OTP state, where PG is LO, CHG
remains in previous state, and the charger is OFF. VOUT is
disconnected from VIN and connected to VBAT internally to maintain
system power need. When the die temperature reduces by TSD-HYS,
normal charging operation occurs and the device returns to thermal
regulation.
FN7642 Rev 2.00 Page 18 of 20
September 22, 2011
ISL9230
FIGURE 32. STATE DIAGRAM (CONT = L)
YES
/CHGEN = H?
YES
VPOR < VIN
& VIN < VBAT + VOS?
VIN > VOVP?
YES
NO
NO
ILIM OR IREF
PIN SHORTED?
YES
NO
/PG = L
PWR DOWN (A)
/PG = HI-Z
/CHG = HI-Z
Q1=OFF, Q2=ON
VIN < VPOR?
YES
NO
ILIM, IREF
CHECK (D)
START
SLEEP (B)
/PG = HI-Z
/CHG = HI-Z
Q1=OFF, Q2=ON
STANDBY (C)
/PG = HI-Z
/CHG = HI-Z
Q1=OFF, Q2=ON
TURN ON Q1 @
100mA
VOUT CHECK (E)
/CHG = HI-Z
Q1 = ON @
100mA
Q2 = ON VOUT < VOSC1?
YES
Q1 CURRENT
LIMIT SET BY AC/
USB AND MODE
Q2 = OFF
IDLE (F)
Q1 = ON @
AC/USB, MODE
Q2 = OFF
NO
YES
VBAT CHECK
(G)
/CHG = Hi-Z
Q1 = ON @
AC/USB, MODE
TURN ON IBSC
VBAT < VBSC?
NO
TURN OFF IBSC
RESET tPRE
ENABLE THERMAL LOOP
SET /CHG = L
TRICKLE (H)
/CHG = L
IBAT = ITRK
ENABLE TPRE
VBAT<VMIN?
NO
NO
YES
DISABLE ITRK
DISABLE tPRE
RESET tFAST
CC/CV CHARGE (I)
/CHG = L
(/CHG = Hi-Z DURING
RECHARGE)
IBAT = IFAST
ENABLE tFAST
VBAT
REACHES
VB_REG AND
IBAT < IEOC?
YES
NO
DISABLE IBAT
TURN OFF Q2
DISABLE tFAST
/CHG = Hi-Z
SINK IDET (7.5mA)
FOR tDET (250ms)
CHARGE
COMPLETE (J)
/CHG = HI-Z
Q1 = ON AT
AC/USB, MODE
Q2 = OFF
VBAT < VRCH
FOR tRCH?NO
SINK IDET (7.5mA)
FOR tDET (250ms) BATTERY DETECTION-1
(K)
(BATT REMOVAL
DETECTION)
VBAT > VMIN?
RESET tFAST
YES
YES
SWITCH VO_REG
TO VB_REG +
225mV (4.425V)
NO
ENABLE
ITRK
FOR tDET
BATTERY DETECTION-2(L)
(BATT REMOVAL
DETECTION)
VBAT > VRCH?
SWITCH
VO_REG
TO NORMAL
OPERATION
G
NO
YES
SINK IDET (7.5mA)
FOR tDET (250ms) BATTERY DETECTION-3(M)
(BATT REMOVAL
DETECTION)
VBAT > VMIN?
SWITCH
VO_REG
To NORMAL
OPERATION
YES G
ANY TIME AFTER (A) WHEN
VIN < VPOR_F
ANY STATE (EXCEPT (N)) AFTER
(B) WHEN VIN<VBAT + VOS _F
ANY STATE AFTER (C)
WHEN VIN > VOVP
ANY STATE AFTER (E) WHEN
VOUT < VOSC1
ANY STATE AFTER (F) WHEN
/CHGEN = H
ANY STATE AFTER (G)
WHEN
VBAT< VBSC
FAULT (N)
/CHG FLASHING AT 2Hz
Q1 = ON AT AC/USB,
MODE
Q2 = OFF
(BATTERY SUPPLEMENT MODE STILL
AVAILABLE)
CHARGING SUSPENDED (O)
Q1 = OFF, Q2 = ON
/CHG REMAINS PREVIOUS
STATE
HALT tFAST
HALT tPRE
ANYTIME WHEN
Tj > TSD
TO START WHEN /CHGEN TOGGLES
GO TO (N) IF tPRE HAS
BEEN ELAPSED
GO TO (N) IF tFAST ELAPSED
Tj > TSD
TURN OFF Q1
Q2 REMAINS ON
GO TO (O)
Tj > TSD
TURN OFF Q1
Q2 REMAINS ON
GO TO (O)
Tj < TSD – TSD_HYS
Tj < TSD -TSD_HYS
TURN ON Q1 at
AC/USB, MODE
ENABLE THERMAL
LOOP
TURN ON Q1 AT
AC/USB, MODE
ENABLE
THERMAL LOOP
IF VBAT < VMIN
NO
AFTER 20ms
AFTER 50µs
AFTER 25ms
AFTER 25ms
AFTER 50µs
AFTER 25ms
FN7642 Rev 2.00 Page 19 of 20
September 22, 2011
ISL9230
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE REVISION CHANGE
August 9, 2011 FN7642.2 On page 5: under "Recommended Operating Conditions," changed value of "Operating Supply Voltage (VIN Pin)"
from "4.3V to 6.4V" to "4.3V to 6.25V".
June 10, 2011 FN7642.1 -Replaced IBAT with IFAST for fast charge operation discussion.
-Corrected CHG state to remain in previous state when die temp reaches an over-temp condition
May 27, 2011 -Changed:
Programmed Charge Current . . . . . . . . . . . . . . . . . . . . .200mA to 1500mA
To:
Programmed Fast Charge Current . . . . . . . . . . . . . . . . . 300mA to 1500mA
-Corrected "IVIN" label in Figure 10 to "IOUT" (was a duplicate)
On page 14:
-Corrected some references of IREF to IBAT and IMIN to IEOC
-Corrected some references of VOUT to VBAT
On page 15:
-In Equations 5 and 6, changed "ICHG" to "IFAST"
May 12, 2011 FN7642.0 Initial Release
ISL9230
FN7642 Rev 2.00 Page 20 of 20
September 22, 2011
Package Outline Drawing
L16.3x3E
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/11
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(4X) 0.15
INDEX AREA
PIN 1
A
3.00
B
3.00
PIN #1
B0.10 M AC
4
6
6
+0.07
112
4
9
13 16
85
16X 0.25
16X 0.40±0.10
4X 1.50
12X 0.50
(16X 0.60)
(2.80 TYP)
(16X 0.25)
(12X 0.50)
C0 . 2 REF
0 . 05 MAX.
0 . 02 NOM.
5
0.90 ±0.10
0.08
0.10 C
C
C
- 0.05
+0.10
- 0.15
1.70
( 1.70)
INDEX AREA
SEE DETAIL “X”
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
Mouser Electronics
Authorized Distributor
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