MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
PS21564-SP INTEGRATED POWER FUNCTIONS
600V/15A low-loss 5th generation IGBT inverter bridge for
three phase DC-to-AC power conversion.
Open emitter type.
APPLICATION
AC100V~200V inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).
• Input interface : 3,5V line CMOS/TTL compatible. (High Active)
• UL Approved : Yellow Card No. E80276
Dimensions in mm
TERMINAL CODE
1 VUFS
2 (UPG)
3 VUFB
4 VP1
5 (COM)
6 UP
7 VVFS
8 (VPG)
9 VVFB
10 VP1
11 (COM)
12 VP
13 VWFS
14 (WPG)
15 VWFB
16 VP1
17 (COM)
18 WP
19 (UNG)
20 VNO
21 UN
22 VN
23 WN
24 FO
25 CFO
26 CIN
27 VNC
28 VN1
29 (WNG)
30 (VNG)
31 P
32 U
33 V
34 W
35 NU
36 NV
37 NW
C
0.8 0.5
30.5
1.778
±0.15
1.778 × 26 (=46.228)
16
17
18 13
14
15 10 987 654 321
11
12192021222324
35 3437 36 33 32 31
26 252728
29
30
0.5
0.5
15.25
(1.5)
35°
(0~5°)
1.25
2.5
1.2
17.4 17.4
(17.6)
(6.5)
4.5
(3.5)
(17.6)
(22.1)
AD
BB
9
5
HEAT SINK SIDE
HEAT SINK SIDE
Type name , Lot No.
6.7 7.62
2.54
2.54
7.62 7.62
(41)
49 (φ3.8)
(0.05) (0.05)
(1.5)(1)
0.8
0.8
(0.7)
NO SOLDER PLATING
ON BOTH LEAD SIDE
φ3.3
DETAIL D
B-B DETAIL C
(36 TERMINAL)
42
±0.15
(φ2 DEPTH 2)
φ3.3
All outer lead terminals are with Pb-free solder plating.
Note1)
3.556
(2.056)
(0.278)
(0.5)
TERMINAL
SLIT
PATTERN
(ex. PCB LAYOUT)
PCB
(R0.75)
(1)
(1.5)
DETAIL A
3.556
1.75
1.2
Note 1: In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
Note 2 : Tf measurement point
Control Terminals
FWDi Chip
Al Board
Temperature measurement
point (inside the AI board)
16mm
18mm
IGBT Chip
Power Terminals
Temperature
measurement point
(inside the AI board)
Groove
Al Board Specification :
Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm
Silicon-grease should be applied evenly with a thickness of 100~200µm
DIP-IPM
PUVWN
400
–20~+100
–40~+125
2500
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
60Hz, Sinusoidal, 1 minute,
All connected pins to heat-sink plate
VCC(PROT)
Tf
Tstg
Viso
V
V
V
V
mA
V
20
20
–0.5~VD+0.5
–0.5~VD+0.5
1
–0.5~VD+0.5
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
VD
VDB
VIN
VFO
IFO
VSC
450
500
600
15
30
22.2
–20~+125
Applied between P-NU, NV, NW
Applied between P-NU, NV, NW
Tf = 25°C
Tf = 25°C, less than 1ms
Tf = 25°C, per 1 chip
(Note 1)
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
ConditionSymbol Parameter Ratings Unit
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
V
V
V
A
A
W
°C
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
ConditionSymbol Parameter Ratings Unit
CONTROL (PROTECTION) PART
Symbol Ratings Unit
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Storage temperature
Isolation voltage
V
°C
°C
Vrms
TOTAL SYSTEM
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).
Parameter Condition
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
1.95
2.05
2.00
1.80
—
0.60
2.10
0.80
1
10
4.5
6.5
mA
V
Tj = 25°C
Tj = 125°C
IC = 15A, Tj = 25°C
IC = 15A, Tj = 125°C
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
ConditionSymbol Parameter Limits
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Rth(j-f)Q
Rth(j-f)F
Min.
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
Unit
Tj = 25°C, –IC = 15A, VIN = 0V
Condition
Symbol Parameter Limits
Min. Typ. Max.
—
—
—
0.60
—
—
—
—
—
—
Unit
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Collector-emitter saturation
voltage
FWD forward voltage
Junction to case thermal
resistance (Note 3)
VD = VDB = 15V
VIN = 5V
Switching times
VCC = 300V, VD = VDB = 15V
IC = 15A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current VCE = VCES
1.45
1.55
1.50
1.20
0.30
0.40
1.50
0.50
—
—
V
µs
µs
µs
µs
µs
°C/W
°C/W
CONTROL (PROTECTION) PART
Note 4: Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is
less than 2.0 times of the current rating.
5:Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure. The fault output pulse width tFO
depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F].
Symbol
ID
VFOH
VFOL
VSC(ref)
IIN
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Parameter Condition Limits Unit
Circuit current
Fault output voltage
Short circuit trip level
Control supply under-voltage
protection
Fault output pulse width
ON threshold voltage
OFF threshold voltage
VD = VDB = 15V
VIN = 5V
Total of VP1-VNC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VSC = 0V, FO circuit pull-up to 5V with 10kΩ
VSC = 1V, IFO = 1mA
Tf = –20~100°C, VD = 15V (Note 4)
VIN = 5V
Trip level
Reset level
Trip level
Reset level
CFO = 22nF (Note 5)
Applied between UP, VP, WP-VNC, UN, VN, WN-VNC
—
—
—
—
4.9
—
0.45
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
—
—
—
—
—
—
—
1.5
—
—
—
—
1.8
2.3
1.4
5.00
0.40
7.00
0.55
—
0.95
0.52
2.0
12.0
12.5
12.5
13.0
—
2.6
2.1
Min. Typ. Max.
mA
V
V
V
mA
V
V
V
V
ms
V
V
VD = VDB = 15V
VIN = 0V
Total of VP1-VNC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Tj ≤ 125°C
Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
Input current
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
Note 6: Measurement point of heat-sink flatness
+–
Heat-sink side
Heat-sink side
Measurement location 3mm
–
+
Mounting screw : M3
Condition
Parameter Limits
Mounting torque
Weight
Heat-sink flatness
Min.
MECHANICAL CHARACTERISTICS AND RATINGS
Typ. Max.
0.59
—
–50
Unit
—
20
—
0.98
—
100
N·m
g
µm
Recommended : 0.78 N·m
(Note 6)
Applied between P-NU, NV, NW
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, Tf ≤ 100°C
Tf ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = VDB = 15V,
P.F = 0.8, sinusoidal output
Tf ≤ 100°C, Tj ≤ 125°C (Note 7)
(Note 8)
200 ≤ VCC ≤ 350V,
13.5 ≤ VD ≤ 16.5V,
13.0 ≤ VDB ≤ 18.5V,
–20°C ≤ Tf ≤ 100°C,
N-line wiring inductance less than
10nH (Note 9)
between VNC-NU, NV, NW (including surge)
RECOMMENDED OPERATION CONDITIONS
400
16.5
18.5
1
—
20
7.5
4.8
—
—
—
—
5.0
V
V
V
V/µs
µs
kHz
Arms
µs
V
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Allowable r.m.s. current
Allowable minimum input
pulse width
VNC variation
VCC
VD
VDB
tdead
fPWM
IO
PWIN(on)
PWIN(off)
VNC
0
13.5
13.0
–1
2.0
—
—
—
0.3
0.5
2.0
2.6
–5.0
ParameterSymbol Condition Max.
Min. Typ. Unit
Recommended value
300
15.0
15.0
—
—
—
—
—
—
—
—
—
—
∆V
D
, ∆V
DB
Note 7: The allowable r.m.s. current value depends on the actual application conditions.
8:The input pulse width less than PWIN(on) might make no response.
9:IPM might not work properly or make response for the input signal with OFF pulse width less than PWIN(off).
Please refer to Fig.5.
fPWM = 5kHz
fPWM = 15kHz
Below rated current
Between rated current and
1.7 times of rated current
Between 1.7 times and
2.0 times of rated current
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
Fig. 2 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
U
OUT
V
OUT
W
OUT
V
NO
CFO
GND
Fo
W
N
V
N
U
N
V
CC
HVIC3
HVIC2
HVIC1
LVIC
CIN
NU
W
V
U
P
HO
IN
COM
V
B
V
S
V
CC
HO
IN
COM
V
B
V
S
V
CC
HO
IN
COM
V
B
V
S
V
CC
Fo
W
N
V
N
U
N
V
P
V
P
U
P
V
NC
V
N1
V
P1
V
P1
V
P1
V
WFS
V
VFS
V
UFS
V
WFB
V
VFB
V
UFB
NV
NW
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
CFO
CIN
V
NO
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
Error output Fo
Output current Ic
Control supply voltage V
D
Protection circuit state
Control input
b1
b2
b3
b4
b5
RESET
RESET
UV
Dt
UV
Dr
SET
b6
b7
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Protection circuit state
Lower-arms control
input
Error output Fo
Sense voltage of the
shunt resistor
Output current Ic
Internal IGBT gate
SC reference voltage
CR circuit time
constant DELAY
a5
a8
a4
a3
a1
a2
SC
RESET
SET
a7a6
Fig. 3 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF.
a7. Input “H” : IGBT ON.
a8. IGBT OFF in spite of input “H”.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
MCU
10kΩ
UP,VP,WP,UN,VN,WN
VNC(Logic)
Fo
DIP-IPM
5V line
Error output Fo
Output current Ic
Control supply voltage VDB
Protection circuit state
Control input
c6
c1
c2 c4
c5
c3
RESET
UVDBt
UVDBr
SETRESET
High-level (no fault output)
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Fig. 4 RECOMMENDED CPU I/O INTERFACE CIRCUIT
V
NO
NW
V
NC
NV
NU
DIP-IPM
Please make the GND wiring connection
of shunt resistor to the V
NO
, V
NC
terminal as
close as possible.
Shunt resistor
Wiring inductance should be less than 10nH.
Equivalent to the inductance of a copper pattern with
length=17mm, width=3mm, and thickness=100µm
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the
wiring impedance of the printed circuit board.
The DIP-IPM input section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using an external
filtering resistor, pay attention to the turn-on threshold voltage.
Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564-SP
TRANSFER-MOLD TYPE
INSULATED TYPE
Jul. 2005
Fig. 6 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
Note 1: To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm)
2:By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler
or transformer isolation is possible.
3:
FO output is open drain type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 10k Ω resistor.
4:
F
O
output pulse width is determined by the external capacitor between CFO and V
NC
terminals (C
FO
). (Example : C
FO
= 22 nF → t
FO
= 1.8 ms (typ.))
5:The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when
using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
6:To prevent malfunction of protection, the wiring of A, B, C should be as short as possible.
7:Please set the C5R1 time constant in the range 1.5~2µs.
8:Each capacitor should be located as nearby the pins of the DIP-IPM as possible.
9:To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approxi-
mately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended.
10
:To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals.
11
:The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.45V to max.0.52V).
12
:OR logic output level should be set up the same rating of short circuit trip level (Vsc(ref): min.0.45V to max.0.52V).
HO
HO
DIP-IPM
C3
C3
C3
C2
C2
C2
C1
C1
C1
HO
IN
IN
15V line
5V line
IN
COM
COM
COM
U
OUT
V
OUT
W
OUT
V
NO
CFO
GND
F
o
W
N
V
N
V
CC
C
A
C4(CFO)
CFO CIN VNO
NW
NV
NU
CIN
V
S
V
S
V
S
V
B
V
B
V
B
V
CC
V
CC
V
CC
Fo
WN
VN
U
N
UN
WP
VP
UP
VNC
VN1
VP1
VP1
VP1
VWFS
VVFS
VUFS
VWFB
VVFB
VUFB
M
C3
HVIC1
HVIC2
HVIC3
LVIC
CONTROLLER
W
V
U
P
Comparator External protection circuit
Too long wiring here might
cause short-circuit.
C5
R1
B
Vref
+
-
C5
R1
B
Vref
+
-
C5
N1
R1
B
Vref
+
-
Shunt resistors
If this wiring is too long, the SC
level fluctuation might be larger
and cause SC malfunction.
Long GND wiring here might
generate noise to input and cause
IGBT malfunction.
OR Logic
C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering
