W24L257
32K
×
8 CMOS STATIC RAM
Publication Release Date: October 3, 2001
- 1 - Revision A5
GENERAL DESCRIPTION
The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 × 8 bits that
operates on a wide voltage range from 3V to 5.5V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
• Low power consumption:
• Access time: 70 nS
• 3.3V/5V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 2V (min.)
• Packaged in 330 mil SOP, and standard type
one STSOP (8 mm × 13.4 mm)
PIN CONFIGURATIONS BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13 16
24
25
26
27
28
20
21
22
23
17
18
19
14 15
A8
A9
#WE
A11
#OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A13
VDD
A7
A6
A5
A12
A4
A3
A2
A1
A0
I/O2
I/O3
I/O1
V
A14
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
TSOP
15
16
28
27
26
25
24
23
22
21
20
19
18
17
A12
A7
A6
A5
A4
A8
V
A11
A9
A14
A13
#W
E
A3 A2
A1
A0
#OE A10
#CS
I/O7
I/O6
I/O5
I/O4
I/O8
VSS
I/O3
I/O2
I/O1
CORE CELL ARRAY
512 ROWS
32 X 8 COLUMNS
DATA
CNTRL
.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN. PRECHARGE CKT.
A13
A8
A1 A0
A11 A10
#CS
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
I/O8
:
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 − A14 Address Inputs
I/O1 − I/O8 Data Inputs/Outputs
#CS Chip Select Input
#WE Write Enable Input
#OE Output Enable Input
VDD Power Supply
VSS Ground
NC No Connection
W24L257
- 2 -
TRUTH TABLE
#CS #OE #WE
MODE I/O1
−
I/O8 VDD CURRENT
H X X Not Selected High Z ISB, ISB1
L H H Output Disable High Z IDD
L L H Read Data Out IDD
L X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
RATING PARAMETER 3.3V 5V UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature L/LL 0 to 70 °C
LE -20 to 85
LI -40 to 85
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD = 5V ±10%; VDD = 3.3V ±5%; VSS = 0V; TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
3.3V 5V PARAMETER SYM.
TEST CONDITIONS
MIN.
MAX. MIN.
MAX.
UNIT
Input Low Voltage VIL - -0.5
+0.6 -0.5
+0.8 V
Input High Voltage VIH - +2.0
VDD +0.5
+2.2
VDD +0.5
V
Input Leakage Current ILI VIN = VSS to VDD -1 +1 -2 +2 µA
Output Leakage Current
ILO VI/O = VSS to VDD,
#CS = VIH (Min.) or
#OE = VIH (Min.) or
#CS = VIL (Max.)
-1 +1 -2 +2 µA
Output Low Voltage VOL
IOL = +2.1 mA - 0.4 - 0.4 V
Output High Voltage VOH
IOH = -1.0 mA 2.2 - 2.4 - V
Operating Power Supply
Current IDD #CS = VIL (Max.)
and I/O = 0 mA,
Cycle = Min.
Duty = 100%
- 35
- 70
mA
W24L257
Publication Release Date: October 3, 2001
- 3 - Revision A5
Operating Characteristics, continued
3.3V 5V PARAMETER SYM.
TEST CONDITIONS
MIN.
MAX.
MIN.
MAX.
UNIT
Standby Power Supply
Current ISB #CS = VIH (min.) or
Cycle = min. Duty = 100% - 1 - 3 mA
LL/LE/LI
- 15 - 15
ISB1
#CS ≥ VDD -0.2V
L - 30 - 30 µA
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V/5V
CAPACITANCE
(VDD = 5V ±10%; VDD = 3V ±5%, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC Test Loads and Waveform
90% 90%
5 nS
10%
5 nS 10%
OUTPUT OUTPUT
3.0 V
0 V
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL 1 TTL
CLZ, OLZ, CHZ, OHZ, WHZ, OW
(For T T T T T T )
W24L257
- 4 -
AC Characteristics, continued
Read Cycle
(VDD = 5V ±10%; VDD = 3V ±5%; VSS = 0V; TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER SYMBOL 3.3V/5V UNIT
MIN. MAX.
Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time TACS - 70 nS
Output Enable to Output Valid TAOE - 35 nS
Chip Selection to Output in Low Z TCLZ* 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - nS
Chip Deselection to Output in High Z TCHZ* - 30 nS
Output Disable to Output in High Z TOHZ* - 30 nS
Output Hold from Address Change TOH 10 - nS
∗ These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYMBOL 3.3V/5V UNIT
MIN. MAX.
Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 55 - nS
Address Valid to End of Write TAW 55 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 40 - nS
Write Recovery Time #CS, #WE
TWR 0 - nS
Data Valid to End of Write TDW 35 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z TWHZ* - 25 nS
Output Disable to Output in High Z TOHZ* - 25 nS
Output Active from End of Write TOW 5 - nS
∗ These parameters are sampled but not 100% tested
W24L257
Publication Release Date: October 3, 2001
- 5 - Revision A5
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
TRC
T
AA
TOH TOH
DOUT
Read Cycle 2
(Chip Select Controlled)
#CS1
DOUT TCLZ
TACS CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
TRC
#CS
TAA
#OE
TAOE
TOLZ
TOH
TACS
DOUT CLZ
TCHZ
TTOHZ
W24L257
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
#OE
TWC
TWR
#WE
DOUT
DIN
TWP
TAS
TOHZ (1, 4)
TDW TDH
TAW
#CS TCW
Write Cycle 2
(#OE = VIL Fixed)
TCW TWR
Address
TWC
#CS
#WE
DOUT
DIN
TAS
TDH
TWP
TWHZ
DW
T
(2) (3)
TOW
TOH
AW
T
(1, 4)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
W24L257
Publication Release Date: October 3, 2001
- 7 - Revision A5
DATA RETENTION CHARACTERISTICS
(TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER SYM.
TEST CONDITIONS MIN.
TYP.
MAX.
UNIT
VDD for Data Retention VDR #CS ≥ VDD -0.2V 2.0 - - V
LL/LE/LI
- - 15 µA
Data Retention Current IDDDR
#CS ≥ VDD -0.2V,
VDD = 3V L - - 30 µA
Chip Deselect to Data
Retention Time TCDR See data retention waveform
0 - - nS
Operation Recovery Time TR TRC*
- - nS
* Read Cycle Time
DATA RETENTION WAVEFORM
TCDR
-0.2V
DDV
VDD
#CS
TR
#CS
VDR 2V
=
>
=
>
0.9 DDV0.9 DD
V
W24L257
- 8 -
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
OPERATING
VOLTAGE
(V)
OPERATING
TEMPERATURE
(
°
C)
STANDBY
CURRENT MAX.
(
µ
A)
PACKAGE
W24L257S70L 70 3.3V/5V 0 to 70 30 330 mil SOP
W24L257S70LL 70 3.3V/5V 0 to 70 15 330 mil SOP
W24L257S70LE 70 3.3V/5V -20 to 85 15 330 mil SOP
W24L257S70LI 70 3.3V/5V -40 to 85 15 330 mil SOP
W24L257Q70L 70 3.3V/5V 0 to 70 30 Small TSOP
W24L257Q70LL 70 3.3V/5V 0 to 70 15 Small TSOP
W24L257Q70LE
70 3.3V/5V -20 to 85 15 Small TSOP
W24L257Q70LI 70 3.3V/5V -40 to 85 15 Small TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W24L257
Publication Release Date: October 3, 2001
- 9 - Revision A5
BONDING PAD DIAGRAM
23
X
Y
A14
A12
A7
A6
A5
A3
822
A2 A10
OEB
A11
A9
A8
WEB
VDDVDD
7
A4
A13
1
2
3
4
529 2425
26
27
630 28
11 12 13 15 16 17 18
A0 I/O0 I/O1 I/O2 VSS VSS I/O4 I/O5 I/O6
19
9
A1
10 20
CSB
14 21
I/O7I/O3
AC5394
PAD NO.
X Y
1 -232.25 1445.22
2 -351.70 1445.22
3 -471.15 1445.22
4 -590.60 1445.22
5 -710.05 1445.22
6 -829.50 1445.22
7 -992.79 1362.24
8 -992.79 -1306.11
9 -857.86 -1452.79
10 -738.41 -1452.79
11 -594.84 -1414.13
12 -451.06 -1414.13
13 -310.67 -1414.13
14 -171.78 -1405.28
15 24.45 -1405.28
16 151.80 -1414.13
17 298.07 -1414.13
18 443.28 -1414.13
19 588.20 -1414.13
20 732.84 -1414.13
21 871.11 -1452.79
22 992.75 -1312.15
23 992.75 1373.67
24 810.09 1445.22
25 690.64 1445.22
26 571.19 1445.22
27 451.74 1445.22
28 332.29 1445.22
29 120.25 1444.65
30 -93.23 1444.65
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
W24L257
- 10 -
PACKAGE DIMENSIONS
28-pin SOP
2
1
A
28 15
14
1
e
S
EH
b
Seating Plane
AA
yL
L
e
c
See Detail F
D
E
E
1
1
e
Detail F
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and determined at the mold parting line.
.
0.250.20
0.0100.008
Notes:
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in Inches Dimension in mm
A
b
c
D
e
HE
L
y
A
A
LE
1
2
E
0.014 0.36
0.112 2.85
0.004
0.093
0.014
0.098
0.016
0.103
0.020
2.36
0.36
0.10
2.49
0.41
2.62
0.51
0.059
0.004
010
0.713
0.067
0.733
0.075 1.50
18.11
1.70
18.62
1.91
0.477
0.4650.453 12.1211.8111.51
10
0
0.10
8.53
8.41
8.28
0.3360.331
0.326
0.71 0.91 1.12
0.028 0.036 0.044
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
1.12 1.27 1.420.044 0.050 0.056
S1.19
0.047
θ
28-pin Standard Type One TSOP
A
A
A
2
1
L
L1
Y
c
E
H
D
D
b
e
Controlling dimension: Millimeters
Min.
Dimension In Inches
Nom. Max. Min. Nom. Max.
Symbol
1.20
0.05 0.15
1.05
1.00
0.95
0.17
0.10
11.70
7.90
13.20
0.50
0.00
0
0.20 0.27
0.15 0.21
11.80 11.90
8.00 8.10
13.40 13.60
0.55
0.60 0.70
0.25
0.10
3 5
0.047
0.006
0.041
0.040
0.035
0.007 0.008 0.011
0.004 0.006 0.008
0.461 0.465 0.469
0.311 0.315 0.319
0.520 0.528 0.536
0.022
0.020 0.024 0.028
0.010
0.000 0.004
035
0.002
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
θ
Dimension In mm
θ
1
W24L257
Publication Release Date: October 3, 2001
- 11 - Revision A5
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 May 2000 - Initial Issued
A2 Nov. 2000 1, 2, 3, 4, 7 Add in 5V specification
1, 9 Modify package as 330 mil SOP and standard type
one TSOP (8 mm × 13.4 mm)
2, 3, 7, 8 Add in LE, LI specification
A3 Dec. 2000 2, 4, 5 Modify the 3.3V ±10%, to 3.3V ±5%
A4 Jun. 2001 8 Correct Ordering Information SOP description
8 Correct Standby Current
A5 Oct. 3, 2001
4 Correct Write Recover Time (TWR) parameter
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798