D a ta S h ee t , V 2 . 1, Au g . 2 0 0 8 XE164 16-Bit Single-Chip Real Time Signal Controller M i c r o c o n t r o l l e rs Edition 2008-08 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S h ee t , V 2 . 1, Au g . 2 0 0 8 XE164 16-Bit Single-Chip Real Time Signal Controller M i c r o c o n t r o l l e rs XE164x XE166 Family Derivatives XE164 Revision History: V2.1, 2008-08 Previous Version(s): V2.0, 2008-03, Preliminary V0.1, 2007-09, Preliminary Page Subjects (major changes since last revision) several Maximum frequency changed to 80 MHz 8 Specification of 6 ADC0 channels corrected 14f Missing ADC0 channels added 28 Voltage domain for XTAL1/XTAL2 corrected to M 68 Coupling factors corrected 73, 75 Improved leakage parameters 74, 76 Pin leakage formula corrected 81 Improved ADC error values 94f Improved definition of external clock parameters 107 JTAG clock speed corrected We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V2.1, 2008-08 XE164x XE166 Family Derivatives 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 75 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 104 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5 5.1 5.2 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Data Sheet 3 31 32 35 36 38 44 45 48 50 54 56 57 59 61 61 62 64 V2.1, 2008-08 16-Bit Single-Chip Real Time Signal Controller XE166 Family 1 XE164 Summary of Features For a quick overview and easy reference, the features of the XE164 are summarized here. * * * * * * High-performance CPU with five-stage pipeline - 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution) - One-cycle 32-bit addition and subtraction with 40-bit result - One-cycle multiplication (16 x 16 bit) - Background division (32 / 16 bit) in 21 cycles - One-cycle multiply-and-accumulate (MAC) instructions - Enhanced Boolean bit manipulation facilities - Zero-cycle jump execution - Additional instructions to support HLL and operating systems - Register-based design with multiple variable register banks - Fast context switching support with two additional local register banks - 16 Mbytes total linear address space for code and data - 1024 Bytes on-chip special function register area (C166 Family compatible) Interrupt system with 16 priority levels for up to 83 sources - Selectable external inputs for interrupt generation and wake-up - Fastest sample-rate 12.5 ns Eight-channel interrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space Clock generation from internal or external clock sources, using on-chip PLL or prescaler On-chip memory modules - 1 Kbyte on-chip stand-by RAM (SBRAM) - 2 Kbytes on-chip dual-port RAM (DPRAM) - Up to 16 Kbytes on-chip data SRAM (DSRAM) - Up to 64 Kbytes on-chip program/data SRAM (PSRAM) - Up to 768 Kbytes on-chip program memory (Flash memory) On-Chip Peripheral Modules - Two Synchronizable A/D Converters with up to 16 channels, 10-bit resolution, conversion time below 1 s, optional data preprocessing (data reduction, range check) - 16-channel general purpose capture/compare unit (CAPCOM2) - Up to three capture/compare units for flexible PWM signal generation (CCU6x) - Multi-functional general purpose timer unit with 5 timers Data Sheet 4 V2.1, 2008-08 XE164x XE166 Family Derivatives Summary of Features * * * * * * * * - Up to 6 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface - On-chip MultiCAN interface (Rev. 2.0B active) with up to 128 message objects (Full CAN/Basic CAN) on up to 4 CAN nodes and gateway functionality - On-chip real time clock Up to 12 Mbytes external address space for code and data - Programmable external bus characteristics for different address ranges - Multiplexed or demultiplexed external address/data buses - Selectable address bus width - 16-bit or 8-bit data bus width - Four programmable chip-select signals Single power supply from 3.0 V to 5.5 V Programmable watchdog timer and oscillator watchdog Up to 75 general purpose I/O lines On-chip bootstrap loaders Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards On-chip debug support via JTAG interface 100-pin Green LQFP package, 0.5 mm (19.7 mil) pitch Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. This ordering code identifies: * * the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. For ordering codes for the XE164 please contact your sales representative or local distributor. This document describes several derivatives of the XE164 group. Table 1 lists these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. For simplicity the term XE164 is used for all derivatives throughout this document. Data Sheet 5 V2.1, 2008-08 XE164x XE166 Family Derivatives Summary of Features Table 1 XE164 Derivative Synopsis Derivative1) Temp. Range Program Memory2) PSRAM3) CCU6 ADC4) Interfaces4) Mod. Chan. SAF-XE164F96FxxL -40 C to 85 C 768 Kbytes 64 Kbytes Flash 0, 1, 2 11 + 5 4 CAN Nodes, 6 Serial Chan. SAF-XE164F72F66L -40 C to 85 C 576 Kbytes 32 Kbytes Flash 0, 1, 2 11 + 5 4 CAN Nodes, 6 Serial Chan. SAF-XE164F48F66L -40 C to 85 C 384 Kbytes 16 Kbytes Flash 0, 1, 2 11 + 5 4 CAN Nodes, 6 Serial Chan. SAF-XE164F24F66L -40 C to 85 C 192 Kbytes 10 Kbytes Flash 0, 1, 2 11 + 5 4 CAN Nodes, 6 Serial Chan. SAF-XE164G96F66L -40 C to 85 C 768 Kbytes 64 Kbytes Flash 0, 1 6+5 2 CAN Nodes, 4 Serial Chan. SAF-XE164G72F66L -40 C to 85 C 576 Kbytes 32 Kbytes Flash 0, 1 6+5 2 CAN Nodes, 4 Serial Chan. SAF-XE164G48F66L -40 C to 85 C 384 Kbytes 16 Kbytes Flash 0, 1 6+5 2 CAN Nodes, 4 Serial Chan. SAF-XE164G24F66L -40 C to 85 C 192 Kbytes 10 Kbytes Flash 0, 1 6+5 2 CAN Nodes, 4 Serial Chan. SAF-XE164H96F66L -40 C to 85 C 768 Kbytes 64 Kbytes Flash 0, 1, 2 11 + 5 No CAN Node, 6 Serial Chan. SAF-XE164H72F66L -40 C to 85 C 576 Kbytes 32 Kbytes Flash 0, 1, 2 11 + 5 No CAN Node, 6 Serial Chan. SAF-XE164H48F66L -40 C to 85 C 384 Kbytes 16 Kbytes Flash 0, 1, 2 11 + 5 No CAN Node, 6 Serial Chan. SAF-XE164H24F66L -40 C to 85 C 192 Kbytes 10 Kbytes Flash 0, 1, 2 11 + 5 No CAN Node, 6 Serial Chan. SAF-XE164K96F66L -40 C to 85 C 768 Kbytes 64 Kbytes Flash 0, 1 6+5 No CAN Node, 4 Serial Chan. SAF-XE164K72F66L -40 C to 85 C 576 Kbytes 32 Kbytes Flash 0, 1 6+5 No CAN Node, 4 Serial Chan. SAF-XE164K48F66L -40 C to 85 C 384 Kbytes 16 Kbytes Flash 0, 1 6+5 No CAN Node, 4 Serial Chan. SAF-XE164K24F66L -40 C to 85 C 192 Kbytes 10 Kbytes Flash 0, 1 6+5 No CAN Node, 4 Serial Chan. 1) This Data Sheet is valid for devices starting with and including design step AC. Data Sheet 6 V2.1, 2008-08 XE164x XE166 Family Derivatives Summary of Features 2) Specific inormation about the on-chip Flash memory in Table 2. 3) All derivatives additionally provide 1 Kbyte SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM (12 Kbytes for devices with 192 Kbytes of Flash). 4) Specific information about the available channels in Table 3. Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). Data Sheet 7 V2.1, 2008-08 XE164x XE166 Family Derivatives Summary of Features The XE164 types are offered with several Flash memory sizes. Table 2 describes the location of the available memory areas for each Flash memory size. Table 2 Flash Memory Allocation Total Flash Size Flash Area A1) Flash Area B Flash Area C 768 Kbytes C0'0000H ... C0'EFFFH C1'0000H ... CB'FFFFH n.a. 576 Kbytes C0'0000H ... C0'EFFFH C1'0000H ... C8'FFFFH n.a. 384 Kbytes C0'0000H ... C0'EFFFH C1'0000H ... C5'FFFFH n.a. 192 Kbytes C0'0000H ... C0'EFFFH C1'0000H ... C1'FFFFH C4'0000H ... C4'FFFFH 1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0'F000H to C0'FFFFH). The XE164 types are offered with different interface options. Table 3 lists the available channels for each option. Table 3 Interface Channel Association Total Number Available Channels 11 ADC0 channels CH0, CH2 ... CH5, CH8 ... CH11, CH13, CH15 6 ADC0 channels CH0, CH2, CH3, CH4, CH5, CH8 5 ADC1 channels CH0, CH2, CH4, CH5, CH6 4 CAN nodes CAN0, CAN1, CAN2, CAN3 2 CAN nodes CAN0, CAN1 6 serial channels U0C0, U0C1, U1C0, U1C1, U2C0, U2C1 4 serial channels U0C0, U0C1, U1C0, U1C1 Data Sheet 8 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information 2 General Device Information The XE164 series of real time signal controllers is a part of the Infineon XE166 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize clock generation via PLL and internal or external clock sources. Onchip memory modules include program Flash, program RAM, and data RAM. VAREFVAGND TRef VDDI VDDP VSS (1) (1) (4) (9) (4) Port 0 8 bit XTAL1 XTAL2 Port 1 8 bit ESR0 ESR1 Port 2 13 bit Port 4 4 bit Port 10 16 bit Port 6 3 bit Port 15 5 bit Port 7 5 bit Port 5 11 bit TRST JTAG Debug 4 bit 2 bit TESTM PORST via Port Pins MC_XX_LOGSYMB100 Figure 1 Data Sheet Logic Symbol 9 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information 2.1 Pin Configuration and Definition 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDDPB ESR0 ESR1 PORST XTAL1 XTAL2 P1.7 P1.6 P1.5 P10.15 P1.4 P10.14 VDDI1 P1.3 P10.13 P10.12 P1.2 P10.11 P10.10 P1.1 P10.9 P10.8 P1.0 VDDPB VS S The pins of the XE164 are described in detail in Table 4, which includes all alternate functions. For further explanations please refer to the footnotes at the end of the table. Figure 2 summarizes all pins, showing their locations on the four sides of the package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP-100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDPB P0.7 P10.7 P10.6 P0.6 P10.5 P10.4 P0.5 P10.3 P2.10 TRef VDDI1 P0.4 P10.2 P0.3 P10.1 P10.0 P0.2 P2.9 P2.8 P0.1 P2.7 P0.0 VDDPB VSS VSS VDDPB P5.4 P5.5 P5.8 P5.9 P5.10 P5.11 P5.13 P5.15 P2.12 P2.11 VDDI1 P2.0 P2.1 P2.2 P4.0 P2.3 P4.1 P2.4 P2.5 P4.2 P2.6 P4.3 VDDPB 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS VDDPB TESTM P7.2 TRST P7.0 P7.3 P7.1 P7.4 VDDIM P6.0 P6.1 P6.2 VDDPA P15.0 P15.2 P15.4 P15.5 P15.6 VAREF VAGND P5.0 P5.2 P5.3 VDDPB MC_XX_PIN100 Figure 2 Data Sheet Pin Configuration (top view) 10 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Notes to Pin Definitions 1. Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to 1x00B, output O1 is selected by 1x01B, etc. Output signal OH is controlled by hardware. 2. Type: Indicates the pad type used (St=standard pad, Sp=special pad, DP=double pad, In=input pad, PS=power supply) and its power supply domain (A, B, M, 1). Table 4 Pin Definitions and Functions Pin Symbol Ctrl. Type Function 3 TESTM I In/B 4 P7.2 O0 / I St/B Bit 2 of Port 7, General Purpose Input/Output EMUX0 O1 St/B External Analog MUX Control Output 0 (ADC1) CCU62_ CCPOS0A I St/B CCU62 Position Input 0 TDI_C I St/B JTAG Test Data Input 5 TRST I In/B Test-System Reset Input For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XE164's debug system. In this case, pin TRST must be driven low once to reset the debug system. An internal pulldown device will hold this pin low when nothing is driving it. 6 P7.0 O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output T3OUT O1 St/B GPT1 Timer T3 Toggle Latch Output T6OUT O2 St/B GPT2 Timer T6 Toggle Latch Output TDO_A OH St/B JTAG Test Data Output ESR2_1 I St/B ESR2 Trigger Input 1 Data Sheet Testmode Enable Enables factory test modes, must be held HIGH for normal operation (connect to VDDPB). An internal pullup device will hold this pin high when nothing is driving it. 11 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 7 P7.3 O0 / I St/B Bit 3 of Port 7, General Purpose Input/Output EMUX1 O1 St/B External Analog MUX Control Output 1 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C0_DOUT O3 St/B USIC0 Channel 0 Shift Data Output CCU62_ CCPOS1A I St/B CCU62 Position Input 1 TMS_C I St/B JTAG Test Mode Selection Input U0C1_DX0F I St/B USIC0 Channel 1 Shift Data Input P7.1 O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output EXTCLK O1 St/B Programmable Clock Signal Output CCU62_ CTRAPA I St/B CCU62 Emergency Trap Input BRKIN_C I St/B OCDS Break Signal Input P7.4 O0 / I St/B Bit 4 of Port 7, General Purpose Input/Output EMUX2 O1 St/B External Analog MUX Control Output 2 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C1_ SCLKOUT O3 St/B USIC0 Channel 1 Shift Clock Output CCU62_ CCPOS2A I St/B CCU62 Position Input 2 TCK_C I St/B JTAG Clock Input U0C0_DX0D I St/B USIC0 Channel 0 Shift Data Input U0C1_DX1E I St/B USIC0 Channel 1 Shift Clock Input P6.0 O0 / I St/A Bit 0 of Port 6, General Purpose Input/Output EMUX0 O1 St/A External Analog MUX Control Output 0 (ADC0) BRKOUT O3 St/A OCDS Break Signal Output ADCx_ REQGTyC I St/A External Request Gate Input for ADC0/1 U1C1_DX0E I St/A USIC1 Channel 1 Shift Data Input 8 9 11 Data Sheet Type Function 12 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 12 P6.1 O0 / I St/A Bit 1 of Port 6, General Purpose Input/Output EMUX1 O1 St/A External Analog MUX Control Output 1 (ADC0) T3OUT O2 St/A GPT1 Timer T3 Toggle Latch Output U1C1_DOUT O3 St/A USIC1 Channel 1 Shift Data Output ADCx_ REQTRyC I St/A External Request Trigger Input for ADC0/1 P6.2 O0 / I St/A Bit 2 of Port 6, General Purpose Input/Output EMUX2 O1 St/A External Analog MUX Control Output 2 (ADC0) T6OUT O2 St/A GPT2 Timer T6 Toggle Latch Output U1C1_ SCLKOUT O3 St/A USIC1 Channel 1 Shift Clock Output U1C1_DX1C I St/A USIC1 Channel 1 Shift Clock Input P15.0 I In/A Bit 0 of Port 15, General Purpose Input ADC1_CH0 I In/A Analog Input Channel 0 for ADC1 P15.2 I In/A Bit 2 of Port 15, General Purpose Input ADC1_CH2 I In/A Analog Input Channel 2 for ADC1 T5IN I In/A GPT2 Timer T5 Count/Gate Input P15.4 I In/A Bit 4 of Port 15, General Purpose Input ADC1_CH4 I In/A Analog Input Channel 4 for ADC1 T6IN I In/A GPT2 Timer T6 Count/Gate Input P15.5 I In/A Bit 5 of Port 15, General Purpose Input ADC1_CH5 I In/A Analog Input Channel 5 for ADC1 T6EUD I In/A GPT2 Timer T6 External Up/Down Control Input P15.6 I In/A Bit 6 of Port 15, General Purpose Input ADC1_CH6 I In/A Analog Input Channel 6 for ADC1 - PS/A Reference Voltage for A/D Converters ADC0/1 21 VAREF VAGND - PS/A Reference Ground for A/D Converters ADC0/1 22 P5.0 I In/A Bit 0 of Port 5, General Purpose Input ADC0_CH0 I In/A Analog Input Channel 0 for ADC0 13 15 16 17 18 19 20 Data Sheet Type Function 13 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. Type Function 23 P5.2 I In/A Bit 2 of Port 5, General Purpose Input ADC0_CH2 I In/A Analog Input Channel 2 for ADC0 TDI_A I In/A JTAG Test Data Input P5.3 I In/A Bit 3 of Port 5, General Purpose Input ADC0_CH3 I In/A Analog Input Channel 3 for ADC0 T3IN I In/A GPT1 Timer T3 Count/Gate Input P5.4 I In/A Bit 4 of Port 5, General Purpose Input ADC0_CH4 I In/A Analog Input Channel 4 for ADC0 T3EUD I In/A GPT1 Timer T3 External Up/Down Control Input TMS_A I In/A JTAG Test Mode Selection Input P5.5 I In/A Bit 5 of Port 5, General Purpose Input ADC0_CH5 I In/A Analog Input Channel 5 for ADC0 CCU60_ T12HRB I In/A External Run Control Input for T12 of CCU60 P5.8 I In/A Bit 8 of Port 5, General Purpose Input ADC0_CH8 I In/A Analog Input Channel 8 for ADC0 CCU6x_ T12HRC I In/A External Run Control Input for T12 of CCU6x CCU6x_ T13HRC I In/A External Run Control Input for T13 of CCU6x P5.9 I In/A Bit 9 of Port 5, General Purpose Input ADC0_CH9 I In/A Analog Input Channel 9 for ADC0 CC2_T7IN I In/A CAPCOM2 Timer T7 Count Input P5.10 I In/A Bit 10 of Port 5, General Purpose Input ADC0_CH10 I In/A Analog Input Channel 10 for ADC0 BRKIN_A I In/A OCDS Break Signal Input P5.11 I In/A Bit 11 of Port 5, General Purpose Input ADC0_CH11 I In/A Analog Input Channel 11 for ADC0 P5.13 I In/A Bit 13 of Port 5, General Purpose Input ADC0_CH13 I In/A Analog Input Channel 13 for ADC0 EX0BINB I In/A External Interrupt Trigger Input 24 28 29 30 31 32 33 34 Data Sheet 14 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. Type Function 35 P5.15 I In/A Bit 15 of Port 5, General Purpose Input ADC0_CH15 I In/A Analog Input Channel 15 for ADC0 P2.12 O0 / I St/B Bit 12 of Port 2, General Purpose Input/Output U0C0_ SELO4 O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_ SELO3 O2 St/B USIC0 Channel 1 Select/Control 3 Output READY I St/B External Bus Interface READY Input P2.11 O0 / I St/B Bit 11 of Port 2, General Purpose Input/Output U0C0_ SELO2 O1 St/B USIC0 Channel 0 Select/Control 2 Output U0C1_ SELO2 O2 St/B USIC0 Channel 1 Select/Control 2 Output BHE/WRH OH St/B External Bus Interf. High-Byte Control Output Can operate either as Byte High Enable (BHE) or as Write strobe for High Byte (WRH). P2.0 O0 / I St/B Bit 0 of Port 2, General Purpose Input/Output AD13 OH / I St/B External Bus Interface Address/Data Line 13 RxDC0C I CAN Node 0 Receive Data Input P2.1 O0 / I St/B Bit 1 of Port 2, General Purpose Input/Output TxDC0 O1 CAN Node 0 Transmit Data Output AD14 OH / I St/B External Bus Interface Address/Data Line 14 ESR1_5 I St/B ESR1 Trigger Input 5 EX0AINA I St/B External Interrupt Trigger Input P2.2 O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output TxDC1 O1 CAN Node 1 Transmit Data Output AD15 OH / I St/B External Bus Interface Address/Data Line 15 ESR2_5 I St/B ESR2 Trigger Input 5 EX1AINA I St/B External Interrupt Trigger Input P4.0 O0 / I St/B Bit 0 of Port 4, General Purpose Input/Output CC2_24 O3 / I St/B CAPCOM2 CC24IO Capture Inp./ Compare Out. CS0 OH External Bus Interface Chip Select 0 Output 36 37 39 40 41 42 Data Sheet St/B St/B St/B St/B 15 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 43 P2.3 O0 / I St/B U0C0_DOUT O1 44 45 46 Type Function St/B Bit 3 of Port 2, General Purpose Input/Output USIC0 Channel 0 Shift Data Output CC2_16 O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out. A16 OH St/B External Bus Interface Address Line 16 ESR2_0 I St/B ESR2 Trigger Input 0 U0C0_DX0E I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0D I St/B USIC0 Channel 1 Shift Data Input RxDC0A I St/B CAN Node 0 Receive Data Input P4.1 O0 / I St/B Bit 1 of Port 4, General Purpose Input/Output TxDC2 O2 CAN Node 2 Transmit Data Output CC2_25 O3 / I St/B CAPCOM2 CC25IO Capture Inp./ Compare Out. CS1 OH External Bus Interface Chip Select 1 Output P2.4 O0 / I St/B St/B St/B Bit 4 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_17 O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out. A17 OH St/B External Bus Interface Address Line 17 ESR1_0 I St/B ESR1 Trigger Input 0 U0C0_DX0F I St/B USIC0 Channel 0 Shift Data Input RxDC1A I St/B CAN Node 1 Receive Data Input P2.5 O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output U0C0_ SCLKOUT O1 St/B USIC0 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_18 O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out. A18 OH St/B External Bus Interface Address Line 18 U0C0_DX1D I St/B USIC0 Channel 0 Shift Clock Input Data Sheet 16 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 47 P4.2 O0 / I St/B Bit 2 of Port 4, General Purpose Input/Output TxDC2 O2 CAN Node 2 Transmit Data Output CC2_26 O3 / I St/B CAPCOM2 CC26IO Capture Inp./ Compare Out. CS2 OH St/B External Bus Interface Chip Select 2 Output T2IN I St/B GPT1 Timer T2 Count/Gate Input P2.6 O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output U0C0_ SELO0 O1 St/B USIC0 Channel 0 Select/Control 0 Output U0C1_ SELO1 O2 St/B USIC0 Channel 1 Select/Control 1 Output CC2_19 O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out. A19 OH St/B External Bus Interface Address Line 19 U0C0_DX2D I St/B USIC0 Channel 0 Shift Control Input RxDC0D I St/B CAN Node 0 Receive Data Input P4.3 O0 / I St/B Bit 3 of Port 4, General Purpose Input/Output CC2_27 O3 / I St/B CAPCOM2 CC27IO Capture Inp./ Compare Out. CS3 OH St/B External Bus Interface Chip Select 3 Output RxDC2A I St/B CAN Node 2 Receive Data Input T2EUD I St/B GPT1 Timer T2 External Up/Down Control Input P0.0 O0 / I St/B 48 49 53 U1C0_DOUT O1 Type Function St/B St/B Bit 0 of Port 0, General Purpose Input/Output USIC1 Channel 0 Shift Data Output CCU61_ CC60 O3 / I St/B CCU61 Channel 0 Input/Output A0 OH St/B External Bus Interface Address Line 0 U1C0_DX0A I St/B USIC1 Channel 0 Shift Data Input Data Sheet 17 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 54 P2.7 O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output U0C1_ SELO0 O1 St/B USIC0 Channel 1 Select/Control 0 Output U0C0_ SELO1 O2 St/B USIC0 Channel 0 Select/Control 1 Output CC2_20 O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out. A20 OH St/B External Bus Interface Address Line 20 U0C1_DX2C I St/B USIC0 Channel 1 Shift Control Input RxDC1C I St/B CAN Node 1 Receive Data Input P0.1 O0 / I St/B 55 56 57 Type Function Bit 1 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_ CC61 O3 / I St/B CCU61 Channel 1 Input/Output A1 OH St/B External Bus Interface Address Line 1 U1C0_DX0B I St/B USIC1 Channel 0 Shift Data Input U1C0_DX1A I St/B USIC1 Channel 0 Shift Clock Input P2.8 O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output U0C1_ SCLKOUT O1 DP/B USIC0 Channel 1 Shift Clock Output EXTCLK O2 DP/B Programmable Clock Signal Output CC2_21 O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out. A21 OH DP/B External Bus Interface Address Line 21 U0C1_DX1D I DP/B USIC0 Channel 1 Shift Clock Input P2.9 O0 / I St/B 1) Bit 9 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CC2_22 O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out. A22 OH St/B External Bus Interface Address Line 22 CLKIN1 I St/B Clock Signal Input TCK_A I St/B JTAG Clock Input Data Sheet 18 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 58 P0.2 O0 / I St/B Bit 2 of Port 0, General Purpose Input/Output U1C0_ SCLKOUT O1 St/B USIC1 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_ CC62 O3 / I St/B CCU61 Channel 2 Input/Output A2 OH St/B External Bus Interface Address Line 2 U1C0_DX1B I St/B USIC1 Channel 0 Shift Clock Input P10.0 O0 / I St/B 59 U0C1_DOUT O1 60 Type Function St/B Bit 0 of Port 10, General Purpose Input/Output USIC0 Channel 1 Shift Data Output CCU60_ CC60 O2 / I St/B CCU60 Channel 0 Input/Output AD0 OH / I St/B External Bus Interface Address/Data Line 0 ESR1_2 I St/B ESR1 Trigger Input 2 U0C0_DX0A I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0A I St/B USIC0 Channel 1 Shift Data Input P10.1 O0 / I St/B U0C0_DOUT O1 St/B Bit 1 of Port 10, General Purpose Input/Output USIC0 Channel 0 Shift Data Output CCU60_ CC61 O2 / I St/B CCU60 Channel 1 Input/Output AD1 OH / I St/B External Bus Interface Address/Data Line 1 U0C0_DX0B I St/B USIC0 Channel 0 Shift Data Input U0C0_DX1A I St/B USIC0 Channel 0 Shift Clock Input Data Sheet 19 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 61 P0.3 O0 / I St/B Bit 3 of Port 0, General Purpose Input/Output U1C0_ SELO0 O1 St/B USIC1 Channel 0 Select/Control 0 Output U1C1_ SELO1 O2 St/B USIC1 Channel 1 Select/Control 1 Output CCU61_ COUT60 O3 St/B CCU61 Channel 0 Output A3 OH St/B External Bus Interface Address Line 3 U1C0_DX2A I St/B USIC1 Channel 0 Shift Control Input RxDC0B I St/B CAN Node 0 Receive Data Input P10.2 O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output U0C0_ SCLKOUT O1 USIC0 Channel 0 Shift Clock Output CCU60_ CC62 O2 / I St/B CCU60 Channel 2 Input/Output AD2 OH / I St/B External Bus Interface Address/Data Line 2 U0C0_DX1B I USIC0 Channel 0 Shift Clock Input P0.4 O0 / I St/B Bit 4 of Port 0, General Purpose Input/Output U1C1_ SELO0 O1 St/B USIC1 Channel 1 Select/Control 0 Output U1C0_ SELO1 O2 St/B USIC1 Channel 0 Select/Control 1 Output CCU61_ COUT61 O3 St/B CCU61 Channel 1 Output A4 OH St/B External Bus Interface Address Line 4 U1C1_DX2A I St/B USIC1 Channel 1 Shift Control Input RxDC1B I St/B CAN Node 1 Receive Data Input TRef IO Sp/1 62 63 65 Data Sheet Type Function St/B St/B Control Pin for Core Voltage Generation 2) 20 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 66 P2.10 O0 / I St/B 67 68 69 Type Function Bit 10 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output U0C0_ SELO3 O2 St/B USIC0 Channel 0 Select/Control 3 Output CC2_23 O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out. A23 OH St/B External Bus Interface Address Line 23 U0C1_DX0E I St/B USIC0 Channel 1 Shift Data Input CAPIN I St/B GPT2 Register CAPREL Capture Input P10.3 O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output CCU60_ COUT60 O2 CCU60 Channel 0 Output AD3 OH / I St/B External Bus Interface Address/Data Line 3 U0C0_DX2A I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2A I St/B USIC0 Channel 1 Shift Control Input P0.5 O0 / I St/B Bit 5 of Port 0, General Purpose Input/Output U1C1_ SCLKOUT O1 St/B USIC1 Channel 1 Shift Clock Output U1C0_ SELO2 O2 St/B USIC1 Channel 0 Select/Control 2 Output CCU61_ COUT62 O3 St/B CCU61 Channel 2 Output A5 OH St/B External Bus Interface Address Line 5 U1C1_DX1A I St/B USIC1 Channel 1 Shift Clock Input U1C0_DX1C I St/B USIC1 Channel 0 Shift Clock Input P10.4 O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output U0C0_ SELO3 O1 St/B USIC0 Channel 0 Select/Control 3 Output CCU60_ COUT61 O2 St/B CCU60 Channel 1 Output AD4 OH / I St/B External Bus Interface Address/Data Line 4 U0C0_DX2B I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2B I St/B USIC0 Channel 1 Shift Control Input Data Sheet St/B 21 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 70 P10.5 O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output U0C1_ SCLKOUT O1 St/B USIC0 Channel 1 Shift Clock Output CCU60_ COUT62 O2 St/B CCU60 Channel 2 Output AD5 OH / I St/B External Bus Interface Address/Data Line 5 U0C1_DX1B I USIC0 Channel 1 Shift Clock Input P0.6 O0 / I St/B 71 72 Type Function St/B Bit 6 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CCU61_ COUT63 O3 St/B CCU61 Channel 3 Output A6 OH St/B External Bus Interface Address Line 6 U1C1_DX0A I St/B USIC1 Channel 1 Shift Data Input CCU61_ CTRAPA I St/B CCU61 Emergency Trap Input U1C1_DX1B I St/B USIC1 Channel 1 Shift Clock Input P10.6 O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output U1C0_ SELO0 O3 St/B USIC1 Channel 0 Select/Control 0 Output AD6 OH / I St/B External Bus Interface Address/Data Line 6 U0C0_DX0C I St/B USIC0 Channel 0 Shift Data Input U1C0_DX2D I St/B USIC1 Channel 0 Shift Control Input CCU60_ CTRAPA I St/B CCU60 Emergency Trap Input Data Sheet 22 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 73 P10.7 O0 / I St/B 74 78 Type Function Bit 7 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CCU60_ COUT63 O2 St/B CCU60 Channel 3 Output AD7 OH / I St/B External Bus Interface Address/Data Line 7 U0C1_DX0B I St/B USIC0 Channel 1 Shift Data Input CCU60_ CCPOS0A I St/B CCU60 Position Input 0 P0.7 O0 / I St/B Bit 7 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output U1C0_ SELO3 O2 St/B USIC1 Channel 0 Select/Control 3 Output A7 OH St/B External Bus Interface Address Line 7 U1C1_DX0B I St/B USIC1 Channel 1 Shift Data Input CCU61_ CTRAPB I St/B CCU61 Emergency Trap Input P1.0 O0 / I St/B Bit 0 of Port 1, General Purpose Input/Output U1C0_ MCLKOUT O1 St/B USIC1 Channel 0 Master Clock Output U1C0_ SELO4 O2 St/B USIC1 Channel 0 Select/Control 4 Output A8 OH St/B External Bus Interface Address Line 8 ESR1_3 I St/B ESR1 Trigger Input 3 EX0BINA I St/B External Interrupt Trigger Input CCU62_ CTRAPB I St/B CCU62 Emergency Trap Input Data Sheet 23 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 79 P10.8 O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output U0C0_ MCLKOUT O1 St/B USIC0 Channel 0 Master Clock Output U0C1_ SELO0 O2 St/B USIC0 Channel 1 Select/Control 0 Output AD8 OH / I St/B External Bus Interface Address/Data Line 8 CCU60_ CCPOS1A I St/B CCU60 Position Input 1 U0C0_DX1C I St/B USIC0 Channel 0 Shift Clock Input BRKIN_B I St/B OCDS Break Signal Input P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output U0C0_ SELO4 O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_ MCLKOUT O2 St/B USIC0 Channel 1 Master Clock Output AD9 OH / I St/B External Bus Interface Address/Data Line 9 CCU60_ CCPOS2A I St/B CCU60 Position Input 2 TCK_B I St/B JTAG Clock Input P1.1 O0 / I St/B Bit 1 of Port 1, General Purpose Input/Output CCU62_ COUT62 O1 St/B CCU62 Channel 2 Output U1C0_ SELO5 O2 St/B USIC1 Channel 0 Select/Control 5 Output U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output A9 OH St/B External Bus Interface Address Line 9 ESR2_3 I St/B ESR2 Trigger Input 3 EX1BINA I St/B External Interrupt Trigger Input U2C1_DX0C I St/B USIC2 Channel 1 Shift Data Input 80 81 Data Sheet Type Function 24 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 82 P10.10 O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output U0C0_ SELO0 O1 St/B USIC0 Channel 0 Select/Control 0 Output CCU60_ COUT63 O2 St/B CCU60 Channel 3 Output AD10 OH / I St/B External Bus Interface Address/Data Line 10 U0C0_DX2C I St/B USIC0 Channel 0 Shift Control Input TDI_B I St/B JTAG Test Data Input U0C1_DX1A I St/B USIC0 Channel 1 Shift Clock Input P10.11 O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output U1C0_ SCLKOUT O1 St/B USIC1 Channel 0 Shift Clock Output BRKOUT O2 St/B OCDS Break Signal Output AD11 OH / I St/B External Bus Interface Address/Data Line 11 U1C0_DX1D I St/B USIC1 Channel 0 Shift Clock Input RxDC2B I St/B CAN Node 2 Receive Data Input TMS_B I St/B JTAG Test Mode Selection Input P1.2 O0 / I St/B Bit 2 of Port 1, General Purpose Input/Output CCU62_ CC62 O1 / I St/B CCU62 Channel 2 Input/Output U1C0_ SELO6 O2 St/B USIC1 Channel 0 Select/Control 6 Output U2C1_ SCLKOUT O3 St/B USIC2 Channel 1 Shift Clock Output A10 OH St/B External Bus Interface Address Line 10 ESR1_4 I St/B ESR1 Trigger Input 4 CCU61_ T12HRB I St/B External Run Control Input for T12 of CCU61 EX2AINA I St/B External Interrupt Trigger Input U2C1_DX0D I St/B USIC2 Channel 1 Shift Data Input U2C1_DX1C I St/B USIC2 Channel 1 Shift Clock Input 83 84 Data Sheet Type Function 25 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 85 P10.12 O0 / I St/B 86 87 Type Function Bit 12 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC2 O2 St/B CAN Node 2 Transmit Data Output TDO_B O3 St/B JTAG Test Data Output AD12 OH / I St/B External Bus Interface Address/Data Line 12 U1C0_DX0C I St/B USIC1 Channel 0 Shift Data Input U1C0_DX1E I St/B USIC1 Channel 0 Shift Clock Input P10.13 O0 / I St/B Bit 13 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC3 O2 St/B CAN Node 3 Transmit Data Output U1C0_ SELO3 O3 St/B USIC1 Channel 0 Select/Control 3 Output WR/WRL OH St/B External Bus Interface Write Strobe Output Active for each external write access, when WR, active for ext. writes to the low byte, when WRL. U1C0_DX0D I St/B USIC1 Channel 0 Shift Data Input P1.3 O0 / I St/B Bit 3 of Port 1, General Purpose Input/Output CCU62_ COUT63 O1 St/B CCU62 Channel 3 Output U1C0_ SELO7 O2 St/B USIC1 Channel 0 Select/Control 7 Output U2C0_ SELO4 O3 St/B USIC2 Channel 0 Select/Control 4 Output A11 OH St/B External Bus Interface Address Line 11 ESR2_4 I St/B ESR2 Trigger Input 4 CCU62_ T12HRB I St/B External Run Control Input for T12 of CCU62 EX3AINA I St/B External Interrupt Trigger Input Data Sheet 26 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 89 P10.14 O0 / I St/B Bit 14 of Port 10, General Purpose Input/Output U1C0_ SELO1 O1 St/B USIC1 Channel 0 Select/Control 1 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output RD OH St/B External Bus Interface Read Strobe Output ESR2_2 I St/B ESR2 Trigger Input 2 U0C1_DX0C I St/B USIC0 Channel 1 Shift Data Input RxDC3C I St/B CAN Node 3 Receive Data Input P1.4 O0 / I St/B Bit 4 of Port 1, General Purpose Input/Output CCU62_ COUT61 O1 St/B CCU62 Channel 1 Output U1C1_ SELO4 O2 St/B USIC1 Channel 1 Select/Control 4 Output U2C0_ SELO5 O3 St/B USIC2 Channel 0 Select/Control 5 Output A12 OH St/B External Bus Interface Address Line 12 U2C0_DX2B I St/B USIC2 Channel 0 Shift Control Input P10.15 O0 / I St/B Bit 15 of Port 10, General Purpose Input/Output U1C0_ SELO2 O1 St/B USIC1 Channel 0 Select/Control 2 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U1C0_DOUT O3 St/B USIC1 Channel 0 Shift Data Output ALE OH St/B External Bus Interf. Addr. Latch Enable Output U0C1_DX1C I St/B USIC0 Channel 1 Shift Clock Input P1.5 O0 / I St/B Bit 5 of Port 1, General Purpose Input/Output CCU62_ COUT60 O1 St/B CCU62 Channel 0 Output U1C1_ SELO3 O2 St/B USIC1 Channel 1 Select/Control 3 Output BRKOUT O3 St/B OCDS Break Signal Output A13 OH St/B External Bus Interface Address Line 13 U2C0_DX0C I St/B USIC2 Channel 0 Shift Data Input 90 91 92 Data Sheet Type Function 27 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 93 P1.6 O0 / I St/B Bit 6 of Port 1, General Purpose Input/Output CCU62_ CC61 O1 / I St/B CCU62 Channel 1 Input/Output U1C1_ SELO2 O2 St/B USIC1 Channel 1 Select/Control 2 Output U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output A14 OH St/B External Bus Interface Address Line 14 U2C0_DX0D I St/B USIC2 Channel 0 Shift Data Input P1.7 O0 / I St/B Bit 7 of Port 1, General Purpose Input/Output CCU62_ CC60 O1 / I St/B CCU62 Channel 0 Input/Output U1C1_ MCLKOUT O2 St/B USIC1 Channel 1 Master Clock Output U2C0_ SCLKOUT O3 St/B USIC2 Channel 0 Shift Clock Output A15 OH St/B External Bus Interface Address Line 15 U2C0_DX1C I St/B USIC2 Channel 0 Shift Clock Input 95 XTAL2 O Sp/1 Crystal Oscillator Amplifier Output 96 XTAL1 I Sp/1 Crystal Oscillator Amplifier Input To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Voltages on XTAL1 must comply to the core supply voltage VDDI1. 97 PORST I In/B Power On Reset Input A low level at this pin resets the XE164 completely. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 120 ns. An internal pullup device will hold this pin high when nothing is driving it. 94 Data Sheet Type Function 28 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. 98 ESR1 O0 / I St/B External Service Request 1 U1C0_DX0F I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2C I St/B USIC1 Channel 0 Shift Control Input U1C1_DX0C I St/B USIC1 Channel 1 Shift Data Input U1C1_DX2B I St/B USIC1 Channel 1 Shift Control Input U2C1_DX2C I St/B USIC2 Channel 1 Shift Control Input EX0AINB I St/B External Interrupt Trigger Input ESR0 O0 / I St/B 99 Type Function External Service Request 0 Note: After power-up, ESR0 operates as opendrain bidirectional reset with a weak pull-up. U1C0_DX0E I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2B I St/B USIC1 Channel 0 Shift Control Input 10 VDDIM - PS/M Digital Core Supply Voltage for Domain M Decouple with a ceramic capacitor, see Table 12 for details. 38, 64, 88 VDDI1 - PS/1 Digital Core Supply Voltage for Domain 1 Decouple with a ceramic capacitor, see Table 12 for details. All VDDI1 pins must be connected to each other. 14 VDDPA - PS/A Digital Pad Supply Voltage for Domain A Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. Note: The A/D_Converters and ports P5, P6, and P15 are fed from supply voltage VDDPA. Data Sheet 29 V2.1, 2008-08 XE164x XE166 Family Derivatives General Device Information Table 4 Pin Definitions and Functions (cont'd) Pin Symbol Ctrl. Type Function 2, 25, 27, 50, 52, 75, 77, 100 VDDPB - PS/B Digital Pad Supply Voltage for Domain B Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. 1, 26, 51, 76 VSS Note: The on-chip voltage regulators and all ports except P5, P6, and P15 are fed from supply voltage VDDPB. - PS/-- Digital Ground All VSS pins must be connected to the ground-line or ground-plane. Note: Also the exposed pad is connected to VSS. The respective board area must be connected to ground (if soldered) or left free. 1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This configuration is referred to as reference clock output signal CLKOUT. 2) Pin TRef was used to control the core voltage generation in step AA. For that step, pin TRef must be connected to VDDPB. This connection is no more required from step AB on. For the current step, pin TRef is logically not connected. Future derivatives will feature an additional general purpose IO pin at this position. Data Sheet 30 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3 Functional Description The architecture of the XE164 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, control, and communication. The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data SRAM) and the generic peripherals are connected to the CPU by separate high-speed buses. Another bus, the LXBus, connects additional on-chip resources and external resources (see Figure 3). This bus structure enhances overall system performance by enabling the concurrent operation of several subsystems of the XE164. PSRAM 10/16/32/64 Kbytes DPRAM 2 Kbytes DSRAM 12/16 Kbytes OCDS Debug Support DMU The block diagram gives an overview of the on-chip components and the advanced internal bus structure of the XE164. EBC LXBus Control External Bus Control CPU PMU C166SV2 - Core Program Flash 2 0/64/256 Kbytes WDT XTAL System Functions Clock, Reset, Stand-By RAM Interrupt & PEC RTC LXBus Program Flash 1 64/128/256 Kbytes IMB Program Flash 0 128/256 Kbytes ADC1 ADC0 8-Bit/ 8-Bit/ 10-Bit 10-Bit 8 Ch. 8 Ch. GPT T2 T3 T4 ... CCU60 CC2 CCU62 T7 T12 T12 T8 T13 T13 Peri pheral Data B us Interrupt Bus USIC2 USIC1 USIC0 Multi 2 Ch., 2 Ch., 2 Ch., CAN 64 x 64 x 64 x Buffer Buffer Buffer RS232, RS232, RS232, LIN, LIN, LIN, 4 ch. SPI, SPI, SPI, IIC, IIS IIC, IIS IIC, IIS T5 T6 BRGen P15 Port 5 5 11 P10 P7 P6 16 5 3 P4 4 P2 13 P1 8 P0 8 MC_XE164X_BLOCKDIAGRAM Figure 3 Data Sheet Block Diagram 31 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.1 Memory Subsystem and Organization The memory space of the XE164 is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same linear address space. Table 5 XE164 Memory Map Address Area Start Loc. End Loc. Area Size1) Notes IMB register space FF'FF00H FF'FFFFH 256 Bytes - Reserved (Access trap) F0'0000H FF'FEFFH <1 Mbyte Minus IMB registers Reserved for EPSRAM E9'0000H EF'FFFFH 448 Kbytes Mirrors EPSRAM Emulated PSRAM E8'0000H E8'FFFFH 64 Kbytes Flash timing Reserved for PSRAM E1'0000H E7'FFFFH 448 Kbytes Mirrors PSRAM Program SRAM E0'0000H E0'FFFFH 64 Kbytes Maximum speed Reserved for pr. mem. CC'0000H DF'FFFFH <1.25 Mbytes - Program Flash 2 C8'0000H CB'FFFFH 256 Kbytes Program Flash 1 C4'0000H C7'FFFFH 256 Kbytes - - C0'0000H C3'FFFFH 256 Kbytes 2) 40'0000H BF'FFFFH 8 Mbytes - 20'5800H 3F'FFFFH < 2 Mbytes Minus USIC/CAN USIC registers 20'4000H 20'57FFH 6 Kbytes Accessed via EBC MultiCAN registers 20'0000H 20'3FFFH 16 Kbytes Accessed via EBC External memory area 01'0000H 1F'FFFFH < 2 Mbytes Minus segment 0 SFR area 00'FE00H 00'FFFFH 0.5 Kbyte - Dual-Port RAM 00'F600H 00'FDFFH 2 Kbytes - Reserved for DPRAM 00'F200H 00'F5FFH 1 Kbyte - ESFR area 00'F000H 00'F1FFH 0.5 Kbyte - XSFR area 00'E000H 00'EFFFH 4 Kbytes - Data SRAM 00'A000H 00'DFFFH 16 Kbytes - Reserved for DSRAM 00'8000H 00'9FFFH 8 Kbytes - External memory area 00'0000H 00'7FFFH 32 Kbytes - Program Flash 0 External memory area Available Ext. IO area 3) 1) The areas marked with "<" are slightly smaller than indicated. See column "Notes". 2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0'F000H to C0'FFFFH). 3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external peripherals properly. Data Sheet 32 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the register spaces (ESFR/SFR) additionally are directly bit addressable. The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment. The Program Management Unit (PMU) handles all code fetches and, therefore, controls access to the program memories such as Flash memory and PSRAM. The Data Management Unit (DMU) handles all data transfers and, therefore, controls access to the DSRAM and the on-chip peripherals. Both units (PMU and DMU) are connected to the high-speed system bus so that they can exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, code is fetched from external memory, or data is read from or written to external resources. These include peripherals on the LXBus such as USIC or MultiCAN. The system bus allows concurrent two-way communication for maximum transfer performance. Up to 64 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the PSRAM with programmable size can be write-protected. Note: The actual size of the PSRAM depends on the chosen derivative (see Table 1). Up to 16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data (12 Kbytes for devices with 192 Kbytes of Flash). The DSRAM is accessed via a separate interface and is optimized for data access. 2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined variables, for the system stack, and for general purpose register banks. A register bank can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, ..., RL7, RH7) General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable. 1 Kbyte of on-chip Stand-By SRAM (SBRAM) provides storage for system-relevant user data that must be preserved while the major part of the device is powered down. The SBRAM is accessed via a specific interface and is powered in domain M. Data Sheet 33 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XE166 Family. In order to to ensure upward compatibility they should either not be accessed or written with zeros. In order to meet the requirements of designs where more memory is required than is available on chip, up to 12 Mbytes (approximately, see Table 5) of external RAM and/or ROM can be connected to the microcontroller. The External Bus Interface also provides access to external peripherals. Up to 768 Kbytes of on-chip Flash memory store code, constant data, and control data. The on-chip Flash memory consists of up to three modules with a maximum capacity of 256 Kbytes each. Each module is organized in 4-Kbyte sectors. The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used internally to store operation control parameters and protection information. Note: The actual size of the Flash memory depends on the chosen derivative (see Table 1). Each sector can be separately write protected1), erased and programmed (in blocks of 128 Bytes). The complete Flash area can be read-protected. A user-defined password sequence temporarily unlocks protected areas. The Flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing. Dynamic error correction provides extremely high read data security for all read access operations. Access to different Flash modules can be executed in parallel. For Flash parameters, please see Section 4.5. 1) To save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing. Data Sheet 34 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.2 External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of the external bus that allows access to integrated peripherals and modules in the same way as to external components. The EBC can be programmed either to Single Chip Mode, when no external memory is required, or to an external bus mode with the following selections1): * * * Address Bus Width with a range of 0 ... 24-bit Data Bus Width 8-bit or 16-bit Bus Operation Multiplexed or Demultiplexed The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed bus modes, the lower addresses are output separately on Port 0 and Port 1. The number of active segment address lines is selectable, restricting the external address space to 8 Mbytes ... 64 Kbytes. This is required when interface lines shall be assigned to Port 2. Up to four external CS signals (three windows plus default) can be generated and output on Port 4 in order to save external glue logic. External modules can be directly connected to the common address/data bus and their individual select lines. Important timing characteristics of the external bus interface are programmable (with registers TCONCSx/FCONCSx) to allow the user to adapt it to a wide range of different types of memories and external peripherals. Access to very slow memories or modules with varying access times is supported by a special `Ready' function. The active level of the control input signal is selectable. In addition, up to four independent address windows may be defined (using registers ADDRSELx) to control access to resources with different bus characteristics. These address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. All accesses to locations not covered by these four address windows are controlled by TCONCS0/FCONCS0. The currently active window can generate a chip select signal. The external bus timing is based on the rising edge of the reference clock output CLKOUT. The external bus protocol is compatible with that of the standard C166 Family. 1) Bus modes are switched dynamically if several address windows with different mode settings are used. Data Sheet 35 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.3 Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instructionfetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel shifter. PSRAM Flash/ROM PMU CPU Prefetch Unit Branch Unit FIFO CSP IP VECSEG CPUCON1 CPUCON2 Return Stack IDX0 IDX1 QX0 QX1 QR0 QR1 +/- +/- Multiply Unit MRW +/- MCW MSW MAH MAL 2-Stage Prefetch Pipeline TFR Injection/ Exception Handler 5-Stage Pipeline IFU DPP0 DPP1 DPP2 DPP3 DPRAM IPIP SPSEG SP STKOV STKUN ADU Division Unit Bit-Mask-Gen. Multiply Unit Barrel-Shifter MDC R15 R15 R14 R15 R14 R14 R15 R14 GPRs GPRs GPRs GPRs R1 R1 R0 R0R1 R0 R1 R0 RF PSW +/- MDH MDL ZEROS ONES MAC CP Buffer ALU WB DSRAM EBC Peripherals DMU mca04917_x.vsd Figure 4 Data Sheet CPU Block Diagram 36 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description With this hardware most XE164 instructions can be executed in a single machine cycle of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits are shifted. Also, multiplication and most MAC instructions execute in one cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast; for example, a 32-/16-bit division is started within 4 cycles while the remaining cycles are executed in the background. Another pipeline optimization, the branch target prediction, eliminates the execution time of branch instructions if the prediction was correct. The CPU has a register context consisting of up to three register banks with 16 wordwide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank accessed by the CPU at any time. The number of these register bank copies is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 32 Kwords is provided for storage of temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow. The high performance of the CPU hardware implementation can be best utilized by the programmer with the highly efficient XE164 instruction set. This includes the following instruction classes: * * * * * * * * * * * * * Standard Arithmetic Instructions DSP-Oriented Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Data Sheet 37 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.4 Interrupt System With a minimum interrupt response time of 7/111) CPU clocks (in the case of internal program execution), the XE164 can react quickly to the occurrence of non-deterministic events. The architecture of the XE164 supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). Where in a standard interrupt service the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source pointer, the destination pointer, or both. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are particularly well suited to supporting the transmission or reception of blocks of data. The XE164 has eight PEC channels, each whith fast interrupt-driven data transfer capabilities. Each of the possible interrupt nodes has a separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Each node can be programmed by its related register to one of sixteen interrupt priority levels. Once accepted by the CPU, an interrupt service can only be interrupted by a higher-priority service request. For standard interrupt processing, each possible interrupt node has a dedicated vector location. Fast external interrupt inputs can service external interrupts with high-precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge, or both edges). Software interrupts are supported by the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 6 shows all of the possible XE164 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes) may be used to generate software-controlled interrupt requests by setting the respective interrupt request bit (xIR). 1) Depending if the jump cache is used or not. Data Sheet 38 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 6 XE164 Interrupt Nodes Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number CAPCOM Register 16, or ERU Request 0 CC2_CC16IC xx'0040H 10H / 16D CAPCOM Register 17, or ERU Request 1 CC2_CC17IC xx'0044H 11H / 17D CAPCOM Register 18, or ERU Request 2 CC2_CC18IC xx'0048H 12H / 18D CAPCOM Register 19, or ERU Request 3 CC2_CC19IC xx'004CH 13H / 19D CAPCOM Register 20, or USIC0 Request 6 CC2_CC20IC xx'0050H 14H / 20D CAPCOM Register 21, or USIC0 Request 7 CC2_CC21IC xx'0054H 15H / 21D CAPCOM Register 22, or USIC1 Request 6 CC2_CC22IC xx'0058H 16H / 22D CAPCOM Register 23, or USIC1 Request 7 CC2_CC23IC xx'005CH 17H / 23D CAPCOM Register 24, or ERU Request 0 CC2_CC24IC xx'0060H 18H / 24D CAPCOM Register 25, or ERU Request 1 CC2_CC25IC xx'0064H 19H / 25D CAPCOM Register 26, or ERU Request 2 CC2_CC26IC xx'0068H 1AH / 26D CAPCOM Register 27, or ERU Request 3 CC2_CC27IC xx'006CH 1BH / 27D CAPCOM Register 28, or USIC2 Request 6 CC2_CC28IC xx'0070H 1CH / 28D CAPCOM Register 29, or USIC2 Request 7 CC2_CC29IC xx'0074H 1DH / 29D CAPCOM Register 30 CC2_CC30IC xx'0078H 1EH / 30D CAPCOM Register 31 CC2_CC31IC xx'007CH 1FH / 31D GPT1 Timer 2 GPT12E_T2IC xx'0080H 20H / 32D GPT1 Timer 3 GPT12E_T3IC xx'0084H 21H / 33D GPT1 Timer 4 GPT12E_T4IC xx'0088H 22H / 34D Data Sheet 39 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 6 XE164 Interrupt Nodes (cont'd) Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number GPT2 Timer 5 GPT12E_T5IC xx'008CH 23H / 35D GPT2 Timer 6 GPT12E_T6IC xx'0090H 24H / 36D GPT2 CAPREL Register GPT12E_CRIC xx'0094H 25H / 37D CAPCOM Timer 7 CC2_T7IC xx'0098H 26H / 38D CAPCOM Timer 8 CC2_T8IC xx'009CH 27H / 39D A/D Converter Request 0 ADC_0IC xx'00A0H 28H / 40D A/D Converter Request 1 ADC_1IC xx'00A4H 29H / 41D A/D Converter Request 2 ADC_2IC xx'00A8H 2AH / 42D A/D Converter Request 3 ADC_3IC xx'00ACH 2BH / 43D A/D Converter Request 4 ADC_4IC xx'00B0H 2CH / 44D A/D Converter Request 5 ADC_5IC xx'00B4H 2DH / 45D A/D Converter Request 6 ADC_6IC xx'00B8H 2EH / 46D A/D Converter Request 7 ADC_7IC xx'00BCH 2FH / 47D CCU60 Request 0 CCU60_0IC xx'00C0H 30H / 48D CCU60 Request 1 CCU60_1IC xx'00C4H 31H / 49D CCU60 Request 2 CCU60_2IC xx'00C8H 32H / 50D CCU60 Request 3 CCU60_3IC xx'00CCH 33H / 51D CCU61 Request 0 CCU61_0IC xx'00D0H 34H / 52D CCU61 Request 1 CCU61_1IC xx'00D4H 35H / 53D CCU61 Request 2 CCU61_2IC xx'00D8H 36H / 54D CCU61 Request 3 CCU61_3IC xx'00DCH 37H / 55D CCU62 Request 0 CCU62_0IC xx'00E0H 38H / 56D CCU62 Request 1 CCU62_1IC xx'00E4H 39H / 57D CCU62 Request 2 CCU62_2IC xx'00E8H 3AH / 58D CCU62 Request 3 CCU62_3IC xx'00ECH 3BH / 59D Unassigned node - xx'00F0H 3CH / 60D Unassigned node - xx'00F4H 3DH / 61D Unassigned node - xx'00F8H 3EH / 62D Unassigned node - xx'00FCH 3FH / 63D CAN Request 0 CAN_0IC xx'0100H 40H / 64D Data Sheet 40 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 6 XE164 Interrupt Nodes (cont'd) Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number CAN Request 1 CAN_1IC xx'0104H 41H / 65D CAN Request 2 CAN_2IC xx'0108H 42H / 66D CAN Request 3 CAN_3IC xx'010CH 43H / 67D CAN Request 4 CAN_4IC xx'0110H 44H / 68D CAN Request 5 CAN_5IC xx'0114H 45H / 69D CAN Request 6 CAN_6IC xx'0118H 46H / 70D CAN Request 7 CAN_7IC xx'011CH 47H / 71D CAN Request 8 CAN_8IC xx'0120H 48H / 72D CAN Request 9 CAN_9IC xx'0124H 49H / 73D CAN Request 10 CAN_10IC xx'0128H 4AH / 74D CAN Request 11 CAN_11IC xx'012CH 4BH / 75D CAN Request 12 CAN_12IC xx'0130H 4CH / 76D CAN Request 13 CAN_13IC xx'0134H 4DH / 77D CAN Request 14 CAN_14IC xx'0138H 4EH / 78D CAN Request 15 CAN_15IC xx'013CH 4FH / 79D USIC0 Cannel 0, Request 0 U0C0_0IC xx'0140H 50H / 80D USIC0 Cannel 0, Request 1 U0C0_1IC xx'0144H 51H / 81D USIC0 Cannel 0, Request 2 U0C0_2IC xx'0148H 52H / 82D USIC0 Cannel 1, Request 0 U0C1_0IC xx'014CH 53H / 83D USIC0 Cannel 1, Request 1 U0C1_1IC xx'0150H 54H / 84D USIC0 Cannel 1, Request 2 U0C1_2IC xx'0154H 55H / 85D USIC1 Cannel 0, Request 0 U1C0_0IC xx'0158H 56H / 86D USIC1 Cannel 0, Request 1 U1C0_1IC xx'015CH 57H / 87D USIC1 Cannel 0, Request 2 U1C0_2IC xx'0160H 58H / 88D USIC1 Cannel 1, Request 0 U1C1_0IC xx'0164H 59H / 89D USIC1 Cannel 1, Request 1 U1C1_1IC xx'0168H 5AH / 90D USIC1 Cannel 1, Request 2 U1C1_2IC xx'016CH 5BH / 91D USIC2 Cannel 0, Request 0 U2C0_0IC xx'0170H 5CH / 92D USIC2 Cannel 0, Request 1 U2C0_1IC xx'0174H 5DH / 93D USIC2 Cannel 0, Request 2 U2C0_2IC xx'0178H 5EH / 94D Data Sheet 41 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 6 XE164 Interrupt Nodes (cont'd) Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number USIC2 Cannel 1, Request 0 U2C1_0IC xx'017CH 5FH / 95D USIC2 Cannel 1, Request 1 U2C1_1IC xx'0180H 60H / 96D USIC2 Cannel 1, Request 2 U2C1_2IC xx'0184H 61H / 97D Unassigned node - xx'0188H 62H / 98D Unassigned node - xx'018CH 63H / 99D Unassigned node - xx'0190H 64H / 100D Unassigned node - xx'0194H 65H / 101D Unassigned node - xx'0198H 66H / 102D Unassigned node - xx'019CH 67H / 103D Unassigned node - xx'01A0H 68H / 104D Unassigned node - xx'01A4H 69H / 105D Unassigned node - xx'01A8H 6AH / 106D SCU Request 1 SCU_1IC xx'01ACH 6BH / 107D SCU Request 0 SCU_0IC xx'01B0H 6CH / 108D Program Flash Modules PFM_IC xx'01B4H 6DH / 109D RTC RTC_IC xx'01B8H 6EH / 110D End of PEC Subchannel EOPIC xx'01BCH 6FH / 111D 1) Register VECSEG defines the segment where the vector table is located. Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table represents the default setting with a distance of 4 (two words) between two vectors. Data Sheet 42 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description The XE164 includes an excellent mechanism to identify and process exceptions or error conditions that arise during run-time, the so-called `Hardware Traps'. A hardware trap causes an immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is also indicated by a single bit in the trap flag register (TFR). Unless another higherpriority trap service is in progress, a hardware trap will interrupt any ongoing program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 7 shows all possible exceptions or error conditions that can arise during runtime: Table 7 Trap Summary Exception Condition Trap Flag Trap Vector Vector Trap Trap 1) Number Priority Location Reset Functions - RESET xx'0000H 00H III Class A Hardware Traps: * System Request 0 * Stack Overflow * Stack Underflow * Software Break SR0 STKOF STKUF SOFTBRK SR0TRAP STOTRAP STUTRAP SBRKTRAP xx'0008H xx'0010H xx'0018H xx'0020H 02H 04H 06H 08H II II II II SR1 UNDOPC ACER PRTFLT BTRAP BTRAP BTRAP BTRAP xx'0028H xx'0028H xx'0028H xx'0028H 0AH 0AH 0AH 0AH I I I I ILLOPA BTRAP xx'0028H 0AH I Reserved - - [2CH - 3CH] [0BH 0FH] - Software Traps: * TRAP Instruction - - Any Any [xx'0000H - [00H xx'01FCH] 7FH] in steps of 4H Current CPU Priority Class B Hardware Traps: * System Request 1 * Undefined Opcode * Memory Access Error * Protected Instruction Fault * Illegal Word Operand Access 1) Register VECSEG defines the segment where the vector table is located to. Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table represents the default setting, with a distance of 4 (two words) between two vectors. Data Sheet 43 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.5 On-Chip Debug Support (OCDS) The On-Chip Debug Support system built into the XE164 provides a broad range of debug and emulation features. User software running on the XE164 can be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface. This consists of the JTAG port conforming to IEEE-1149. The debug interface can be completed with an optional break interface. The debugger controls the OCDS with a set of dedicated registers accessible via the debug interface (JTAG). In addition the OCDS system can be controlled by the CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-generated instructions by the CPU. Multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. Single stepping is supported, as is the injection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the activation of an external signal. Tracing data can be obtained via the debug interface, or via the external bus interface for increased performance. The JTAG interface uses four interface signals, to communicate with external circuitry. The debug interface can be amended with two optional break lines. Data Sheet 44 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.6 Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM2 unit is typically used to handle high-speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), digital to analog (D/A) conversion, software timing, or time recording with respect to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to a number of prescaled values of the internal system clock. It may also be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range for the timer period and resolution while allowing precise adjustments for application-specific requirements. An external count input for CAPCOM2 timer T7 allows event scheduling for the capture/compare registers with respect to external events. The capture/compare register array contains 16 dual purpose capture/compare registers. Each may be individually allocated to either CAPCOM2 timer T7 or T8 and programmed for a capture or compare function. 12 registers of the CAPCOM2 module have one port pin associated with it. This serves as an input pin to trigger the capture function or as an output pin to indicate the occurrence of a compare event. Table 8 Compare Modes (CAPCOM2) Compare Modes Function Mode 0 Interrupt-only compare mode; Several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; Several compare events per timer period are possible Mode 2 Interrupt-only compare mode; Only one compare interrupt per timer period is generated Mode 3 Pin set `1' on match; pin reset `0' on compare timer overflow; Only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; Pin toggles on each compare match; Several compare events per timer period are possible Single Event Mode Generates single edges or pulses; Can be used with any compare mode Data Sheet 45 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured') into the capture/compare register in response to an external event at the port pin associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the compare mode selected. Data Sheet 46 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Reload Reg. T7REL fCC T7IN T6OUF T7 Input Control Timer T7 CC16IO CC17IO CC16IRQ CC17IRQ Mode Control (Capture or Compare) Sixteen 16-bit Capture/ Compare Registers CC31IO fCC T6OUF T7IRQ CC31IRQ T8 Input Control Timer T8 T8IRQ Reload Reg. T8REL MC_CAPCOM2_BLOCKDIAG Figure 5 Data Sheet CAPCOM2 Unit Block Diagram 47 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.7 Capture/Compare Units CCU6x The XE164 features up to three CCU6 units (CCU60, CCU61, CCU62). The CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices with several CCU6 modules. The module provides two independent timers (T12, T13), that can be used for PWM generation, especially for AC motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features * * * * * * * * * * Three capture/compare channels, where each channel can be used either as a capture or as a compare channel. Supports generation of a three-phase PWM (six outputs, individual signals for highside and low-side switches) 16-bit resolution, maximum count frequency = peripheral clock Dead-time control for each channel to avoid short circuits in the power stage Concurrent update of the required T12/13 registers Center-aligned and edge-aligned PWM can be generated Single-shot mode supported Many interrupt request sources Hysteresis-like control mode Automatic start on a HW event (T12HR, for synchronization purposes) Timer 13 Features * * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock Can be synchronized to T12 Interrupt generation at period match and compare match Single-shot mode supported Automatic start on a HW event (T13HR, for synchronization purposes) Additional Features * * * * * * * Block commutation for brushless DC drives implemented Position detection via Hall sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC drives Output levels can be selected and adapted to the power stage Data Sheet 48 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description CCU6 Module Kernel fSYS com pare Channel 0 Channel 3 com pare 3 1 2 2 2 trap i nput T13 output select st art Trap Control Hal l i nput 1 Multichannel Control output select Channel 2 compa re 1 compa re Interrupts Channel 1 Deadtime Control compa re T12 capture TxHR 1 3 1 CTRAP CCPOS0 CCPOS1 CCPOS2 COUT60 CC60 COUT61 CC61 COUT62 CC62 COUT63 Input / Output Control m c_ccu6_blockdiagram . vsd Figure 6 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns that can be modulated by timer T12 and/or timer T13. The modulation sources can be selected and combined for signal modulation. Data Sheet 49 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.8 General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT12E unit incorporates five 16-bit timers organized in two separate modules, GPT1 and GPT2. Each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. Counter Mode allows timer clocking in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes each timer has one associated port pin (TxIN1)) which serves as a gate or clock input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles. The counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (TxEUD1)), e.g. to facilitate position tracking. In Incremental Interface Mode the GPT1 timers1) can be directly connected to the incremental position sensor signals A and B through their respective inputs TxIN and TxEUD. Direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components. It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to the basic operating modes, T2 may be configured as reload or capture register for timer T3. A timer used as capture or reload register is stopped. The contents of timer T3 is captured into T2 in response to a signal at the associated input pin (TxIN). Timer T3 is reloaded with the contents of T2, triggered either by an external signal or a selectable state transition of its toggle latch T3OTL. 1) Exception: Timer T4 is not connected to pins. Data Sheet 50 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description T3CON.BPS1 fGPT n 2 :1 Basic Clock Interrupt Request (T2IRQ) Aux. Timer T2 T2IN T2EUD U/D T2 Mode Reload Control Capture Interrupt Request (T3IRQ) T3IN T3 Mode Control T3EUD Core Timer T3 U/D T3OTL T3OUT Toggle Latch Capture T4IN T4EUD T4 Mode Control Reload Aux. Timer T4 U/D Interrupt Request (T4IRQ) MC_GPT_BLOCK1 Figure 7 Data Sheet Block Diagram of GPT1 51 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a port pin (TxEUD1)). Concatenation of the timers is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2 timers and to initiate a reload from the CAPREL register. The CAPREL register can capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared after the capture procedure. This allows the XE164 to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. 1) Exception: T5EUD is not connected to a pin. Data Sheet 52 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description T6CON.BPS2 fGPT 2n:1 Basic Clock Interrupt Request (T5IRQ) GPT2 Timer T5 T5IN T5EUD T5 Mode Control U/D Clear Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIRQ) Reload Clear Interrupt Request (T6IRQ) Toggle FF T6IN T6 Mode Control GPT2 Timer T6 T6OTL T6OUT T6OUF U/D T6EUD MC_GPT_BLOCK2 Figure 8 Data Sheet Block Diagram of GPT2 53 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.9 Real Time Clock The Real Time Clock (RTC) module of the XE164 can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: * * * Selectable 32:1 and 8:1 dividers (on - off) The reloadable 16-bit timer T14 The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of: - a reloadable 10-bit timer - a reloadable 6-bit timer - a reloadable 6-bit timer - a reloadable 10-bit timer All timers count up. Each timer can generate an interrupt request. All requests are combined to a common node request. fRTC :32 M UX RUN M UX Interrupt Sub Node :8 PRE REFCLK CNT INT0 CNT INT1 CNT INT2 RTCINT CNT INT3 REL-Register f CNT T14REL 10 Bits 6 Bits 6 Bits 10 Bits T14 10 Bits 6 Bits 6 Bits 10 Bits T14-Register CNT-Register M CB05568B Figure 9 RTC Block Diagram Note: The registers associated with the RTC are only affected by a power reset. Data Sheet 54 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description The RTC module can be used for different purposes: * * * * System clock to determine the current time and date Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources 48-bit timer for long-term measurements Alarm interrupt at a defined time Data Sheet 55 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.10 A/D Converters For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with 11 + 5 multiplexed input channels and a sample and hold circuit have been integrated on-chip. They use the successive approximation method. The sample time (to charge the capacitors) and the conversion time are programmable so that they can be adjusted to the external circuit. The A/D converters can also operate in 8-bit conversion mode, further reducing the conversion time. Several independent conversion result registers, selectable interrupt requests, and highly flexible conversion sequences provide a high degree of programmability to meet the application requirements. Both modules can be synchronized to allow parallel sampling of two input channels. For applications that require more analog input channels, external analog multiplexers can be controlled automatically. For applications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converters of the XE164 support two types of request sources which can be triggered by several internal and external events. * * Parallel requests are activated at the same time and then executed in a predefined sequence. Queued requests are executed in a user-defined sequence. In addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. All requests are arbitrated according to the priority level assigned to them. Data reduction features, such as limit checking or result accumulation, reduce the number of required CPU access operations allowing the precise evaluation of analoginputs (high conversion rate) even at a low CPU speed. The Peripheral Event Controller (PEC) can be used to control the A/D converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Each A/D converter contains eight result registers which can be concatenated to build a result FIFO. Wait-for-read mode can be enabled for each result register to prevent the loss of conversion data. In order to decouple analog inputs from digital noise and to avoid input trigger noise, those pins used for analog input can be disconnected from the digital input stages under software control. This can be selected for each pin separately with registers P5_DIDIS and P15_DIDIS (Port x Digital Input Disable). The Auto-Power-Down feature of the A/D converters minimizes the power consumption when no conversion is in progress. Data Sheet 56 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.11 Universal Serial Interface Channel Modules (USIC) The XE164 includes up to three USIC modules (USIC0, USIC1, USIC2), each providing two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure which is identical for all supported serial communication protocols. Each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). In addition, the data handling software can use FIFOs. The protocol part (generation of shift clock/data/control signals) is independent of the general part and is handled by protocol-specific preprocessors (PPPs). The USIC's input/output lines are connected to pins by a pin routing unit. The inputs and outputs of each USIC channel can be assigned to different interface pins, providing great flexibility to the application software. All assignments can be made during runtime. Bus Buffer & Shift Structure Protocol Preprocessors Pins Control 0 DBU 0 PPP_B DSU 0 PPP_C PPP_D Control 1 PPP_A DBU 1 Pin Routing Shell Bus Interface PPP_A PPP_B DSU 1 PPP_C PPP_D fsys Fractional Dividers Baud rate Generators USIC_basic.vsd Figure 10 General Structure of a USIC Module The regular structure of the USIC module brings the following advantages: * * * Higher flexibility through configuration with same look-and-feel for data management Reduced complexity for low-level drivers serving different protocols Wide range of protocols with improved performances (baud rate, buffer handling) Data Sheet 57 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols: * * * * * UART (asynchronous serial channel) - maximum baud rate: fSYS / 4 - data frame length programmable from 1 to 63 bits - MSB or LSB first LIN Support (Local Interconnect Network) - maximum baud rate: fSYS / 16 - checksum generation under software control - baud rate detection possible by built-in capture event of baud rate generator SSC/SPI/QSPI (synchronous serial channel with or without data buffer) - maximum baud rate in slave mode: fSYS - maximum baud rate in master mode: fSYS / 2, limited by loop delay - number of data bits programmable from 1 to 63, more with explicit stop condition - MSB or LSB first - optional control of slave select signals IIC (Inter-IC Bus) - supports baud rates of 100 kbit/s and 400 kbit/s IIS (Inter-IC Sound Bus) - maximum baud rate: fSYS / 2 for transmitter, fSYS for receiver Note: Depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. Please note that there may be additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in UART mode, for IIC, etc.). Data Sheet 58 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.12 MultiCAN Module The MultiCAN module contains up to four independently operating CAN nodes with FullCAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All CAN nodes share a common set of 128 message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer. The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. MultiCAN Module Kernel Clock Control Address Decoder CAN Node 4 fC AN Message Object Buffer 128 Objects . . . Linked List Control CAN Node 1 CAN Node 0 Interrupt Control TX DC4 RXDC4 . . . TX DC1 RXDC1 Port Control . . . TX DC0 RXDC0 CAN Control mc_multican_block5.vsd Figure 11 Data Sheet Block Diagram of MultiCAN Module 59 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description MultiCAN Features * * * * * * * * * * CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) Up to four independent CAN nodes 128 independent message objects (shared by the CAN nodes) Dedicated control registers for each CAN node Data transfer rate up to 1 Mbit/s, individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality for message objects: - Can be assigned to one of the CAN nodes - Configurable as transmit or receive objects, or as message buffer FIFO - Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering - Remote Monitoring Mode, and frame counter for monitoring Automatic Gateway Mode support 16 individually programmable interrupt nodes Analyzer mode for CAN bus monitoring Data Sheet 60 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.13 Watchdog Timer The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the chip. It can be disabled and enabled at any time by executing the instructions DISWDT and ENWDT respectively. The software has to service the Watchdog Timer before it overflows. If this is not the case because of a hardware or software failure, the Watchdog Timer overflows, generating a prewarning interrupt and then a reset request. The Watchdog Timer is a 16-bit timer clocked with the system clock divided by 16,384 or 256. The Watchdog Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the Watchdog Timer is reloaded and the prescaler is cleared. Time intervals between 3.2 s and 13.4 s can be monitored (@ 80 MHz). The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz). 3.14 Clock Generation The Clock Generation Unit can generate the system clock signal fSYS for the XE164 from a number of external or internal clock sources: * * * * External clock signals with pad or core voltage levels External crystal using the on-chip oscillator On-chip clock source for operation without crystal Wake-up clock (ultra-low-power) to further reduce power consumption The programmable on-chip PLL with multiple prescalers generates a clock signal for maximum system performance from standard crystals or from the on-chip clock source. See also Section 4.6.2. The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. In this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure. All available clock signals can be output on one of two selectable pins. Data Sheet 61 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.15 Parallel Ports The XE164 provides up to 75 I/O lines which are organized into 7 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. This configuration selects the direction (input/output), push/pull or open-drain operation, activation of pull devices, and edge characteristics (shape) and driver characteristics (output current) of the port drivers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs without pull devices active. All port lines have alternate input or output functions associated with them. These alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. For this reason, certain functions appear several times in Table 9. All port lines that are not used for alternate functions may be used as general purpose I/O lines. Table 9 Summary of the XE164's Parallel Ports Port Width Alternate Functions Port 0 8 Address lines, Serial interface lines of USIC1, CAN0, and CAN1, Input/Output lines for CCU61 Port 1 8 Address lines, Serial interface lines of USIC1 and USIC2, Input/Output lines for CCU62, OCDS control, interrupts Port 2 13 Address and/or data lines, bus control, Serial interface lines of USIC0, CAN0, and CAN1, Input/Output lines for CCU60 and CAPCOM2, Timer control signals, JTAG, interrupts, system clock output Port 4 8 Chip select signals, Serial interface lines of CAN2, Input/Output lines for CAPCOM2, Timer control signals Port 5 16 Analog input channels to ADC0, Input/Output lines for CCU6x, Timer control signals, JTAG, OCDS control, interrupts Data Sheet 62 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 9 Summary of the XE164's Parallel Ports (cont'd) Port Width Alternate Functions Port 6 4 ADC control lines, Serial interface lines of USIC1, Timer control signals, OCDS control Port 7 5 ADC control lines, Serial interface lines of USIC0, Input/Output lines for CCU62, Timer control signals, JTAG, OCDS control,system clock output Port 10 16 Address and/or data lines, bus control, Serial interface lines of USIC0, USIC1, CAN2 and CAN3, Input/Output lines for CCU60, JTAG, OCDS control Port 15 8 Analog input channels to ADC1, Timer control signals Data Sheet 63 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description 3.16 Instruction Set Summary Table 10 lists the instructions of the XE164. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "Instruction Set Manual". This document also provides a detailed description of each instruction. Table 10 Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16- x 16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise exclusive OR, (word/byte operands) 2/4 BCLR/BSET Clear/Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 CMP(B) Compare word (byte) operands 2/4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL/SHR Shift left/right direct word GPR 2 Data Sheet 64 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 10 Instruction Set Summary (cont'd) Mnemonic Description Bytes ROL/ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS/Z Move byte operand to word op. with sign/zero extension 2/4 JMPA/I/R Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 JB(C) Jump relative if direct bit is set (and clear bit) 4 JNB(S) Jump relative if direct bit is not set (and set bit) 4 CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH/POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand 4 RET(P) Return from intra-segment subroutine (and pop direct word register from system stack) 2 RETS Return from inter-segment subroutine 2 RETI Return from interrupt service subroutine 2 SBRK Software Break 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Unused instruction1) 4 SRVWDT Service Watchdog Timer 4 DISWDT/ENWDT Disable/Enable Watchdog Timer 4 EINIT End-of-Initialization Register Lock 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 Data Sheet 65 V2.1, 2008-08 XE164x XE166 Family Derivatives Functional Description Table 10 Instruction Set Summary (cont'd) Mnemonic Description Bytes NOP Null operation 2 CoMUL/CoMAC Multiply (and accumulate) 4 CoADD/CoSUB Add/Subtract 4 Co(A)SHR (Arithmetic) Shift right 4 CoSHL Shift left 4 CoLOAD/STORE Load accumulator/Store MAC register 4 CoCMP Compare 4 CoMAX/MIN Maximum/Minimum 4 CoABS/CoRND Absolute value/Round accumulator 4 CoMOV Data move 4 CoNEG/NOP Negate accumulator/Null operation 4 1) The Enter Power Down Mode instruction is not used in the XE164, due to the enhanced power control scheme. PWRDN will be correctly decoded, but will trigger no action. Data Sheet 66 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4 Electrical Parameters The operating range for the XE164 is defined by its electrical parameters. For proper operation the specified limits must be respected during system design. Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. Additional details are described where applicable. 4.1 General Parameters These parameters are valid for all subsequent descriptions, unless otherwise noted. Table 11 Absolute Maximum Rating Parameters Parameter Symbol Min. Typ. Max. Unit Note / Test Condition TST Junction temperature TJ Voltage on VDDI pins with VDDIM, VDDI1 respect to ground (VSS) Voltage on VDDP pins with VDDPA, respect to ground (VSS) VDDPB Voltage on any pin with VIN respect to ground (VSS) -65 - 150 C - -40 - 125 C under bias -0.5 - 1.65 V - -0.5 - 6.0 V - -0.5 - VDDP V VIN < VDDPmax Input current on any pin during overload condition - -10 - 10 mA - Absolute sum of all input currents during overload condition - - - |100| mA - Output current on any pin IOH, IOL - - |30| mA - Storage temperature Values + 0.5 Note: Stresses above the values listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for an extended time may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 67 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XE164. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 12 Operating Condition Parameters Parameter Symbol Digital core supply voltage VDDI Values Min. Typ. Max. Unit Note / Test Condition 1.4 - 1.6 V - +10 mV Core Supply Voltage Difference VDDI -10 Digital supply voltage for IO pads and voltage regulators, upper voltage range VDDPA, VDDPB 4.5 - 5.5 V 2) Digital supply voltage for IO pads and voltage regulators, lower voltage range VDDPA, VDDPB 3.0 - 4.5 V 2) Digital ground voltage VSS 0 - 0 V Reference voltage Overload current IOV -5 - 5 mA Per IO pin3)4) -2 - 5 mA Per analog input pin3)4) KOVA - 1.0 x 10-6 1.0 x 10-4 - IOV > 0 Overload negative current KOVA coupling factor for analog inputs5) - 2.5 x 10-4 1.5 x 10-3 - IOV < 0 KOVD - 1.0 x 10-4 5.0 x 10-3 - IOV > 0 Overload negative current KOVD coupling factor for digital I/O pins5) - 1.0 x 10-2 3.0 x 10-2 - IOV < 0 - - 50 mA 4) Overload positive current coupling factor for analog inputs5) Overload positive current coupling factor for digital I/O pins5) Absolute sum of overload currents Data Sheet |IOV| VDDIM - VDDI1 1) 68 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 12 Operating Condition Parameters (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition External Pin Load Capacitance CL - 20 - pF Pin drivers in default mode6) Voltage Regulator Buffer Capacitance for DMP_M CEVRM 1.0 - 4.7 F 7) Voltage Regulator Buffer Capacitance for DMP_1 CEVR1 0.47 - 2.2 F One for each supply pin7) Operating frequency fSYS TA - - 80 MHz 8) - - - C See Table 1 Ambient temperature 1) If both core power domains are clocked, the difference between the power supply voltages must be less than 10 mV. This condition imposes additional constraints when using external power supplies. Do not combine internal and external supply of different core power domains. Do not supply the core power domains with two independent external voltage regulators. The simplest method is to supply both power domains directly via a single external power supply. 2) Performance of pad drivers, A/D Converter, and Flash module depends on VDDP. If the external supply voltage VDDP becomes lower than the specified operating range, a power reset must be generated. Otherwise, the core supply voltage VDDI may rise above its specified operating range due to parasitic effects. This power reset can be generated by the on-chip SWD. If the SWD is disabled the power reset must be generated by activating the PORST input. 3) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin (IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload conditions depends on the application. Overload conditions must not occur on pin XTAL1 (powered by VDDI). 4) Not subject to production test - verified by design/characterization. 5) An overload current (IOV) through a pin injects an error current (IINJ) into the adjacent pins. This error current adds to that pin's leakage current (IOZ). The value of the error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is reversed from the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ| + (|IOV| x KOV). The additional error current may distort the input voltage on analog inputs. 6) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (CL). 7) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate buffer capacitors with the recomended values shall be connected as close as possible to each VDDI pin to keep the resistance of the board tracks below 2 . Connect all VDDI1 pins together. The minimum capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values slightly increase the startup time. 8) The operating frequency range may be reduced for specific types of the device designation (...FxxL). 80-MHz devices are marked ...F80L. Data Sheet 69 XE164. This is indicated in the V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Parameter Interpretation The parameters listed in the following include both the characteristics of the XE164 and its demands on the system. To aid in correctly interpreting the parameters when evaluating them for a design, they are marked accordingly in the column "Symbol": CC (Controller Characteristics): The logic of the XE164 provides signals with the specified characteristics. SR (System Requirement): The external system must provide signals with the specified characteristics to the XE164. Data Sheet 70 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.2 DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XE164 can operate within a wide supply voltage range from 3.0 V to 5.5 V. However, during operation this supply voltage must remain within 10 percent of the selected nominal supply voltage. It cannot vary across the full operating voltage range. Because of the supply voltage restriction and because electrical behavior depends on the supply voltage, the parameters are specified separately for the upper and the lower voltage range. During operation, the supply voltages may only change with a maximum speed of dV/dt < 1 V/ms. Leakage current is strongly dependent on the operating temperature and the voltage level at the respective pin. The maximum values in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. The value for the leakage current in an application can be determined by using the respective leakage derating formula (see tables) with values from that application. The pads of the XE164 are designed to operate in various driver modes. The DC parameter specifications refer to the current limits in Table 13. Table 13 Current Limits for Port Output Drivers Port Output Driver Mode Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current (IOLnom, -IOHnom) VDDP 4.5 V VDDP < 4.5 V VDDP 4.5 V VDDP < 4.5 V Strong driver 10 mA 10 mA 2.5 mA 2.5 mA Medium driver 4.0 mA 2.5 mA 1.0 mA 1.0 mA Weak driver 0.5 mA 0.5 mA 0.1 mA 0.1 mA 1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring output pins, the total output current in each direction (IOL and -IOH) must remain below 50 mA. Data Sheet 71 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Pullup/Pulldown Device Behavior Most pins of the XE164 feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the respective pin depending on the intended signal level. Figure 12 shows the current paths. The shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values. VDDP Pullup Pulldown VSS MC_XC2X_PULL Figure 12 Data Sheet Pullup/Pulldown Current Definition 72 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.2.1 DC Parameters for Upper Voltage Area These parameters apply to the upper IO voltage range, 4.5 V VDDP 5.5 V. Table 14 DC Characteristics for Upper Voltage Range (Operating Conditions apply)1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition - 0.3 x V - - VDDP VDDP V - V VDDP in [V], Input low voltage (all except XTAL1) VIL SR -0.3 Input high voltage (all except XTAL1) VIH SR 0.7 x Input Hysteresis2) HYS CC 0.11 - x VDDP - VOL CC - VOL CC - VOH CC VDDP - 1.0 V - 0.4 V - - V IOL IOLmax3) IOL IOLnom3)4) IOH IOHmax3) VOH CC VDDP - - V IOH IOHnom3)4) Input leakage current (Port 5, Port 15)6) IOZ1 CC - 10 200 nA 0 V < VIN < VDDP Input leakage current (all other)6)7) IOZ2 CC - 0.2 5 A Pull level keep current IPLK - - 30 A Pull level force current IPLF 250 - - A TJ 110C, 0.45 V < VIN < VDDP VPIN VIH (up)8) VPIN VIL (dn) VPIN VIL (up)8) VPIN VIH (dn) Pin capacitance9) (digital inputs/outputs) CIO CC - - 10 pF Output low voltage Output low voltage Output high voltage5) VDDP + 0.3 Series resistance = 0 - 1.0 5) Output high voltage - 0.4 1) Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. 2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 13, Current Limits for Port Output Drivers. The limit for pin groups must be respected. Data Sheet 73 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4) As a rule, with decreasing output current the output levels approach the respective supply level (VOLVSS, VOHVDDP). However, only the levels for nominal output currents are verified. 5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 6) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 7) The given values are worst-case values. In production test, this leakage current is only tested at 125C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [C]): IOZ = 0.05 x e(1.5 + 0.028xTJ) [A]. For example, at a temperature of 95C the resulting leakage current is 3.2 A. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) [A] This voltage derating formula is an approximation which applies for maximum temperature. Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal leakage. 8) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN VIH for a pullup; VPIN VIL for a pulldown. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN VIL for a pullup; VPIN VIH for a pulldown. These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 9) Not subject to production test - verified by design/characterization. Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal capacitance. Data Sheet 74 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.2.2 DC Parameters for Lower Voltage Area These parameters apply to the lower IO voltage range, 3.0 V VDDP 4.5 V. Table 15 DC Characteristics for Lower Voltage Range (Operating Conditions apply)1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition - 0.3 x V - - VDDP VDDP V - V VDDP in [V], Input low voltage (all except XTAL1) VIL SR -0.3 Input high voltage (all except XTAL1) VIH SR 0.7 x Input Hysteresis2) HYS CC 0.07 - x VDDP - VOL CC - VOL CC - VOH CC VDDP - 1.0 V - 0.4 V - - V IOL IOLmax3) IOL IOLnom3)4) IOH IOHmax3) VOH CC VDDP - - V IOH IOHnom3)4) Input leakage current (Port 5, Port 15)6) IOZ1 CC - 10 200 nA 0 V < VIN < VDDP Input leakage current (all other)6)7) IOZ2 CC - 0.2 2.5 A Pull level keep current IPLK - - 10 A Pull level force current IPLF 150 - - A TJ 110C, 0.45 V < VIN < VDDP VPIN VIH (up)8) VPIN VIL (dn) VPIN VIL (up)8) VPIN VIH (dn) Pin capacitance9) (digital inputs/outputs) CIO CC - - 10 pF Output low voltage Output low voltage Output high voltage5) VDDP + 0.3 Series resistance = 0 - 1.0 5) Output high voltage - 0.4 1) Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. 2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 13, Current Limits for Port Output Drivers. The limit for pin groups must be respected. Data Sheet 75 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4) As a rule, with decreasing output current the output levels approach the respective supply level (VOLVSS, VOHVDDP). However, only the levels for nominal output currents are verified. 5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 6) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. The leakage current value is not tested in the lower voltage range but only in the upper voltage range. This parameter is ensured by correlation. 7) The given values are worst-case values. In production test, this leakage current is only tested at 125C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [C]): IOZ = 0.03 x e(1.35 + 0.028xTJ) [A]. For example, at a temperature of 95C the resulting leakage current is 1.65 A. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.3 x DV) [A] This voltage derating formula is an approximation which applies for maximum temperature. Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal leakage. 8) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN VIH for a pullup; VPIN VIL for a pulldown. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN VIL for a pullup; VPIN VIH for a pulldown. These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 9) Not subject to production test - verified by design/characterization. Because pin P2.8 is connected to two pads (standard pad and high-speed clock pad), it has twice the normal capacitance. Data Sheet 76 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.2.3 Power Consumption The power consumed by the XE164 depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: * * The switching current IS depends on the device activity The leakage current ILK depends on the device temperature To determine the actual power consumption, always both components, switching current IS (Table 16) and leakage current ILK (Table 17) must be added: IDDP = IS + ILK. Note: The power consumption values are not subject to production test. They are verified by design/characterization. To determine the total power consumption for dimensioning the external power supply, also the pad driver currents must be considered. The given power consumption parameters and their values refer to specific operating conditions: * * Active mode: Regular operation, i.e. peripherals are active, code execution out of Flash. Stopover mode: Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1 stopped. Note: The maximum values cover the complete specified operating range of all manufactured devices. The typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperature, application-oriented activity. After a power reset, the decoupling capacitors for VDDI are charged with the maximum possible current, see parameter ICC in Table 20. For additional information, please refer to Section 5.2, Thermal Considerations. Data Sheet 77 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 16 Switching Power Consumption XE164 (Operating Conditions apply) Parameter SymValues bol Min. Typ. Max. Power supply current ISACT (active) with all peripherals active and EVVRs on Power supply current in stopover mode, EVVRs on ISSO Unit Note / Test Condition - 10 + 10 + mA 0.6xfSYS 1.0xfSYS Active mode1)2) fSYS in [MHz] - 1.0 Stopover Mode2) 2.0 mA 1) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current consumed by the pin output drivers. A small current is consumed because the drivers' input stages are switched. 2) The pad supply voltage has only a minor influence on this parameter. Data Sheet 78 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters IS [mA] 100 ISACTmax 90 80 70 ISACTtyp 60 50 40 30 20 10 20 40 60 80 fSYS [MHz] MC_XC2XM_IS Figure 13 Data Sheet Supply Current in Active Mode as a Function of Frequency 79 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 17 Leakage Power Consumption XE164 (Operating Conditions apply) Parameter Symbol Min. ILK1 Leakage supply current2) Formula3): 600,000 x e-; = 5000 / (273 + BxTJ); Typ.: B = 1.0, Max.: B = 1.3 Values Typ. Max. Unit Note / Test Condition1) - 0.03 0.05 mA - 0.5 1.3 mA - 2.1 6.2 mA TJ = 25C TJ = 85C TJ = 125C 1) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs (including pins configured as outputs) are disconnected. 2) The supply current caused by leakage depends mainly on the junction temperature (see Figure 14) and the supply voltage. The temperature difference between the junction temperature TJ and the ambient temperature TA must be taken into account. As this fraction of the supply current does not depend on device activity, it must be added to other power consumption values. 3) This formula is valid for temperatures above 0C. For temperatures below 0C a value of below 10 A can be assumed. ILK [mA] 10 8 ILK1max 6 4 ILK1typ 2 -50 0 100 50 150 TJ [C] MC_XC2X_ILK125 Figure 14 Leakage Supply Current as a Function of Temperature Data Sheet 80 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.3 Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Table 18 A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Max. Unit Test Condition VAREF SR VAGND + 1.0 VDDPA V 1) VAGND SR VSS - 0.05 VAREF V - VAIN SR VAGND VAREF V 2) 20 MHz 3) CC (13 + STC) x tADCI + 2 x tSYS - - CC (11 + STC) x tADCI + 2 x tSYS - - Wakeup time from analog tWAF powerdown, fast mode CC - 1 s - Wakeup time from analog tWAS powerdown, slow mode CC - 10 s - Total unadjusted error5) TUE CC - 2 LSB VAREF = 5.0 V1) DNL error EADNL CC - 1 LSB INL error EAINL CC - 1.2 LSB Gain error EAGAIN CC - 0.8 LSB Offset error EAOFF CC - 0.8 LSB Total capacitance of an analog input CAINT CC - 10 pF 6)7) Switched capacitance of an analog input CAINS CC - 4 pF 6)7) Resistance of the analog input path RAIN CC - 1.5 k 6)7) Total capacitance of the reference input CAREFT CC - 15 pF 6)7) Analog reference supply Analog reference ground Analog input voltage range fADCI Conversion time for 10-bit tC10 Analog clock frequency result4) Conversion time for 8-bit result4) Data Sheet tC8 0.5 81 + 0.05 - 1.0 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 18 A/D Converter Characteristics (cont'd) (Operating Conditions apply) Parameter Symbol Limit Values Min. Max. Unit Test Condition Switched capacitance of the reference input CAREFS CC - 7 pF 6)7) Resistance of the reference input path RAREF 2 k 6)7) CC - 1) TUE is tested at VAREFx = VDDPA, VAGND = 0 V. It is verified by design for all other voltages within the defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on Port 5 or Port 15 pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. Values for the basic clock tADCI depend on programming and are found in Table 19. 5) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 6) Not subject to production test - verified by design/characterization. 7) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 k, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 k. RSource V AIN R AIN, On C AINT - C AINS C Ext A/D Converter CAINS MCS05570 Figure 15 Data Sheet Equivalent Circuitry for Analog Inputs 82 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Sample time and conversion time of the XE164's A/D converters are programmable. The timing above can be calculated using Table 19. The limit values for fADCI must not be exceeded when selecting the prescaler value. Table 19 A/D Converter Computation Table GLOBCTR.5-0 (DIVA) A/D Converter Analog Clock fADCI INPCRx.7-0 (STC) 000000B fSYS fSYS / 2 fSYS / 3 fSYS / (DIVA+1) fSYS / 63 fSYS / 64 00H 000001B 000010B : 111110B 111111B 01H 02H : FEH FFH Sample Time tS tADCI x 2 tADCI x 3 tADCI x 4 tADCI x (STC+2) tADCI x 256 tADCI x 257 Converter Timing Example A: Assumptions: Analog clock Sample time fSYS fADCI tS = 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H = fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns = tADCI x 2 = 100 ns Conversion 10-bit: tC10 = 13 x tADCI + 2 x tSYS = 13 x 50 ns + 2 x 12.5 ns = 0.675 s Conversion 8-bit: tC8 = 11 x tADCI + 2 x tSYS = 11 x 50 ns + 2 x 12.5 ns = 0.575 s Converter Timing Example B: Assumptions: Analog clock Sample time fSYS fADCI tS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H = fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns = tADCI x 5 = 375 ns Conversion 10-bit: tC10 = 16 x tADCI + 2 x tSYS = 16 x 75 ns + 2 x 25 ns = 1.25 s Conversion 8-bit: tC8 Data Sheet = 14 x tADCI + 2 x tSYS = 14 x 75 ns + 2 x 25 ns = 1.10 s 83 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.4 System Parameters The following parameters specify several aspects which are important when integrating the XE164 into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 20 Various System Parameters Parameter Min. Typ. Max. Unit Note / Test Condition VLV - VLV VLV + V VLV - VLV VLV + V Core voltage (PVC) supervision level (see Table 22) VPVC CC VLV - VLV VLV + V Current control limit ICC CC 13 - 30 mA Power domain DMP_M 90 - 150 mA Power domain DMP_1 FREQSEL = 00B Supply watchdog (SWD) supervision level (see Table 21) Symbol VSWD CC Values 0.150 0.125 0.070 0.100 voltage in upper voltage area 0.050 0.030 VLV = selected voltage fWU CC 400 500 600 kHz Internal clock source frequency fINT CC 4.8 5.0 5.2 MHz Startup time from stopover mode tSSO CC 200 260 320 s 84 VLV = selected voltage in lower voltage area Wakeup clock source frequency Data Sheet VLV = selected User instruction from PSRAM V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 21 Coding of Bitfields LEVxV in Register SWDCON0 Code Default Voltage Level 0000B 2.9 V 0001B 3.0 V 0010B 3.1 V 0011B 3.2 V 0100B 3.3 V 0101B 3.4 V 0110B 3.6 V 0111B 4.0 V 1000B 4.2 V 1001B 4.5 V 1010B 4.6 V 1011B 4.7 V 1100B 4.8 V 1101B 4.9 V 1110B 5.0 V 1111B 5.5 V Notes1) LEV1V: reset request LEV2V: no request 1) The indicated default levels are selected automatically after a power reset. Table 22 Coding of Bitfields LEVxV in Registers PVCyCONz Notes1) Code Default Voltage Level 000B 0.9 V 001B 1.0 V 010B 1.1 V 011B 1.2 V 100B 1.3 V LEV1V: reset request 101B 1.4 V LEV2V: interrupt request 110B 1.5 V 111B 1.6 V 1) The indicated default levels are selected automatically after a power reset. Data Sheet 85 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.5 Flash Memory Parameters The XE164 is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XE164's Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 23 Flash Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Typ. Max. Unit Note / Test Condition Programming time per 128-byte page tPR - 31) 3.5 ms ms Erase time per sector/page tER - 41) 5 ms ms Data retention time tRET 20 - - years 1,000 erase / program cycles Flash erase endurance for NER user sectors2) 15,000 - - cycles Data retention time 5 years Flash erase endurance for NSEC security pages 10 - - cycles Data retention time 20 years 64 - - cycles Drain disturb limit NDD 3) 1) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. This requirement is only relevant for extremely low system frequencies. In the XE164 erased areas must be programmed completely (with actual code/data or dummy values) before that area is read. 2) A maximum of 64 Flash sectors can be cycled 15,000 times. For all other sectors the limit is 1,000 cycles. 3) This parameter limits the number of subsequent programming operations within a physical sector. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this limit will not be violated. Access to the XE164 Flash modules is controlled by the IMB. Built-in prefetch mechanisms optimize the performance for sequential access. Flash access waitstates only affect non-sequential access. Due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates. Data Sheet 86 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 24 Flash Access Waitstates Required Waitstates System Frequency Range 4 WS (WSFLASH = 100B) 1 WS (WSFLASH = 001B) fSYS fSYSmax fSYS 17 MHz fSYS 13 MHz fSYS 8 MHz 0 WS (WSFLASH = 000B) Forbidden! Must not be selected! 3 WS (WSFLASH = 011B) 2 WS (WSFLASH = 010B) Note: The maximum achievable system frequency is limited by the properties of the respective derivative. Data Sheet 87 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6 AC Parameters These parameters describe the dynamic behavior of the XE164. 4.6.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Output delay Hold time Hold time 0.8 V DDP 0.7 V DDP Input Signal (driven by tester) 0.3 V DDP 0.2 V DDP Output Signal (measured) Output timings refer to the rising edge of CLKOUT. Input timings are calculated from the time, when the input signal reaches V IH or V IL, respectively. MCD05556C Figure 16 Input Output Waveforms VLoad + 0.1 V Timing Reference Points V Load - 0.1 V V OH - 0.1 V V OL + 0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA). MCA05565 Figure 17 Data Sheet Floating Waveforms 88 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6.2 Definition of Internal Timing The internal operation of the XE164 is controlled by the internal system clock fSYS. Because the system clock signal fSYS can be generated from a number of internal and external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as well as the derived external timing) depend on the mechanism used to generate fSYS. This must be considered when calculating the timing for the XE164. Phase Locked Loop Operation (1:N) f IN f SYS TCS Direct Clock Drive (1:1) f IN f SYS TCS Prescaler Operation (N:1) f IN f SYS TCS M C_XC2X_CLOCKGEN Figure 18 Generation Mechanisms for the System Clock Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the example of prescaler operation uses a divider factor of 2:1. The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS). Data Sheet 89 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is derived directly from the input clock signal CLKIN1: fSYS = fIN. The frequency of fSYS is the same as the frequency of fIN. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fIN. Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results in a similar configuration. Prescaler Operation When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 1B), the system clock is derived either from the crystal oscillator (input clock signal XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1): fSYS = fOSC / K1. If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fOSC (external or internal). The lowest system clock frequency results from selecting the maximum value for the divider factor K1: fSYS = fOSC / 1024. Phase Locked Loop (PLL) When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B), the on-chip phase locked loop is enabled and provides the system clock. The PLL multiplies the input frequency by the factor F (fSYS = fIN x F). F is calculated from the input divider P (= PDIV+1), the multiplication factor N (= NDIV+1), and the output divider K2 (= K2DIV+1): (F = N / (P x K2)). The input clock can be derived either from an external source at XTAL1 or from the onchip clock source. The PLL circuit synchronizes the system clock to the input clock. This synchronization is performed smoothly so that the system clock frequency does not change abruptly. Adjustment to the input clock continuously changes the frequency of fSYS so that it is locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration of individual TCSs. 1) Voltages on XTAL1 must comply to the core supply voltage VDDI1. Data Sheet 90 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitter is limited. This means that the relative deviation for periods of more than one TCS is lower than for a single TCS (see formulas and Figure 19). This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles is K2 x T, where T is the number of consecutive fSYS cycles (TCS). The maximum accumulated jitter (long-term jitter) DTmax is defined by: DTmax [ns] = (220 / (K2 x fSYS) + 4.3) This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or the prescaler value K2 > 17. In all other cases for a timeframe of T x TCS the accumulated jitter DT is determined by: DT [ns] = DTmax x [(1 - 0.058 x K2) x (T - 1) / (0.83 x fSYS - 1) + 0.058 x K2] fSYS in [MHz] in all formulas. Example, for a period of 3 TCSs @ 33 MHz and K2 = 4: Dmax = (220 / (4 x 33) + 4.3) = 5.97 ns (Not applicable directly in this case!) D3 = 5.97 x [(1 - 0.058 x 4) x (3 - 1) / (0.83 x 33 - 1) + 0.058 x 4] = 5.97 x [0.768 x 2 / 26.39 + 0.232] = 1.7 ns Example, for a period of 3 TCSs @ 33 MHz and K2 = 2: Dmax = (220 / (2 x 33) + 4.3) = 7.63 ns (Not applicable directly in this case!) D3 = 7.63 x [(1 - 0.058 x 2) x (3 - 1) / (0.83 x 33 - 1) + 0.058 x 2] = 7.63 x [0.884 x 2 / 26.39 + 0.116] = 1.4 ns Data Sheet 91 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Acc. jitter DT ns 9 fSYS = 33 MHz fSYS = 66 MHz fVCO = 66 MHz 8 7 f VCO = 132 MHz 6 5 4 3 2 1 0 Cycles T 1 20 40 60 80 100 MC_XC 2X_JITTER Figure 19 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF (see Table 12). The maximum peak-to-peak noise on the pad supply voltage (measured between VDDPB pin 100/144 and VSS pin 1) is limited to a peak-to-peak voltage of VPP = 50 mV. This can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using PCB supply and ground planes. Different frequency bands can be selected for the VCO so that the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 25 VCO Bands for PLL Operation1) PLLCON0.VCOSEL VCO Frequency Range Base Frequency Range 00 50 ... 110 MHz 10 ... 40 MHz 01 100 ... 160 MHz 20 ... 80 MHz 1X Reserved 1) Not subject to production test - verified by design/characterization. Data Sheet 92 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is derived from the low-frequency wakeup clock source: fSYS = fWU. In this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption. Selecting and Changing the Operating Frequency When selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bitfields, to avoid unintended intermediate states. Many applications change the frequency of the system clock (fSYS) during operation in order to optimize system performance and power consumption. Changing the operating frequency also changes the switching currents, which influences the power supply. To ensure proper operation of the on-chip EVRs while they generate the core voltage, the operating frequency shall only be changed in certain steps. This prevents overshoots and undershoots of the supply voltage. To avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. Please refer to the Programmer's Guide. Data Sheet 93 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6.3 External Clock Input Parameters These parameters specify the external clock generation for the XE164. The clock can be generated in two ways: * * By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2. By supplying an external clock signal. This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain). If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH. In connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator. Note: The given clock timing parameters (t1 ... t4) are only valid for an external clock input signal. Table 26 External Clock Input Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Typ. Max. Unit Note / Test Condition - 1.7 V 1) - - V Peak-to-peak voltage2) - 20 A 0 V < VIN < VDDI - 40 MHz Clock signal 4 - 16 MHz Crystal or Resonator 6 - - ns 6 - - ns - 8 8 ns - 8 8 ns Min. Input voltage range limits for signal on XTAL1 Input voltage (amplitude) on XTAL1 XTAL1 input current Oscillator frequency High time Low time Rise time Fall time VIX1 SR -1.7 + VDDI VAX1 SR 0.3 x VDDI IIL CC - fOSC CC 4 t1 SR t2 SR t3 SR t4 SR 1) Overload conditions must not occur on pin XTAL1. 2) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. Data Sheet 94 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters t3 t1 VOFF VAX1 t2 t4 tOSC = 1/fOSC MC_EXTCLOCK Figure 20 External Clock Drive XTAL1 Note: For crystal/resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. Please refer to the limits specified by the crystal/resonator supplier. Data Sheet 95 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6.4 External Bus Timing The following parameters specify the behavior of the XE164 bus interface. Table 27 CLKOUT Reference Signal Parameter Symbol Limits Min. t5 t6 t7 t8 t9 CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time Unit Note / Test Condition Max. 40/25/12.51) CC ns CC 3 - ns CC 3 - ns CC - 3 ns CC - 3 ns 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fSYS = 25/40/80 MHz). For longer periods the relative deviation decreases (see PLL deviation formula). t9 t5 t6 t7 t8 CLKOUT MC_X_EBCCLKOUT Figure 21 CLKOUT Signal Timing Note: The term CLKOUT refers to the reference clock output signal which is generated by selecting fSYS as the source signal for the clock output signal EXTCLK on pin P2.8 and by enabling the high-speed clock driver on this pin. Data Sheet 96 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Variable Memory Cycles External bus cycles of the XE164 are executed in five consecutive cycle phases (AB, C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). The duration of the access phase can optionally be controlled by the external module using the READY handshake input. This table provides a summary of the phases and the ranges for their length. Table 28 Programmable Bus Cycle Phases (see timing diagrams) Bus Cycle Phase Parameter Valid Values Unit Address setup phase, the standard duration of this tpAB phase (1 ... 2 TCS) can be extended by 0 ... 3 TCS if the address window is changed 1 ... 2 (5) TCS Command delay phase tpC 0...3 TCS Write Data setup/MUX Tristate phase tpD 0...1 TCS Access phase tpE 1 ... 32 TCS Address/Write Data hold phase tpF 0...3 TCS Note: The bandwidth of a parameter (from minimum to maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described in additional notes (see standard timing). Timing values are listed in Table 29 and Table 30. The shaded parameters have been verified by characterization. They are not subject to production test. Data Sheet 97 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 29 External Bus Cycle Timing for Upper Voltage Range (Operating Conditions apply) Parameter Symbol Limits Min. Typ. Unit Note Max. Output valid delay for: RD, WR(L/H) t10 CC - 13 ns Output valid delay for: BHE, ALE t11 CC - 13 ns Output valid delay for: A23 ... A16, A15 ... A0 (on P0/P1) t12 CC - 14 ns Output valid delay for: A15 ... A0 (on P2/P10) t13 CC - 14 ns Output valid delay for: CS t14 CC - 13 ns Output valid delay for: t15 CC D15 ... D0 (write data, MUX-mode) - 14 ns Output valid delay for: D15 ... D0 (write data, DEMUXmode) t16 CC - 14 ns Output hold time for: RD, WR(L/H) t20 CC 0 8 ns Output hold time for: BHE, ALE t21 CC 0 8 ns Output hold time for: t23 CC A23 ... A16, A15 ... A0 (on P2/P10) 0 8 ns Output hold time for: CS t24 CC 0 8 ns Output hold time for: D15 ... D0 (write data) t25 CC 0 8 ns Input setup time for: READY, D15 ... D0 (read data) t30 SR 18 - ns Input hold time for: READY, D15 ... D0 (read data)1) t31 SR -4 - ns 1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. Data Sheet 98 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 30 External Bus Cycle Timing for Lower Voltage Range (Operating Conditions apply) Parameter Symbol Limits Min. Typ. Unit Note Max. Output valid delay for: RD, WR(L/H) t10 CC - 20 ns Output valid delay for: BHE, ALE t11 CC - 20 ns Output valid delay for: A23 ... A16, A15 ... A0 (on P0/P1) t12 CC - 22 ns Output valid delay for: A15 ... A0 (on P2/P10) t13 CC - 22 ns Output valid delay for: CS t14 CC - 20 ns Output valid delay for: t15 CC D15 ... D0 (write data, MUX-mode) - 21 ns Output valid delay for: D15 ... D0 (write data, DEMUXmode) t16 CC - 21 ns Output hold time for: RD, WR(L/H) t20 CC 0 10 ns Output hold time for: BHE, ALE t21 CC 0 10 ns Output hold time for: t23 CC A23 ... A16, A15 ... A0 (on P2/P10) 0 10 ns Output hold time for: CS t24 CC 0 10 ns Output hold time for: D15 ... D0 (write data) t25 CC 0 10 ns Input setup time for: READY, D15 ... D0 (read data) t30 SR 29 - ns Input hold time for: READY, D15 ... D0 (read data)1) t31 SR -6 - ns 1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. Data Sheet 99 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters tpAB tpC tpD tpE tpF CLKOUT t21 t11 ALE t11/ t14 t24 A23-A16, BHE, CSx High Address t20 t10 RD WR(L/H) t31 t13 AD15-AD0 (read) AD15-AD0 (write) t23 Low Address t30 Data In t13 t15 Low Address t25 Data Out MC_X_EBCMUX Figure 22 Data Sheet Multiplexed Bus Cycle 100 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters tpAB tpC tpD tpE tpF CLKOUT t21 t11 ALE t11/ t14 A23-A0, BHE, CSx t24 Address t20 t10 RD WR(L/H) t31 t30 D15-D0 (read) Data In t16 D15-D0 (write) t25 Data Out MC_X_EBCDEMUX Figure 23 Data Sheet Demultiplexed Bus Cycle 101 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Bus Cycle Control with the READY Input The duration of an external bus cycle can be controlled by the external circuit using the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. An asynchronous READY signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the additional synchronization stage. The minimum duration of an asynchronous READY signal for safe synchronization is one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the next bus cycle is controlled by READY, an active READY signal must be disabled before the first valid sample point in the next bus cycle. This sample point depends on the programmed phases of the next cycle. Data Sheet 102 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters tpD tpE tpRDY tpF CLKOUT t10 t20 RD, WR t31 t30 D15-D0 (read) Data In t25 D15-D0 (write) Data Out t31 t30 READY Synchronous Not Rdy t31 t30 READY t31 t30 READY Asynchron. t31 t30 Not Rdy READY MC_X_EBCREADY Figure 24 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point ("Not Rdy") a READY-controlled waitstate is inserted (tpRDY), sampling the READY input active at the indicated sampling point ("Ready") terminates the currently running bus cycle. Note the different sampling points for synchronous and asynchronous READY. This example uses one mandatory waitstate (see tpE) before the READY input value is used. Data Sheet 103 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6.5 Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 31 SSC Master/Slave Mode Timing for Upper Voltage Range (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Unit Note / Test Co ndition Min. Typ. Max. 0 - 1) ns 0.5 x - 3) ns Master Mode Timing Slave select output SELO active to first SCLKOUT transmit edge t1 CC Slave select output SELO inactive t2 CC after last SCLKOUT receive edge 2) tBIT t3 CC t4 SR -6 - 13 ns 31 - - ns t5 SR -7 - - ns Select input DX2 setup to first clock input DX1 transmit edge t10 SR 7 - - ns 4) Select input DX2 hold after last clock input DX1 receive edge t11 SR 5 - - ns 4) Data input DX0 setup time to clock input DX1 receive edge t12 SR 7 - - ns 4) Data input DX0 hold time from clock input DX1 receive edge t13 SR 5 - - ns 4) Data output DOUT valid time t14 CC 8 - 29 ns 4) Transmit data output valid time Receive data input setup time to SCLKOUT receive edge Data input DX0 hold time from SCLKOUT receive edge Slave Mode Timing 1) The maximum value further depends on the settings for the slave select output leading delay. 2) tSYS = 1/fSYS (= 12.5ns @ 80 MHz) 3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay. 4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 104 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Table 32 SSC Master/Slave Mode Timing for Lower Voltage Range (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Unit Note / Test Co ndition Min. Typ. Max. 0 - 1) ns 2) 0.5 x - 3) ns 2) Master Mode Timing Slave select output SELO active to first SCLKOUT transmit edge t1 CC Slave select output SELO inactive t2 CC after last SCLKOUT receive edge tBIT t3 CC t4 SR -13 - 16 ns 48 - - ns t5 SR -11 - - ns Select input DX2 setup to first clock input DX1 transmit edge t10 SR 12 - - ns 4) Select input DX2 hold after last clock input DX1 receive edge t11 SR 8 - - ns 4) Data input DX0 setup time to clock input DX1 receive edge t12 SR 12 - - ns 4) Data input DX0 hold time from clock input DX1 receive edge t13 SR 8 - - ns 4) Data output DOUT valid time t14 CC 11 - 44 ns 4) Transmit data output valid time Receive data input setup time to SCLKOUT receive edge Data input DX0 hold time from SCLKOUT receive edge Slave Mode Timing 1) The maximum value further depends on the settings for the slave select output leading delay. 2) tSYS = 1/fSYS (= 12.5 ns @ 80 MHz) 3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock output delay. 4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 105 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters Master Mode Timing t1 Select Output SELOx t2 Inactive Inactive Active Clock Output SCLKOUT Receive Edge First Transmit Edge Last Receive Edge Transmit Edge t3 t3 Data Output DOUT t4 Data Input DX0 t4 t5 Data valid t5 Data valid Slave Mode Timing t10 Select Input DX2 Clock Input DX1 t11 Inactive Inactive Active Receive Edge First Transmit Edge t12 Data Input DX0 t12 t13 Data valid t 14 Last Receive Edge Transmit Edge t 13 Data valid t14 Data Output DOUT Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge: with this clock edge, receive data at receive data input is latched . Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. USIC_SSC_TMGX.VSD Figure 25 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. Data Sheet 106 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters 4.6.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 33 JTAG Interface Timing Parameters (Operating Conditions apply) Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge Symbol t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR Values Min. Typ. Max. Unit Note / Test Condition 60 50 - ns - 16 - - ns - 16 - - ns - - - 8 ns - - - 8 ns - 6 - - ns - TDI/TMS hold after TCK rising edge t7 SR 6 - - ns - TDO valid after TCK falling edge1) t8 CC t8 CC t9 CC - - 30 ns CL = 50 pF 10 - - ns CL = 20 pF - - 30 ns CL = 50 pF t10 CC - - 30 ns CL = 50 pF TDO high imped. to valid from TCK falling edge1)2) TDO valid to high imped. from TCK falling edge1) 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 107 V2.1, 2008-08 XE164x XE166 Family Derivatives Electrical Parameters t1 0.9 VDDP 0.5 VDDP t2 t5 t3 0.1 VDDP t4 MC_JTAG_TCK Figure 26 Test Clock Timing (TCK) TCK t6 t7 t6 t7 TMS TDI t9 t8 t10 TDO MC_JTAG Figure 27 Data Sheet JTAG Timing 108 V2.1, 2008-08 XE164x XE166 Family Derivatives Package and Reliability 5 Package and Reliability In addition to the electrical parameters, the following specifcations ensure proper integration of the XE164 into the target system. 5.1 Packaging These parameters specify the packaging rather than the silicon. Table 34 Package Parameters (PG-LQFP-100-3) Parameter Symbol Limit Values Min. Unit Notes Max. Exposed Pad Dimension Ex x Ey - 6.2 x 6.2 mm - Power Dissipation PDISS RJA - 1.0 W - - 49 K/W No thermal via1) 37 K/W 4-layer, no pad2) 22 K/W 4-layer, pad3) Thermal resistance Junction-Ambient 1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) or a 4-layer board without thermal vias; exposed pad not soldered. 2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not soldered. 3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered to the board. Data Sheet 109 V2.1, 2008-08 XE164x XE166 Family Derivatives Package and Reliability Package Outlines Figure 28 PG-LQFP-100-3 (Plastic Green Thin Quad Flat Package) All dimensions in mm. You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page "Packages": http://www.infineon.com/packages Data Sheet 110 V2.1, 2008-08 XE164x XE166 Family Derivatives Package and Reliability 5.2 Thermal Considerations When operating the XE164 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends on the package and its integration into the target board. The "Thermal resistance RJA" quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 125 C. The difference between junction temperature and ambient temperature is determined by T = (PINT + PIOSTAT + PIODYN) x RJA The internal power consumption is defined as PINT = VDDP x IDDP (see Section 4.2.3). The static external power consumption caused by the output drivers is defined as PIOSTAT = ((VDDP-VOH) x IOH) + (VOL x IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: * * * * Reduce VDDP, if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 111 V2.1, 2008-08 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG