STM32F051xx ARM-based 32-bit MCU, 16 to 64-KB Flash, timers, ADC, DAC and communication interfaces, 2.0-3.6 V Datasheet production data Features F Core: ARM(R) 32-bit CortexTM-M0 CPU, frequency up to 48 MHz Memories - 16 to 64 Kbytes of Flash memory - 8 Kbytes of SRAM with HW parity checking CRC calculation unit Reset and power management - Voltage range: 2.0 V to 3.6 V - Power-on/Power down reset (POR/PDR) - Programmable voltage detector (PVD) - Low power modes: Sleep, Stop, Standby - VBAT supply for RTC and backup registers Clock management - 4 to 32 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 8 MHz RC with x6 PLL option - Internal 40 kHz RC oscillator Up to 55 fast I/Os - All mappable on external interrupt vectors - Up to 36 I/Os with 5 V tolerant capability 5-channel DMA controller 1 x 12-bit, 1.0 s ADC (up to 16 channels) - Conversion range: 0 to 3.6 V - Separate analog supply from 2.4 up to 3.6 One 12-bit D/A converter Two fast low-power analog comparators with programmable input and output Up to 18 capacitive sensing channels supporting touchkey, linear and rotary touch sensors Up to 11 timers - One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop - One 32-bit and one 16-bit timer, with up to 4 IC/OC, usable for IR control decoding January 2014 This is information on a product in full production. LQFP64 10x10 mm LQFP48 7x7 mm LQFP32 7x7 mm UFQFPN32 5x5 mm UFQFPN48 7x7 mm A UFBGA64 5x5 mm - One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop - Two 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control - One 16-bit timer with 1 IC/OC - Independent and system watchdog timers - SysTick timer: 24-bit downcounter - One 16-bit basic timer to drive the DAC Calendar RTC with alarm and periodic wakeup from Stop/Standby Communication interfaces - Up to 2 I2C interfaces; one supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus and wakeup from STOP - Up to two USARTs supporting master synchronous SPI and modem control; one with ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature - Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frame, 1 with I2S interface multiplexed HDMI CEC interface, wakeup on header reception Serial wire debug (SWD) 96-bit unique ID (R) All packages ECOPACK 2 Table 1. Device summary Reference STM32F051xx DocID022265 Rev 4 Part number STM32F051K4, STM32F051C4, STM32F051R4 STM32F051K6, STM32F051C6, STM32F051R6 STM32F051C8, STM32F051R8, STM32F051K8 1/115 www.st.com Contents STM32F051xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM(R) CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13 3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 2/115 3.5.1 3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 21 3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID022265 Rev 4 STM32F051xx Contents 3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Universal synchronous/asynchronous receiver transmitters (USART) . . 24 3.18 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 25 3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 47 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 47 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID022265 Rev 4 3/115 4 Contents 7 STM32F051xx 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.20 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 108 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4/115 DocID022265 Rev 4 STM32F051xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F051xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitive sensing GPIOs available on STM32F051xx devices . . . . . . . . . . . . . . . . . . . . 19 No. of capacitive sensing channels available on STM32F051xx devices. . . . . . . . . . . . . . 19 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F051xx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F051xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F051xx SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 37 Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 38 STM32F051xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 47 Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical and maximum current consumption from the VDD supply at VDD = 3.6 . . . . . . . . . 50 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 51 Typical and maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . 52 Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 53 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 55 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID022265 Rev 4 5/115 6 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. 6/115 STM32F051xx I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 96 LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 98 LQFP32 - 7 x 7mm 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . 100 UFBGA64 - 5 x 5 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 103 UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . 105 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DocID022265 Rev 4 STM32F051xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP64 64-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 UFBGA64 64-pin package ball-out (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LQFP48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 UFQFPN48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LQFP32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 UFQFPN32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM32F051xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 96 LQFP64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP48 - 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 98 LQFP48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP32 - 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 100 LQFP32 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UFBGA64 - 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . 104 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5) . . . . 106 UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LQFP64 PD max vs. TA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DocID022265 Rev 4 7/115 7 Introduction 1 STM32F051xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F051xx microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM CortexTM-M0 core, please refer to the CortexTM-M0 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html. 8/115 DocID022265 Rev 4 STM32F051xx 2 Description Description The STM32F051xx microcontrollers incorporate the high-performance ARM CortexTM-M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 64 Kbytes of Flash memory and 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs, two SPIs, one I2S, one HDMI CEC and up to two USARTs), one 12-bit ADC, one 12-bit DAC, up to six general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer. The STM32F051xx microcontrollers operate in the -40 to +85 C and -40 to +105 C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. The STM32F051xx microcontrollers include devices in six different packages ranging from 32 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F051xx peripherals proposed. These features make the STM32F051xx microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs. DocID022265 Rev 4 9/115 26 Description STM32F051xx Table 2. STM32F051xx family device features and peripheral counts Peripheral Flash (Kbytes) STM32F051Kx 16 32 STM32F051Cx 64 16 32 SRAM (Kbytes) Timers 64 Advanced control 1 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 1 (16-bit) 1 [1](2) 2 I C USART 1 (4) 1 1 [1](2) 32 (3) 1 (3) 2 1(4) 2 2 2 [1] (3) 1 2 1(4) 2 1 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.) GPIOs 25 (on LQFP32) 27 (on UFQFPN32) 39 55 Capacitive sensing channels 13 (on LQFP32) 14 (on UFQFPN32) 17 18 1 16 ext. + 3 int. 12-bit ADC (number of channels) Analog comparator 2 Max. CPU frequency 48 MHz Operating voltage Operating temperature Packages 2.0 to 3.6 V Ambient operating temperature: -40 C to 85 C / -40 C to 105 C Junction temperature: -40 C to 125 C LQFP32 UFQFPN32 LQFP48 UFQFPN48 1. The SPI1 interface can be used either in SPI mode or in I2S audio mode. 2. SPI2 is not present. 3. I2C2 is not present. 4. USART2 is not present. 10/115 64 1 [1](2) 2 [1] CEC 12-bit ADC (number of channels) 16 8 SPI [I2S](1) Comm. interfaces STM32F051Rx DocID022265 Rev 4 LQFP64 UFBGA64 STM32F051xx Description Figure 1. Block diagram %XVPDWUL[ &257(;0&38 I+&/. 0+] 19,& 2EO )ODVK LQWHUIDFH 9'' 6HULDO :LUH 'HEXJ )ODVK .% ELWV 65$0 FRQWUROOHU 6:&/. 6:',2 DV$) 65$0 .% 32:(5 92/75(* 9729 325 5HVHW ,QW 6833/< 683(59,6,21 3253'5 #9''$ 5&+60+] 5&+60+] *3'0$ FKDQQHOV #9''$ #9'' ;7$/26& 0+] 3// *3,2SRUW$ 3%>@ *3,2SRUW% 3&>@ *3,2SRUW& 3' *3,2SRUW' 3)>@ 3)>@ *3,2SRUW) JURXSVRI FKDQQHOV $QDORJ VZLWFKHV 7RXFK 6HQVLQJ &RQWUROOHU 6<1& ,:'* 3RZHU &RQWUROOHU &5& ;7$/N+] %DFNXS UHJ 026,6' 0,620&. 6&.&. 166:6DV$) $+% 026,0,62 6&.166 DV$) (;7,7 :.83 ::'* 63,,6 9%$7 WR9 26&B,1 3& 26&B287 3& 7$03(557& $/$50287 57&LQWHUIDFH 7,0(5 FKDQQHOV FRPSOFKDQQHOV %5.(75LQSXWDV$) 7,0(5 FK(75DV$) 7,0(5 FK(75DV$) 7,0(5 FKDQQHODV$) 7,0(5 FKDQQHOV FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) 7,0(5 FKDQQHO FRPSO%5.DV$) $3% $) 26&B,1 3) 26&B287 3) #96: 57& $+%GHFRGHU 3$>@ $+%3&/. $3%3&/. $'&&/. &(&&/. 86$57&/. +&/. )&/. 1567 9''$ 9'' 39' 5&/6 5(6(7 &/2&. &21752/ 9'' WR9 966 #9'' ,5B287DV$) '%*0&8 86$57 63, 86$57 5;7;&76576 &.DV$) 5;7;&76576 &.DV$) 6<6&)*,) ,1387 ,1387 287387 DV$) $'LQSXWV *3FRPSDUDWRU *3FRPSDUDWRU #9''$ 7HPS VHQVRU ELW $'& 9''$ 966$ ,& 6&/6'$60%$ P$IRU)0 DV$) ,& 6&/6'$ DV$) +'0,&(& &(& DV$) ,) 7,0(5 #9''$ ,) ELW '$& '$&B287DV$) #9''$ 06Y9 DocID022265 Rev 4 11/115 26 Functional overview STM32F051xx 3 Functional overview 3.1 ARM(R) CortexTM-M0 core with embedded Flash and SRAM The ARM CortexTM-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M0 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F0xx family has an embedded ARM core and is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 3.2 Memories The device has the following features: 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. The non-volatile memory is divided into two arrays: - 16 to 64 Kbytes of embedded Flash memory for programs and data - Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot in RAM selection disabled 3.3 Boot modes At startup, the boot pin and boot selector option bit are used to select one of three boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15 or PA9/PA10. 12/115 DocID022265 Rev 4 STM32F051xx 3.4 Functional overview Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Power management 3.5.1 Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VDDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC and DAC are used). The VDDA voltage level must be always greater or equal to the VDD voltage level and must be provided first. VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 3.5.2 Power supply supervisors The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.5.3 Voltage regulator The regulator has two operating modes and it is always enabled after reset. Main (MR) is used in normal operating mode (Run). Low power (LPR) can be used in Stop mode where the power demand is reduced. DocID022265 Rev 4 13/115 26 Functional overview STM32F051xx In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). 3.5.4 Low-power modes The STM32F051xx microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC alarm, COMPx, I2C1, USART1 or the CEC. The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for processing incoming data. If this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs. Note: 14/115 The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. DocID022265 Rev 4 STM32F051xx 3.6 Functional overview Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. Figure 2. Clock tree &,)4&#,+ TO &LASH PROGRAMMING INTERFACE (3) TO )# 393#,+ TO )3 ,3% -(Z (3) (3) 2# TO #%# (#,+ 0,,32# 0,,-5, 0,, X X X 37 (3) 0,,#,+ (3% !(" !(" PRESCALER 393#,+ #33 /3#?/54 /3#?). -(Z (3% /3# -(Z (3) (3) 2# /3#?). /3#?/54 ,3% /3# K(Z ,3% 24##,+ TO 24# !0" PRESCALER TO !(" BUS CORE MEMORY AND $-! TO CORTEX 3YSTEM TIMER &(#,+ #ORTEX FREE RUNNING CLOCK 0#,+ )F !0" PRESCALER X ELSE X !$# 0RESCALER 0#,+ 393#,+ (3) ,3% TO !0" PERIPHERALS TO 4)- TO !$# -(Z MAX TO 53!24 24#3%,;= ,3) ,3) 2# K(Z TO )7$' 0,,#,+ -#/ -AIN CLOCK OUTPUT (3) (3) (3% 393#,+ ,3) ,3% -#/ -36 DocID022265 Rev 4 15/115 26 Functional overview 3.7 STM32F051xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.8 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except TIM14), DAC and ADC. 3.9 Interrupts and events 3.9.1 Nested vectored interrupt controller (NVIC) The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M0) and 4 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 55 GPIOs can be connected to the 16 external interrupt lines. 16/115 DocID022265 Rev 4 STM32F051xx 3.10 Functional overview Analog to digital converter (ADC) The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 3. Temperature sensor calibration values Calibration value name 3.10.2 Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 C (5 C), VDDA= 3.3 V (10 mV) 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at a temperature of 110 C (5 C), VDDA= 3.3 V (10 mV) 0x1FFF F7C2 - 0x1FFF F7C3 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 4. Internal voltage reference calibration values Calibration value name VREFINT_CAL Description Memory address Raw data acquired at a temperature of 30 C (5 C), 0x1FFF F7BA - 0x1FFF F7BB VDDA= 3.3 V (10 mV) DocID022265 Rev 4 17/115 26 Functional overview 3.10.3 STM32F051xx VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.11 Digital-to-analog converter (DAC) The 12-bit buffered DAC channel can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This digital Interface supports the following features: Left or right data alignment in 12-bit mode Synchronized update capability DMA capability External triggers for conversion Five DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger outputs and the DAC interface is generating its own DMA requests. 3.12 Comparators (COMP) The device embeds two fast rail-to-rail low-power comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. The reference voltage can be one of the following: External I/O DAC output pins Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 24: Embedded internal reference voltage for the value and precision of the internal reference voltage. Both comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.13 Touch sensing controller (TSC) The STM32F051xx devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 18 capacitive sensing channels distributed over 6 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific 18/115 DocID022265 Rev 4 STM32F051xx Functional overview threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. Table 5. Capacitive sensing GPIOs available on STM32F051xx devices Group 1 2 3 Capacitive sensing signal name Pin name Capacitive sensing signal name Pin name TSC_G1_IO1 PA0 TSC_G4_IO1 PA9 TSC_G1_IO2 PA1 TSC_G4_IO2 PA10 TSC_G1_IO3 PA2 TSC_G4_IO3 PA11 TSC_G1_IO4 PA3 TSC_G4_IO4 PA12 TSC_G2_IO1 PA4 TSC_G5_IO1 PB3 TSC_G2_IO2 PA5 TSC_G5_IO2 PB4 TSC_G2_IO3 PA6 TSC_G5_IO3 PB6 TSC_G2_IO4 PA7 TSC_G5_IO4 PB7 TSC_G3_IO1 PC5 TSC_G6_IO1 PB11 TSC_G3_IO2 PB0 TSC_G6_IO2 PB12 TSC_G3_IO3 PB1 TSC_G6_IO3 PB13 TSC_G3_IO4 PB2 TSC_G6_IO4 PB14 Group 4 5 6 Table 6. No. of capacitive sensing channels available on STM32F051xx devices Number of capacitive sensing channels Analog I/O group STM32F051Rx STM32F051Cx STM32F051Kx (UFQFPN32) STM32F051Kx (LQFP32) G1 3 3 3 3 G2 3 3 3 3 G3 3 2 2 1 G4 3 3 3 3 G5 3 3 3 3 G6 3 3 0 0 Number of capacitive sensing channels 18 17 14 13 DocID022265 Rev 4 19/115 26 Functional overview 3.14 STM32F051xx Timers and watchdogs The STM32F051xx devices include up to six general-purpose timers, one basic timer and an advanced control timer. Table 7 compares the features of the advanced-control, general-purpose and basic timers. Table 7. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Advanced control TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2 32-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM3 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM14 16-bit Up Any integer between 1 and 65536 No 1 No TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 Yes TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 Yes TIM6 16-bit Up Any integer between 1 and 65536 Yes 0 No General purpose Basic 20/115 DocID022265 Rev 4 Capture/compare Complementary channels outputs STM32F051xx 3.14.1 Functional overview Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for: Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining. 3.14.2 General-purpose timers (TIM2..3, TIM14..17) There are six synchronizable general-purpose timers embedded in the STM32F051xx devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base. TIM2, TIM3 STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining. TIM2 and TIM3 both have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Their counters can be frozen in debug mode. TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output. Its counter can be frozen in debug mode. TIM15, TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single DocID022265 Rev 4 21/115 26 Functional overview STM32F051xx channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17. TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation. Their counters can be frozen in debug mode. 3.14.3 Basic timer TIM6 This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base. 3.14.4 Independent watchdog (IWDG) The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.14.5 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.14.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source (HCLK or HCLK/8) 3.15 Real-time clock (RTC) and backup registers The RTC and the 5 backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. 22/115 DocID022265 Rev 4 STM32F051xx Functional overview The RTC is an independent BCD timer/counter. Its main features are the following: Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. Automatically correction for 28, 29 (leap year), 30, and 31 day of the month. Programmable alarm with wake up from Stop and Standby mode capability. On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection. Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection. Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC clock sources can be: A 32.768 kHz external crystal A resonator or oscillator The internal low-power RC oscillator (typical frequency of 40 kHz) The high-speed external clock divided by 32 3.16 Inter-integrated circuit interfaces (I2C) Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s) and I2C1 supports also Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive. Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 8. Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1 also has a clock domain independent DocID022265 Rev 4 23/115 26 Functional overview STM32F051xx from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller. Refer to Table 9 for the differences between I2C1 and I2C2. Table 9. STM32F051xx I2C implementation I2C features(1) I2C1 I2C2 7-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X Independent clock X SMBus X Wakeup from STOP X 1. X = supported. 3.17 Universal synchronous/asynchronous receiver transmitters (USART) The device embeds up to two universal synchronous/asynchronous receiver transmitters (USART1 and USART2), which communicate at speeds of up to 6 Mbit/s. They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock domain independent from the CPU clock, allowing USART1 to wake up the MCU from Stop mode. The USART interfaces can be served by the DMA controller. Refer to Table 10 for the differences between USART1 and USART2. Table 10. STM32F051xx USART implementation USART modes/features(1) 24/115 USART1 USART2 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Smartcard mode X Single-wire half-duplex communication X DocID022265 Rev 4 X STM32F051xx Functional overview Table 10. STM32F051xx USART implementation (continued) USART modes/features(1) USART1 IrDA SIR ENDEC block X LIN mode X Dual clock domain and wakeup from Stop mode X Receiver timeout interrupt X Modbus communication X Auto baud rate detection X Driver Enable X USART2 X 1. X = supported. 3.18 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. One standard I2S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. Refer to Table 11 for the differences between SPI1 and SPI2. Table 11. STM32F051xx SPI/I2S implementation SPI features(1) SPI1 SPI2 Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X I2S mode X TI mode X X 1. X = supported. DocID022265 Rev 4 25/115 26 Functional overview 3.19 STM32F051xx High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception. 3.20 Serial wire debug port (SW-DP) An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU. 26/115 DocID022265 Rev 4 STM32F051xx Pinouts and pin descriptions 0# 0#/3#?). 0#/3#?/54 0&/3#?). 0&/3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 0! 0! ,1&0 0& 0& 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 633 6$$ 6"!4 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! 6$$ 633 Figure 3. LQFP64 64-pin package pinout (top view) 0! 0& 0& 4 Pinouts and pin descriptions -36 DocID022265 Rev 4 27/115 36 Pinouts and pin descriptions STM32F051xx Figure 4. UFBGA64 64-pin package ball-out (top view) $ 3& 26&B,1 3& 3% 3% 3% 3$ 3$ 3$ % 3& 26&B287 9%$7 3% %227 3' 3& 3& 3$ & 3) 26&B,1 3) 3% 3% 3& 3$ 3$ 3$ ' 3) 26&B287 3) 3% 966 966 3) 3$ 3& ( 1567 3& 3& 9'' 9'' 3) 3& 3& ) 966$ 3& 3$ 3$ 3% 3& 3% 3% * 3& 3$ 3$ 3$ 3% 3% 3% 3% + 9''$ 3$ 3$ 3$ 3& 3& 3% 3% 069 28/115 DocID022265 Rev 4 STM32F051xx Pinouts and pin descriptions 6"!4 0# 0#/3#?). 0#/3#?/54 0&/3#?). 0&/3#?/54 .234 633! 6$$! 0! 0! 0! 0" 0! 0" 0" 0" 0" 0" "//4 ,1&0 0& 0& 0! 0! 0! 0! 0! 0! 0" 0" 0" 0" 6$$ 0" 633 0" 0" 0" 0" 0! 0! 0! 0! 0! 0! 0" 6$$ 633 Figure 5. LQFP48 48-pin package pinout (top view) -36 6"!4 0! 0" 0! 0" 0" 0" 0" 0" "//4 0" 6$$ 633 Figure 6. UFQFPN48 48-pin package pinout (top view) 0& 0# 0#/3#?). 0#/3#?/54 0&/3#?). 0&/3#?/54 0! 0! 0! .234 0! 633! 6$$! 0! 0! 0! 0" 0" 0" 0" 8)4)31 6$$ 0" 633 0" 0" 0" 0" 0! 0! 0! 0! 0! 0! 0& 0! 069 DocID022265 Rev 4 29/115 36 Pinouts and pin descriptions STM32F051xx 0" 0! 0" 0" 0" 0" 633 "//4 Figure 7. LQFP32 32-pin package pinout (top view) 6$$ 0&/3#?). 0&/3#?/54 .234 6$$! 0! 0! 0! ,1&0 0! 0! 0! 0! 0! 0! 0! 6$$ 0" 633 0" 0! 0! 0! 0! 0! -36 0" "//4 0" 0" 0" 0" 0" 0! Figure 8. UFQFPN32 32-pin package pinout (top view) 633 633! 0! 0! 0! 0! 0! 0! 0! 6$$ 0! 0! 0! 0! 0! 0" 0" 0" 6$$ 0&/3#?). 0&/3#?/54 .234 6$$! 0! 0! 0! -36 30/115 DocID022265 Rev 4 STM32F051xx Pinouts and pin descriptions Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.3 V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Notes Pin functions Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 13. Pin definitions Pin functions LQFP48/UFQFPN48 LQFP32 UFQFPN32 1 B2 1 - - VBAT S I/O structure UFBGA64 Pin name (function after reset) Pin type LQFP64 Pin number Notes Alternate functions Additional functions Backup power supply - RTC_TAMP1, RTC_TS, RTC_OUT, WKUP2 2 A2 2 - - PC13 I/O TC (1)(2) 3 A1 3 - - PC14-OSC32_IN (PC14) I/O TC (1)(2) - OSC32_IN 4 B1 4 - - PC15-OSC32_OUT I/O (PC15) TC (1)(2) - OSC32_OUT 5 C1 5 2 2 PF0-OSC_IN (PF0) I/O FT - OSC_IN 6 D1 6 3 3 PF1-OSC_OUT (PF1) I/O FT - OSC_OUT DocID022265 Rev 4 31/115 36 Pinouts and pin descriptions STM32F051xx Table 13. Pin definitions (continued) Pin functions LQFP48/UFQFPN48 LQFP32 UFQFPN32 7 E1 7 4 4 NRST 8 E3 - - - PC0 I/O TTa EVENTOUT ADC_IN10 9 E2 - - - PC1 I/O TTa EVENTOUT ADC_IN11 10 F2 - - - PC2 I/O TTa EVENTOUT ADC_IN12 11 A2 - - - PC3 I/O TTa EVENTOUT ADC_IN13 12 F1 8 - 0 VSSA S Analog ground 13 H1 9 5 5 VDDA S Analog power supply 14 15 16 G2 H2 F3 10 11 12 6 7 8 6 7 8 PA0 PA1 PA2 I/O structure UFBGA64 Pin name (function after reset) Pin type LQFP64 Pin number Notes I/O RST I/O I/O I/O Alternate functions Additional functions Device reset input / internal reset output (active low) TTa USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1 ADC_IN0, COMP1_INM6, RTC_TAMP2, WKUP1 TTa USART2_RTS, TIM2_CH2, TSC_G1_IO2, EVENTOUT ADC_IN1, COMP1_INP TTa USART2_TX, TIM2_CH3, TIM15_CH1, COMP2_OUT, TSC_G1_IO3 ADC_IN2, COMP2_INM6 ADC_IN3, COMP2_INP 17 G3 13 9 9 PA3 I/O TTa USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4 18 C2 - - - PF4 I/O FT EVENTOUT - 19 D2 - - - PF5 I/O FT EVENTOUT - TTa SPI1_NSS, I2S1_WS, USART2_CK, TIM14_CH1, TSC_G2_IO1 ADC_IN4, COMP1_INM4, COMP2_INM4, DAC1_OUT TTa SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2 ADC_IN5, COMP1_INM5, COMP2_INM5 20 21 H3 F4 32/115 14 15 10 11 10 11 PA4 PA5 I/O I/O DocID022265 Rev 4 STM32F051xx Pinouts and pin descriptions Table 13. Pin definitions (continued) Pin functions 22 G4 16 12 12 PA6 I/O I/O structure Pin name (function after reset) Pin type UFQFPN32 LQFP32 LQFP48/UFQFPN48 UFBGA64 LQFP64 Pin number Notes Alternate functions Additional functions TTa SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT ADC_IN6 ADC_IN7 23 H4 17 13 13 PA7 I/O TTa SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT 24 H5 - - - PC4 I/O TTa EVENTOUT ADC_IN14 25 H6 - - - PC5 I/O TTa TSC_G3_IO1 ADC_IN15 TTa TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT ADC_IN8 TIM3_CH4, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3 ADC_IN9 TSC_G3_IO4 - FT I2C2_SCL, CEC, TIM2_CH3, TSC_SYNC - FT I2C2_SDA, TIM2_CH4, TSC_G6_IO1, EVENTOUT - 26 F5 18 14 14 PB0 I/O 27 G5 19 15 15 PB1 I/O TTa 28 G6 20 - 16 PB2 I/O FT 29 G7 21 - - PB10 I/O (3) 30 H7 22 - - PB11 I/O 31 D4 23 16 0 VSS S Ground 32 E4 24 17 17 VDD S Digital power supply DocID022265 Rev 4 33/115 36 Pinouts and pin descriptions STM32F051xx Table 13. Pin definitions (continued) Pin functions I/O structure Pin name (function after reset) Pin type UFQFPN32 LQFP32 LQFP48/UFQFPN48 UFBGA64 LQFP64 Pin number Notes Alternate functions Additional functions - 33 H8 25 - - PB12 I/O FT SPI2_NSS, TIM1_BKIN, TSC_G6_IO2, EVENTOUT 34 G8 26 - - PB13 I/O FT SPI2_SCK, TIM1_CH1N, TSC_G6_IO3 - FT SPI2_MISO, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4 - RTC_REFIN 35 F8 27 - - PB14 I/O 36 F7 28 - - PB15 I/O FT SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2 37 F6 - - - PC6 I/O FT TIM3_CH1 - 38 E7 - - - PC7 I/O FT TIM3_CH2 - 39 E8 - - - PC8 I/O FT TIM3_CH3 - 40 D8 - - - PC9 I/O FT TIM3_CH4 - FT USART1_CK, TIM1_CH1, EVENTOUT, MCO - FT USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1 - FT USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2 - FT USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT - 41 42 43 44 D7 C7 C6 C8 34/115 29 30 31 32 18 19 20 21 18 19 20 21 PA8 PA9 PA10 PA11 I/O I/O I/O I/O DocID022265 Rev 4 STM32F051xx Pinouts and pin descriptions Table 13. Pin definitions (continued) Pin functions I/O structure Pin name (function after reset) Pin type UFQFPN32 LQFP32 LQFP48/UFQFPN48 UFBGA64 LQFP64 Pin number Notes Alternate functions Additional functions USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT - IR_OUT, SWDIO - 45 B8 33 22 22 PA12 I/O FT 46 A8 34 23 23 PA13 (SWDIO) I/O FT 47 D6 35 - - PF6 I/O FTf I2C2_SCL - 48 E6 36 - - PF7 I/O FTf I2C2_SDA - 49 A7 37 24 24 PA14 (SWCLK) I/O FT USART2_TX, SWCLK - SPI1_NSS, I2S1_WS, USART2_RX, TIM2_CH1_ETR, EVENTOUT - (4) (4) 50 A6 38 25 25 PA15 I/O FT 51 B7 - - - PC10 I/O FT - 52 B6 - - - PC11 I/O FT - 53 C5 - - - PC12 I/O FT - 54 B5 - - - PD2 I/O FT TIM3_ETR - FT SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT - FT SPI1_MISO, I2S1_MCK, TIM3_CH1, TSC_G5_IO2, EVENTOUT - FT SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 - 55 56 57 A5 A4 C4 39 40 41 26 27 28 26 27 28 PB3 PB4 PB5 I/O I/O I/O DocID022265 Rev 4 35/115 36 Pinouts and pin descriptions STM32F051xx Table 13. Pin definitions (continued) Pin functions 58 D3 42 29 29 PB6 I/O I/O structure Pin name (function after reset) Pin type UFQFPN32 LQFP32 LQFP48/UFQFPN48 UFBGA64 LQFP64 Pin number Alternate functions Additional functions FTf I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3 - I2C1_SDA, USART1_RX, TIM17_CH1N, TSC_G5_IO4 - 59 C3 43 30 30 PB7 I/O FTf 60 B4 44 31 31 BOOT0 I B 61 B3 45 - 32 PB8 I/O Notes FTf Boot memory selection (4) FTf I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC - I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT - 62 A3 46 - - PB9 I/O 63 D5 47 32 0 VSS S Ground 64 E5 48 1 1 VDD S Digital power supply 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the main reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual. 3. On the LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the package, they are not forced to a defined level by hardware). 4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated. 36/115 DocID022265 Rev 4 Pin name AF0 PA0 AF1 AF2 AF3 USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 AF4 AF5 AF6 AF7 COMP1_OUT DocID022265 Rev 4 PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4 PA4 SPI1_NSS, I2S1_WS USART2_CK PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 PA8 MCO USART1_CK TIM1_CH1 EVENTOUT PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1 PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 COMP1_OUT PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 COMP2_OUT PA13 SWDIO IR_OUT PA14 SWCLK USART2_TX PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT TSC_G2_IO1 COMP2_OUT TIM14_CH1 TIM14_CH1 TIM16_CH1 EVENTOUT COMP1_OUT TIM17_CH1 EVENTOUT COMP2_OUT STM32F051xx Table 14. Alternate functions selected through GPIOA_AFR registers for port A 37/115 STM32F051xx Table 15. Alternate functions selected through GPIOB_AFR registers for port B Pin name AF0 AF1 AF2 AF3 PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 PB2 TSC_G3_IO4 PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1 PB12 SPI2_NSS EVENTOUT TIM1_BKIN TSC_G6_IO2 PB13 SPI2_SCK TIM1_CH1N TSC_G6_IO3 PB14 SPI2_MISO TIM15_CH1 TIM1_CH2N TSC_G6_IO4 PB15 SPI2_MOSI TIM15_CH2 TIM1_CH3N TIM15_CH1N 38/115 DocID022265 Rev 4 STM32F051xx 5 Memory mapping Memory mapping Figure 9. STM32F051xx memory map [)))))))) [)) $+% [ [( [( &RUWH[ 0,QWHUQDO 3HULSKHUDOV UHVHUYHG [& [)) $+% [ UHVHUYHG [$ [ [))))))) [))))& [)))) [ $3% UHVHUYHG 2SWLRQ%\WHV [ UHVHUYHG 6\VWHPPHPRU\ [ [)))(& $3% [ [ UHVHUYHG [ 3HULSKHUDOV [ )ODVKPHPRU\ [ 65$0 [ UHVHUYHG &2'( [ )ODVKV\VWHPPHPRU\ RU65$0GHSHQGLQJRQ %227FRQILJXUDWLRQ [ [ 5HVHUYHG 069 DocID022265 Rev 4 39/115 41 Memory mapping STM32F051xx Table 16. STM32F051xx peripheral register boundary addresses Bus AHB2 AHB1 APB 40/115 Boundary address Size Peripheral 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB Reserved 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 3 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH Interface 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0400 - 0x4002 0FFF 3 KB Reserved 0x4002 0000 - 0x4002 03FF 1 KB DMA 0x4001 8000 - 0x4001 FFFF 32 KB Reserved 0x4001 5C00 - 0x4001 7FFF 9 KB Reserved 0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU 0x4001 4C00 - 0x4001 57FF 3 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB Reserved 0x4001 2400 - 0x4001 27FF 1 KB ADC 0x4001 0800 - 0x4001 23FF 7 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP 0x4000 8000 - 0x4000 FFFF 32 KB Reserved DocID022265 Rev 4 STM32F051xx Memory mapping Table 16. STM32F051xx peripheral register boundary addresses (continued) Bus APB Boundary address Size Peripheral 0x4000 7C00 - 0x4000 7FFF 1 KB Reserved 0x4000 7800 - 0x4000 7BFF 1 KB CEC 0x4000 7400 - 0x4000 77FF 1 KB DAC 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 5C00 - 0x4000 6FFF 5 KB Reserved 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 4800 - 0x4000 53FF 3 KB Reserved 0x4000 4400 - 0x4000 47FF 1 KB USART2 0x4000 3C00 - 0x4000 43FF 2 KB Reserved 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB Reserved 0x4000 2000 - 0x4000 23FF 1 KB TIM14 0x4000 1400 - 0x4000 1FFF 3 KB Reserved 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0800 - 0x4000 0FFF 2 KB Reserved 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 DocID022265 Rev 4 41/115 41 Electrical characteristics STM32F051xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = VDDA = 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage -#5 PIN -#5 PIN & S) 6). -36 42/115 DocID022265 Rev 4 -36 STM32F051xx 6.1.6 Electrical characteristics Power supply scheme Figure 12. Power supply scheme 9%$7 %DFNXSFLUFXLWU\ /6(57& %DFNXSUHJLVWHUV 9 3RZHUVZLWFK 9'' 9&25( [9'' 5HJXODWRU 287 [Q) *3,2V ,1 [) /HYHOVKLIWHU 9'',2 ,2 ORJLF .HUQHOORJLF &38'LJLWDO 0HPRULHV [966 9''$ 9''$ Q) ) 95() 95() $'& '$& $QDORJ 5&V3// 966$ 06Y9 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DocID022265 Rev 4 43/115 94 Electrical characteristics 6.1.7 STM32F051xx Current consumption measurement Figure 13. Current consumption measurement scheme * %%@7#"5 6"!4 )$$ 6$$ )$$! 6$$! -36 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics, Table 18: Current characteristics, and Table 19: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 17. Voltage characteristics(1) Symbol Ratings Min Max Unit -0.3 4.0 V - 0.4 V Input voltage on FT and FTf pins VSS 0.3 VDDIOx + 4.0 V Input voltage on TTa pins VSS 0.3 4.0 V Input voltage on any other pin VSS 0.3 4.0 V Variations between different VDD power pins - 50 mV Variations between all the different ground pins - 50 mV VDDx-VSS External main supply voltage (including VDDA, VDD and VBAT) VDD-VDDA Allowed voltage difference for VDD > VDDA VIN(2) |VDDx| |VSSx VSS| VESD(HBM) Electrostatic discharge voltage (human body model) see Section 6.3.12: Electrical sensitivity characteristics 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 18: Current characteristics for the maximum allowed injected current values. 44/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 18. Current characteristics Symbol Ratings Max. Unit mA IVDD Total current into sum of all VDD power lines (source)(1) 120 IVSS (1) -120 Total current out of sum of all VSS ground lines (sink) IVDD(PIN) (1) Maximum current into each VDD power pin (source) 100 IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100 IIO(PIN) IIO(PIN) Output current sunk by any I/O and control pin 25 Output current source by any I/O and control pin Total output current sunk by sum of all IOs and control pins -25 (2) Total output current sourced by sum of all IOs and control pins(2) Injected current on FT, FTf and B pins IINJ(PIN)(3) Injected current on TC and RST pin (5) IINJ(PIN) 80 -80 -5/+0(4) 5 Injected current on TTa pins 5 Total injected current (sum of all I/O and control pins)(6) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the device. See note (2) below Table 55: ADC accuracy. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 19. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID022265 Rev 4 Value Unit -65 to +150 C 150 C 45/115 94 Electrical characteristics STM32F051xx 6.3 Operating conditions 6.3.1 General operating conditions Table 20. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 48 fPCLK Internal APB clock frequency 0 48 VDD Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.65 3.6 TC and RST I/O -0.3 VDDIOx+0.3 TTa I/O -0.3 VDDA+0.3 FT and FTf I/O -0.3 5.5(1) BOOT0 0 9.0 LQFP64 - 444 LQFP48 - 364 LQFP32 - 357 UFQFPN32 - 526 UFQFPN48 - 625 UFBGA64 - 308 -40 85 -40 105 VDDA VBAT VIN PD Analog operating voltage (ADC and DAC not used) Analog operating voltage (ADC and DAC used) Backup operating voltage I/O input voltage Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2) Maximum power dissipation Ambient temperature for the suffix 7 version Maximum power dissipation -40 105 Low power dissipation(3) -40 125 Suffix 6 version -40 105 Suffix 7 version -40 125 Junction temperature range Low power dissipation(3) MHz V V Ambient temperature for the suffix 6 version TA TJ Must have a potential equal to or higher than VDD Unit V V mW C C C 1. To sustain a voltage higher than VDDIOx+0.3 V, the internal pull-up/pull-down resistors must be disabled. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.2: Thermal characteristics). 46/115 DocID022265 Rev 4 STM32F051xx 6.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 21 are derived from tests performed under the ambient temperature condition summarized in Table 20. Table 21. Operating conditions at power-up / power-down Symbol Parameter tVDD tVDDA 6.3.3 Conditions Min Max VDD rise time rate 0 VDD fall time rate 20 VDDA rise time rate 0 VDDA fall time rate 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 22. Embedded reset and power control block characteristics Symbol VPOR/PDR(1) VPDRhyst tRSTTEMPO(4) Parameter Power on/power down reset threshold Conditions Min Typ Max Unit Falling edge(2) 1.80 1.88 1.96(3) V 1.84(3) 1.92 2.00 V - 40 - mV 1.50 2.50 4.50 ms Rising edge PDR hysteresis Reset temporization 1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector monitors only VDD. 2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 3. Data based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. Table 23. Programmable voltage detector characteristics Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 Conditions Min Typ Max Unit Rising edge 2.1 2.18 2.26 V Falling edge 2 2.08 2.16 V Rising edge 2.19 2.28 2.37 V Falling edge 2.09 2.18 2.27 V Rising edge 2.28 2.38 2.48 V Falling edge 2.18 2.28 2.38 V Rising edge 2.38 2.48 2.58 V Falling edge 2.28 2.38 2.48 V DocID022265 Rev 4 47/115 94 Electrical characteristics STM32F051xx Table 23. Programmable voltage detector characteristics (continued) Symbol Parameter Min Typ Max Unit Rising edge 2.47 2.58 2.69 V Falling edge 2.37 2.48 2.59 V Rising edge 2.57 2.68 2.79 V Falling edge 2.47 2.58 2.69 V Rising edge 2.66 2.78 2.9 V Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3 V Falling edge 2.66 2.78 2.9 V PVD hysteresis - 100 - mV PVD current consumption - 0.15 0.26(1) A VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 VPVD7 PVD threshold 7 VPVDhyst (1) IDD(PVD) Conditions 1. Guaranteed by design, not tested in production. 6.3.4 Embedded reference voltage The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 24. Embedded internal reference voltage Symbol Parameter VREFINT Internal reference voltage TS_vrefint (2) ADC sampling time when reading the internal reference voltage VREFINT Internal reference voltage spread over the temperature range TCoeff Conditions Min Typ Max Unit -40 C < TA < +105 C 1.16 1.2 1.25 V 1.16 1.2 1.24(1) V 17.1(3) - - s - - 10(3) mV - - 100(3) ppm/C -40 C < TA < +85 C VDDA = 3 V Temperature coefficient 1. Data based on characterization results, not tested in production. 2. The shortest sampling time can be determined in the application by multiple iterations. 3. Guaranteed by design, not tested in production. 48/115 DocID022265 Rev 4 STM32F051xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: All I/O pins are in analog input mode All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency: - 0 wait state and Prefetch OFF from 0 to 24 MHz - 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 25 to Table 28 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. DocID022265 Rev 4 49/115 94 Electrical characteristics STM32F051xx Table 25. Typical and maximum current consumption from the VDD supply at VDD = 3.6 All peripherals enabled Symbol Parameter Conditions HSE bypass, PLL on Supply current in Run mode, code executing from Flash HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off HSE bypass, PLL on IDD Supply current in Run mode, code executing from RAM HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off Supply current in Sleep mode, code executing from Flash or RAM HSE bypass, PLL on HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off fHCLK Max @ TA(1) Typ All peripherals disabled Max @ TA(1) Typ 25 C 85 C 105 C 48 MHz 22.0 22.8 22.8 23.8 32 MHz 15.0 15.5 15.5 24 MHz 12.2 13.2 8 MHz 4.4 1 MHz Unit 25 C 85 C 105 C 11.8 12.7 12.7 13.3 16.0 7.6 8.7 8.7 9.0 13.2 13.6 7.2 7.9 7.9 8.1 5.2 5.2 5.4 2.7 2.9 2.9 3.0 1.0 1.3 1.3 1.4 0.7 0.9 0.9 0.9 48 MHz 22.0 22.8 22.8 23.8 11.8 12.7 12.7 13.3 32 MHz 15.0 15.5 15.5 16.0 7.6 8.7 8.7 9.0 24 MHz 12.2 13.2 13.2 13.6 7.2 7.9 7.9 8.1 8 MHz 5.2 5.2 5.4 2.7 2.9 2.9 3.0 48 MHz 22.2 23.2(2) 23.2 24.4(2) 12.0 12.7(2) 12.7 13.3(2) 32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0 24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1 8 MHz 4.0 4.5 4.5 4.7 1.9 2.9 2.9 3.0 1 MHz 0.6 0.8 0.8 0.9 0.3 0.6 0.6 0.7 48 MHz 22.2 23.2 23.2 24.4 12.0 12.7 12.7 13.3 32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0 24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1 8 MHz 4.5 4.5 4.7 1.9 2.9 2.9 3.0 48 MHz 14.0 15.3(2) 15.3 16.0(2) 2.8 3.0(2) 3.0 3.2(2) 32 MHz 9.5 10.2 10.2 10.7 2.0 2.1 2.1 2.3 24 MHz 7.3 7.8 7.8 8.3 1.5 1.7 1.7 1.9 8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8 1 MHz 0.4 0.6 0.6 0.6 0.2 0.4 0.4 0.4 48 MHz 14.0 15.3 15.3 16.0 3.8 4.0 4.1 4.2 32 MHz 9.5 10.2 10.2 10.7 2.6 2.7 2.8 2.8 24 MHz 7.3 7.8 7.8 8.3 2.0 2.1 2.1 2.1 8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8 4.4 4.0 1. Data based on characterization results, not tested in production unless otherwise specified. 2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA). 50/115 DocID022265 Rev 4 mA STM32F051xx Electrical characteristics Table 26. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter Conditions (1) VDDA = 3.6 V Max @ TA(2) fHCLK Max @ TA(2) Typ 25 C IDDA Supply current in Run or Sleep mode, code executing from Flash or RAM HSE bypass, PLL on HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off Unit Typ 85 C 105 C 25 C 85 C 105 C 48 MHz 150 170(3) 178 182(3) 164 183(3) 195 198(3) 32 MHz 104 121 126 128 113 129 135 138 24 MHz 82 96 100 103 88 102 106 108 8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 48 MHz 220 240 248 252 244 263 275 278 32 MHz 174 191 196 198 193 209 215 218 24 MHz 152 167 173 174 168 183 190 192 8 MHz 72 79 82 83 83.5 91 94 95 A 1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, IDDA is independent from the frequency. 2. Data based on characterization results, not tested in production unless otherwise specified. 3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA). DocID022265 Rev 4 51/115 94 Electrical characteristics STM32F051xx Table 27. Typical and maximum current consumption in Stop and Standby modes Parameter IDD Supply current in Standby mode Supply current in Stop mode IDDA Supply current in Standby mode Supply current in Stop mode Supply current in Standby mode 2.0 V 2.4 V Regulator in run mode, all oscillators OFF 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 C 85 C 105 C 15 15.1 15.25 15.45 15.7 16 22(2) 48 64(2) Regulator in lowpower mode, all oscillators OFF 3.15 3.25 3.35 3.45 3.7 4 (2) 32 45(2) LSI ON and IWDG ON 0.8 0.95 1.05 1.2 1.35 1.5 - - - LSI OFF and IWDG OFF 0.65 0.75 0.85 0.95 1.1 1.3 2(2) 2.5 3(2) Regulator in run mode, all oscillators OFF 1.85 2 2.15 2.3 2.45 2.6 3.5(2) 3.5 4.5(2) Regulator in lowpower mode, all 1.85 oscillators OFF 2 2.15 2.3 2.45 2.6 3.5(2) 3.5 4.5(2) VDDA monitoring ON Supply current in Stop mode Conditions VDDA monitoring OFF Symbol Max(1) Typ @VDD (VDD = VDDA) A LSI ON and IWDG ON 2.25 2.5 2.65 2.85 3.05 3.3 - - - LSI OFF and IWDG OFF 1.75 1.9 2 2.15 2.3 2.5 3.5(2) 3.5 4.5(2) Regulator in run mode, all oscillators OFF 1.11 1.15 1.18 1.22 1.27 1.35 - - - Regulator in lowpower mode, all oscillators OFF 1.11 1.15 1.18 1.22 1.27 1.35 - - - LSI ON and IWDG ON 1.5 1.58 1.65 1.78 1.91 2.04 - - - LSI OFF and IWDG OFF 1 1.02 1.05 1.05 1.15 1.22 - - - 1. Data based on characterization results, not tested in production unless otherwise specified. 2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA). 52/115 Unit DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 28. Typical and maximum current consumption from the VBAT supply Max(1) RTC domain IDD_VBAT supply current = 3.6 V = 3.3 V = 2.7 V Conditions = 2.4 V Parameter = 1.8 V Symbol = 1.65 V Typ @ VBAT LSE & RTC ON; "Xtal mode": lower driving capability; LSEDRV[1:0] = '00' 0.41 0.43 0.53 0.58 0.71 0.80 LSE & RTC ON; "Xtal mode" higher driving capability; LSEDRV[1:0] = '11' 0.71 0.75 0.85 0.91 1.06 1.16 TA = 25 C 0.85 TA = TA = 85 C 105 C 1.1 Unit 1.5 A 1.25 1.55 2 1. Data based on characterization results, not tested in production. Typical current consumption The MCU is placed under the following conditions: VDD=VDDA=3.3 V All I/O pins are in analog input configuration The Flash access time is adjusted to fHCLK frequency: - 0 wait state and Prefetch OFF from 0 to 24 MHz - 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled, fPCLK = fHCLK PLL is used for frequencies greater than 8 MHz AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and 500 kHz respectively DocID022265 Rev 4 53/115 94 Electrical characteristics STM32F051xx Table 29. Typical current consumption in Run mode, code with data processing running from Flash Typ Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash IDDA 54/115 Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 48 MHz 23.3 11.5 36 MHz 17.6 9.0 32 MHz 15.9 8.0 24 MHz 12.4 7.5 16 MHz 8.5 5.2 8 MHz 4.5 3.0 4 MHz 2.8 1.9 2 MHz 1.7 1.3 1 MHz 1.3 1.0 500 kHz 1.0 0.9 48 MHz 158 158 36 MHz 120 120 32 MHz 108 108 24 MHz 83 83 16 MHz 60 60 8 MHz 2.43 2.43 4 MHz 2.43 2.43 2 MHz 2.43 2.43 1 MHz 2.43 2.43 500 kHz 2.43 2.43 DocID022265 Rev 4 Unit mA A STM32F051xx Electrical characteristics Table 30. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Peripherals Peripherals enabled disabled 48 MHz 13.9 2.98 36 MHz 10.55 2.84 32 MHz 9.6 2.6 24 MHz 7.23 2.09 16 MHz 5.01 1.58 8 MHz Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA fHCLK Supply current in Sleep mode from VDDA supply DocID022265 Rev 4 0.99 4 MHz 1.81 0.85 2 MHz 1.27 0.77 1 MHz 1.03 0.73 500 kHz 0.9 0.71 125 kHz 0.78 0.69 48 MHz 158 157 36 MHz 119 119 32 MHz 108 107 24 MHz 83 83 16 MHz 60 60 8 MHz 2.36 2.38 4 MHz 2.36 2.38 2 MHz 2.36 2.38 1 MHz 2.36 2.38 500 kHz 2.36 2.38 125 kHz 2.36 2.38 Unit mA A 55/115 94 Electrical characteristics STM32F051xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 32: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx f SW C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 56/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 31. Switching output I/O current consumption Symbol Parameter Conditions(1) VDDIOx = 3.3 V C =CINT VDDIOx = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS ISW I/O current consumption VDDIOx = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint VDDIOx = 2.4 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint I/O toggling frequency (fSW) Typ 4 MHz 0.07 8 MHz 0.15 16 MHz 0.31 24 MHz 0.53 48 MHz 0.92 4 MHz 0.18 8 MHz 0.37 16 MHz 0.76 24 MHz 1.39 48 MHz 2.188 4 MHz 0.32 8 MHz 0.64 16 MHz 1.25 24 MHz 2.23 48 MHz 4.442 4 MHz 0.49 8 MHz 0.94 16 MHz 2.38 24 MHz 3.99 4 MHz 0.64 8 MHz 1.25 16 MHz 3.24 24 MHz 5.02 4 MHz 0.81 8 MHz 1.7 16 MHz 3.67 4 MHz 0.66 8 MHz 1.43 16 MHz 2.45 24 MHz 4.97 Unit mA 1. CS = 7 pF (estimated value). DocID022265 Rev 4 57/115 94 Electrical characteristics STM32F051xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 32. The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled unless otherwise mentioned The given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on Ambient operating temperature and supply voltage conditions summarized in Table 17: Voltage characteristics The peripheral clock used is 48 MHz. 58/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 32. Peripheral current consumption Peripheral Typical consumption at 25 C Unit IDD IDDA ADC(1) 0.53 0.964 CEC 0.24 - 0.10 - 0.27 0.408 DBGMCU 0.18 - DMA 0.35 - GPIOA 0.48 - GPIOB 0.58 - GPIOC 0.12 - GPIOD 0.04 - GPIOF 0.06 - I2C1 0.43 - I2C2 0.42 - PWR 0.22 - SPI1/I2S1 0.63 - SPI2 0.53 - SYSCFG & COMP 0.28 See note (3) TIM1 1.01 - TIM2 1.00 - TIM3 0.78 - TIM6 0.32 - TIM14 0.45 - TIM15 0.66 - TIM16 0.57 - TIM17 0.59 - TSC 0.28 - USART1 1.07 - USART2 0.48 - WWDG 0.22 - CRC DAC (2) mA 1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high). 2. DAC channel 1 enabled by setting EN1 bit in DAC_CR. 3. COMP IDDA is specified as IDD(COMP) in Table 57: Comparator characteristics. DocID022265 Rev 4 59/115 94 Electrical characteristics 6.3.6 STM32F051xx Wakeup time from low-power mode The wakeup times given in Table 33 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture. The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. After wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz. The wakeup source from Sleep and Stop mode is an EXTI Line configured in event mode. The wakeup source from Standby mode is the WKUP1 pin (PA0). All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions except when explicitly mentioned Table 33. Low-power mode wakeup timings Typ @VDD Symbol Parameter Conditions Max Unit = 2.0 V = 2.4 V = 2.7 V tWUSTOP Wakeup from Stop mode Wakeup from tWUSTANDBY Standby mode tWUSLEEP 60/115 =3V = 3.3 V Regulator in run mode 4.20 4.20 4.20 4.20 4.20 5 Regulator in low power mode 8.05 7.05 6.60 6.27 6.05 9 s 60.35 55.60 Wakeup from Sleep mode 53.50 52.02 4 SYSCLK cycles DocID022265 Rev 4 50.96 - STM32F051xx 6.3.7 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 14: High-speed external clock source AC timing diagram. Table 34. High-speed external user clock characteristics Symbol Parameter(1) fHSE_ext User external clock source frequency VHSEH VHSEL Conditions Min Typ Max Unit 1 8 32 MHz OSC_IN input pin high level voltage 0.7 VDD - VDD OSC_IN input pin low level voltage VSS - 0.3 VDD 15 - - tw(HSEH) OSC_IN high or low time tw(HSEL) tr(HSE) tf(HSE) V ns OSC_IN rise or fall time - - 20 1. Guaranteed by design, not tested in production. Figure 14. High-speed external clock source AC timing diagram T7(3%( 6(3%( 6(3%, TR(3% TF(3% T7(3%, T 4(3% -36 DocID022265 Rev 4 61/115 94 Electrical characteristics STM32F051xx Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15. Table 35. Low-speed external user clock characteristics Parameter(1) Symbol Conditions fLSE_ext User external clock source frequency Min Typ Max Unit - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7 VDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDD 450 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) tr(LSE) tf(LSE) V ns OSC32_IN rise or fall time - - 50 1. Guaranteed by design, not tested in production. Figure 15. Low-speed external clock source AC timing diagram T7,3%( 6,3%( 6,3%, TR,3% TF,3% T7,3%, T 4,3% -36 62/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 36. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 36. HSE oscillator characteristics Symbol fOSC_IN Parameter Conditions(1) Min(2) Typ Max(2) Unit 4 8 32 MHz - 200 - k Oscillator frequency Feedback resistor RF (3) During startup IDD HSE current consumption gm tSU(HSE) Oscillator transconductance (4) Startup time - 8.5 VDD = 3.3 V, Rm = 30 , CL = 10 pF@8 MHz - 0.4 - VDD = 3.3 V, Rm = 45 , CL = 10 pF@8 MHz - 0.5 - VDD = 3.3 V, Rm = 30 , CL = 5 pF@32 MHz - 0.8 - VDD = 3.3 V, Rm = 30 , CL = 10 pF@32 MHz - 1 - VDD = 3.3 V, Rm = 30 , CL = 20 pF@32 MHz - 1.5 - Startup 10 - - mA/V VDD is stabilized - 2 - ms mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design, not tested in production. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DocID022265 Rev 4 63/115 94 Electrical characteristics STM32F051xx Figure 16. Typical application with an 8 MHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F(3% /3#?). -( Z RESONATOR #, 2%84 2& "IAS CONTROLLED GAIN /3#?/5 4 -36 1. REXT value depends on the crystal characteristics. 64/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 37. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol IDD gm Parameter LSE current consumption Oscillator transconductance tSU(LSE)(3) Startup time Conditions(1) Min(2) Typ Max(2) Unit LSEDRV[1:0]=00 lower driving capability - 0.5 0.9 LSEDRV[1:0]= 01 medium low driving capability - - 1 LSEDRV[1:0] = 10 medium high driving capability - - 1.3 LSEDRV[1:0]=11 higher driving capability - - 1.6 LSEDRV[1:0]=00 lower driving capability 5 - - LSEDRV[1:0]= 01 medium low driving capability 8 - - LSEDRV[1:0] = 10 medium high driving capability 15 - - LSEDRV[1:0]=11 higher driving capability 25 - - VDD is stabilized - 2 - A A/V s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 2. Guaranteed by design, not tested in production. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DocID022265 Rev 4 65/115 94 Electrical characteristics STM32F051xx Figure 17. Typical application with a 32.768 kHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F,3% /3#?). $RIVE PROGRAMMABLE AMPLIFIER K( Z RESONATOR #, /3#?/5 4 -36 Note: 66/115 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DocID022265 Rev 4 STM32F051xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI) RC oscillator Table 38. HSI oscillator characteristics(1) Symbol fHSI TRIM DuCy(HSI) ACCHSI Parameter Conditions Min Typ Max Unit Frequency - 8 - MHz HSI user trimming step - - 1(2) % Duty cycle (2) 45 Accuracy of the HSI oscillator (factory calibrated) - 55 (2) % % TA = -40 to 105 C -3.8(3) - 4.6(3) TA = -10 to 85 C -2.9(3) - 2.9(3) % TA = 0 to 70 C -1.3(3) - 2.2(3) % -1 - 1 % TA = 25 C tsu(HSI) HSI oscillator startup time 1(2) - 2(2) s IDDA(HSI) HSI oscillator power consumption - 80 100(2) A 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 18. HSI oscillator accuracy characterization results -!8 -). 4! ; #= -36 DocID022265 Rev 4 67/115 94 Electrical characteristics STM32F051xx High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 39. HSI14 oscillator characteristics(1) Symbol fHSI14 TRIM Parameter Conditions Min Typ - 14 Frequency HSI14 user-trimming step - DuCy(HSI14) Duty cycle 45 Accuracy of the HSI14 oscillator (factory calibrated) TA = -10 to 85 C TA = 25 C tsu(HSI14) IDDA(HSI14) HSI14 oscillator startup time MHz - 1 55 % (2) % (3) - 5.1 % -3.2(3) - 3.1(3) % -1.3 - (3) 2.2 % -1 - 1 % - (2) s 1 HSI14 oscillator power consumption (2) (3) (3) TA = 0 to 70 C Unit - (2) TA = -40 to 105 C -4.2 ACCHSI14 Max (2) - 100 2 150(2) A 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. Figure 19. HSI14 oscillator accuracy characterization results -!8 -). 4! ; #= -36 68/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Low-speed internal (LSI) RC oscillator Table 40. LSI oscillator characteristics(1) Symbol fLSI tsu(LSI) Parameter Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 s LSI oscillator power consumption - 0.75 1.2 A Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.9 PLL characteristics The parameters given in Table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 41. PLL characteristics Value Symbol fPLL_IN fPLL_OUT tLOCK JitterPLL Parameter Unit Min Typ Max 1(2) 8.0 24(2) MHz PLL input clock duty cycle 40 (2) - 60(2) % PLL multiplier output clock 16(2) - 48 MHz PLL lock time - - 200(2) s Cycle-to-cycle jitter - - 300(2) ps PLL input clock(1) 1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design, not tested in production. DocID022265 Rev 4 69/115 94 Electrical characteristics 6.3.10 STM32F051xx Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 42. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA-40 to +105 C 40 53.5 60 s Page (1 KB) erase time TA -40 to +105 C 20 - 40 ms tME Mass erase time TA -40 to +105 C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA 2 - 3.6 V Symbol tprog tERASE Vprog Parameter Conditions Programming voltage 1. Guaranteed by design, not tested in production. Table 43. Flash memory endurance and data retention Symbol NEND tRET Min(1) Unit TA = -40 to +105 C 10 kcycles 1 kcycle(2) at TA = 85 C 30 Parameter Endurance Data retention Conditions 1 kcycle (2) at TA = 105 C 10 (2) 20 10 kcycles at TA = 55 C Years 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 44. They are based on the EMS levels and classes defined in application note AN1709. 70/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 44. EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD 3.3 V, LQFP64, TA +25 C, Voltage limits to be applied on any I/O pin to fHCLK 48 MHz, induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, LQFP64, TA +25 C, fHCLK 48 MHz, conforming to IEC 61000-4-4 3B Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 45. EMI characteristics Symbol Parameter SEMI Conditions Monitored frequency band 0.1 to 30 MHz VDD 3.6 V, TA 25 C, 30 to 130 MHz LQFP64 package Peak level compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level DocID022265 Rev 4 Max vs. [fHSE/fHCLK] Unit 8/48 MHz -3 28 dBV 23 4 - 71/115 94 Electrical characteristics 6.3.12 STM32F051xx Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 46. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Electrostatic discharge TA +25 C, conforming voltage (human body model) to JESD22-A114 Electrostatic discharge VESD(CDM) voltage (charge device model) TA +25 C, conforming to ANSI/ESD STM5.3.1 Class Maximum value(1) 2 2000 Unit V II 500 1. Data based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 47. Electrical sensitivities Symbol LU 6.3.13 Parameter Static latch-up class Conditions TA +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. 72/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 A/+0 A range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 48. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 48. I/O current injection susceptibility Functional susceptibility Symbol IINJ 6.3.14 Description Unit Negative injection Positive injection Injected current on BOOT0 -0 NA Injected current on PA10, PA12, PB4, PB5, PB10, PB15 and PD2 pins with induced leakage current on adjacent pins less than -10 A -5 NA Injected current on all other FT and FTf pins -5 NA Injected current on PA6 and PC0 -0 +5 Injected current on all other TTa, TC and RST pins -5 +5 mA I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 20: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 49. I/O static characteristics Symbol VIL Parameter Low level input voltage Conditions Min Typ Max TC and TTa I/O - - 0.3 VDDIOx+0.07(1) FT and FTf I/O - - 0.475 VDDIOx-0.2(1) BOOT0 - - 0.3 VDDIOx-0.3(1) All I/Os except BOOT0 pin - - 0.3 VDDIOx DocID022265 Rev 4 Unit V 73/115 94 Electrical characteristics STM32F051xx Table 49. I/O static characteristics (continued) Symbol VIH Vhys Ilkg RPU Parameter High level input voltage Schmitt trigger hysteresis Input leakage current(2) Weak pull-up equivalent resistor (4) RPD Weak pull-down equivalent resistor(4) CIO I/O pin capacitance Conditions Min TC and TTa I/O 0.445 VDDIOx+0.398 FT and FTf I/O 0.5 VDDIOx+0.2(1) (1) (1) 0.2 VDDIOx+0.95 BOOT0 Typ Max - - - - - - V All I/Os except BOOT0 pin 0.7 VDDIOx - TC and TTa I/O - 200(1) - FT and FTf I/O - (1) 100 - BOOT0 - 300(1) - TC, FT and FTf I/O TTa in digital mode VSS VIN VDDIOx - - 0.1 TTa in digital mode VDDIOx VIN VDDA - - 1 TTa in analog mode VSS VIN VDDA - - 0.2 FT and FTf I/O (3) VDDIOx VIN 5 V - - 10 VIN VSS 25 40 55 k VIN VDDIOx 25 40 55 k - 5 - pF 1. Data based on design simulation only. Not tested in production. 2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 48: I/O current injection susceptibility. 3. To sustain a voltage higher than VDDIOx +0.3 V, the internal pull-up/pull-down resistors must be disabled. 4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 74/115 Unit DocID022265 Rev 4 mV A STM32F051xx Electrical characteristics All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 20 for standard I/Os, and in Figure 21 for 5 V tolerant I/Os. Figure 20. TC and TTa I/O input characteristics 9 9 ,1 ,2[ 9 ' ' 9 ,+PLQ 7HVWHGUDQJH QWV 77/VWDQGDUGUHTXLUHPHQW LUHPH UHTX GDUG VWDQ 6 &02 9 ,+PLQ [ 9 '',2 8QGHILQHGLQSXWUDQJH 9 ,2[ 9,/PD[ '' 9 ,2[ 9,/PD[ '' LUHPHQWV QGDUGUHTX &026VWD 77/VWDQGDUGUHTXLUHPHQW 7HVWHGUDQJH 9 9 '',2[ 069 Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics 9 9 ,1 [ 9 ',2 ' 9 ,+PLQ 7HVWHGUDQJH 77/VWDQGDUGUHTXLUHPHQW WV HPHQ UHTXLU DUG VWDQG 6 &02 8QGHILQHGLQSXWUDQJH 9 '',2[ 9 ,+PLQ [ 9 '',2 [ 9 ,/PD 9 ,2[ 9,/PD[ '' 77/VWDQGDUGUHTXLUHPHQW HQWV UGUHTXLUHP QGD &026VWD 7HVWHGUDQJH 9 9 '',2[ 069 DocID022265 Rev 4 75/115 94 Electrical characteristics STM32F051xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 18: Current characteristics). The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 18: Current characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or TC unless otherwise specified). Table 50. Output voltage characteristics(1) Symbol Parameter VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL Output low level voltage for an I/O pin VOH Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(3) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOLFM+ (4) Output low level voltage for an FTf I/O pin in FM+ mode Conditions Min Max CMOS port(2) |IIO| = 8 mA VDDIOx 2.7 V - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.3 - - 0.4 VDDIOx-0.4 - |IIO| = 20 mA VDDIOx 2.7 V - 0.4 V |IIO| = 10 mA - 0.4 V TTL port(2) |IIO| = 8 mA VDDIOx 2.7 V |IIO| = 20 mA VDDIOx 2.7 V |IIO| = 6 mA Unit V V V V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18: Current characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Data based on characterization results. Not tested in production. 4. Data based on design simulation only. Not tested in production. 76/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 51, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 51. I/O AC characteristics(1)(2) OSPEEDRy [1:0] value(1) Symbol Parameter Conditions Min Max Unit - 2 MHz - 125 - 125 - 10 - 25 - 25 CL = 30 pF, VDDIOx 2.7 V - 50 CL = 50 pF, VDDIOx 2.7 V - 30 CL = 50 pF, VDDIOx 2.7 V - 20 CL = 30 pF, VDDIOx 2.7 V - 5 CL = 50 pF, VDDIOx 2.7 V - 8 CL = 50 pF, VDDIOx 2.7 V - 12 CL = 30 pF, VDDIOx 2.7 V - 5 CL = 50 pF, VDDIOx 2.7 V - 8 CL = 50 pF, VDDIOx 2.7 V - 12 - 2 - 12 - 34 10 - fmax(IO)out Maximum frequency(3) x0 tf(IO)out Output fall time tr(IO)out Output rise time CL = 50 pF fmax(IO)out Maximum frequency(3) 01 tf(IO)out Output fall time tr(IO)out Output rise time fmax(IO)out Maximum 11 tf(IO)out tr(IO)out FM+ configuration (4) frequency(3) Output fall time Output rise time fmax(IO)out Maximum CL = 50 pF frequency(3) tf(IO)out Output fall time tr(IO)out Output rise time tEXTIpw Pulse width of external signals detected by the EXTI controller CL = 50 pF ns MHz ns MHz ns MHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design, not tested in production. 3. The maximum frequency is defined in Figure 22. 4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of FM+ I/O configuration. DocID022265 Rev 4 77/115 94 Electrical characteristics STM32F051xx Figure 22. I/O AC characteristics definition W I ,2 RXW W U ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WW U I 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\WKHVSHFLILHGFDSDFLWDQFH 069 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 52. NRST pin characteristics Symbol Parameter VIL(NRST) Min Typ Max NRST input low level voltage - - 0.3 VDD+0.07(1) VIH(NRST) NRST input high level voltage 0.445 VDD+0.398(1) - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV 25 40 55 k - - 100(1) ns 2.7 < VDD < 3.6 300(1) - - 2.0 < VDD < 3.6 500(1) - - RPU Weak pull-up equivalent resistor(2) VF(NRST) NRST input filtered pulse VNF(NRST) NRST input not filtered pulse Conditions VIN VSS 1. Data based on design simulation only. Not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 78/115 DocID022265 Rev 4 Unit V ns STM32F051xx Electrical characteristics Figure 23. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9 '' 1567 5 38 ,QWHUQDOUHVHW )LOWHU ) 069 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 52: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 6.3.16 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 53 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 20: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 53. ADC characteristics Symbol Parameter VDDA Analog supply voltage for ADC ON IDDA (ADC) Current consumption of the ADC(1) Conditions VDD = VDDA = 3.3 V Min Typ Max Unit 2.4 - 3.6 V - 0.9 - mA fADC ADC clock frequency 0.6 - 14 MHz fS(2) Sampling rate 0.05 - 1 MHz - - 823 kHz - - 17 1/fADC 0 - VDDA V - - 50 k fADC = 14 MHz fTRIG(2) External trigger frequency VAIN Conversion voltage range RAIN(2) External input impedance RADC(2) Sampling switch resistance - - 1 k CADC(2) Internal sample and hold capacitor - - 8 pF tCAL(2) Calibration time See Equation 1 and Table 54 for details fADC = 14 MHz DocID022265 Rev 4 5.9 s 83 1/fADC 79/115 94 Electrical characteristics STM32F051xx Table 53. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle ADC clock = HSI14 WLATENCY(2) tlatr(2) ADC_DR register write latency fADC = fPCLK/2 = 14 MHz 0.196 s fADC = fPCLK/2 5.5 1/fPCLK 0.219 s 10.5 1/fPCLK Trigger conversion latency fADC = fPCLK/4 = 12 MHz fADC = fPCLK/4 JitterADC fADC = fHSI14 = 14 MHz 0.188 - 0.259 s fADC = fHSI14 - 1 - 1/fHSI14 fADC = 14 MHz 0.107 - 17.1 s 1.5 - 239.5 1/fADC 0 0 1 s 1 - 18 s ADC jitter on trigger conversion tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) Unit fADC = 14 MHz 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 A on IDDA and 60 A on IDD should be taken into account. 2. Guaranteed by design, not tested in production. Equation 1: RAIN max formula TS R AIN ------------------------------------------------------------- - R ADC N+2 f ADC C ADC ln 2 The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 54. RAIN max for fADC = 14 MHz 80/115 Ts (cycles) tS (s) RAIN max (k)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 54. RAIN max for fADC = 14 MHz (continued) Ts (cycles) tS (s) RAIN max (k)(1) 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 55. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) 1.3 2 1 1.5 0.5 1.5 0.7 1 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 0.8 1.5 ET Total unadjusted error 3.3 4 EO Offset error 1.9 2.8 EG Gain error 2.8 3 ED Differential linearity error 0.7 1.3 EL Integral linearity error 1.2 1.7 ET Total unadjusted error 3.3 4 EO Offset error 1.9 2.8 EG Gain error 2.8 3 ED Differential linearity error 0.7 1.3 EL Integral linearity error 1.2 1.7 fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k VDDA = 3 V to 3.6 V TA = 25 C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k VDDA = 2.7 V to 3.6 V TA = 40 to 105 C fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k VDDA = 2.4 V to 3.6 V TA = 25 C Unit LSB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. DocID022265 Rev 4 81/115 94 Electrical characteristics STM32F051xx Figure 24. ADC accuracy characteristics %' %XAMPLE OF AN ACTUAL TRANSFER CURVE 4HE IDEAL TRANSFER CURVE %ND POINT CORRELATION LINE %4 %44OTAL 5NADJUSTED %RROR MAXIMUM DEVIATION BETWEEN THE ACTUAL AND THE IDEAL TRANSFER CURVES %//FFSET %RROR DEVIATION BETWEEN THE FIRST ACTUAL TRANSITION AND THE FIRST IDEAL ONE %''AIN %RROR DEVIATION BETWEEN THE LAST IDEAL TRANSITION AND THE LAST ACTUAL ONE %$$IFFERENTIAL ,INEARITY %RROR MAXIMUM DEVIATION BETWEEN ACTUAL STEPS AND THE IDEAL ONE %,)NTEGRAL ,INEARITY %RROR MAXIMUM DEVIATION BETWEEN ANY ACTUAL TRANSITION AND THE END POINT CORRELATION LINE %/ %, %$ ,3")$%!, 633! 6$$! -36 Figure 25. Typical connection diagram using the ADC 9 ''$ 6DPSOHDQGKROG$'& FRQ YHU WHU 97 5 $,1 9$,1 5 $'& $,1[ & SDU DVLWLF 97 ,/ $ ELW FRQ YHU WHU &$'& 069 1. Refer to Table 53: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 12: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 82/115 DocID022265 Rev 4 STM32F051xx 6.3.17 Electrical characteristics DAC electrical specifications Table 56. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage for DAC ON 2.4 - 3.6 V RLOAD(1) Resistive load with buffer ON 5 - - k Load is referred to ground RO(1) CLOAD(1) Impedance output with buffer OFF - - 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer ON 0.2 - - V DAC_OUT max(1) Higher DAC_OUT voltage with buffer ON - - VDDA - 0.2 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC_OUT max(1) Higher DAC_OUT voltage with buffer OFF - - VDDA - 1LSB V - - 380 A IDDA(1) DAC DC current consumption in quiescent mode(2) With no load, middle code (0x800) on the input - - 480 A With no load, worst code (0xF1C) on the input Differential non linearity Difference between two consecutive code-1LSB) - - 0.5 LSB Given for the DAC in 10-bit configuration - - 2 LSB Given for the DAC in 12-bit configuration - - 1 LSB Given for the DAC in 10-bit configuration - - 4 LSB Given for the DAC in 12-bit configuration - - 10 mV - - 3 LSB Given for the DAC in 10-bit at VDDA = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VDDA = 3.6 V - - 0.5 % DNL(3) INL(3) Offset(3) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VDDA/2) Gain error(3) Gain error DocID022265 Rev 4 It gives the maximum output excursion of the DAC. Given for the DAC in 12-bit configuration 83/115 94 Electrical characteristics STM32F051xx Table 56. DAC characteristics (continued) Symbol Min Typ Max Unit Settling time (full scale: for a 10-bit input code transition (3) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 1LSB - 3 4 s Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement - -67 -40 dB No RLOAD, CLOAD = 50 pF Update rate(3) Parameter Comments CLOAD 50 pF, RLOAD 5 k MS/s CLOAD 50 pF, RLOAD 5 k 1. Guaranteed by design, not tested in production. 2. The DAC is in "quiescent mode" when it keeps the value steady on the output so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Figure 26. 12-bit buffered / non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 84/115 DocID022265 Rev 4 STM32F051xx 6.3.18 Electrical characteristics Comparator characteristics Table 57. Comparator characteristics Symbol VDDA Parameter Conditions Min(1) Typ Max(1) Unit Analog supply voltage 2 - 3.6 VIN Comparator input voltage range 0 - VDDA VBG Scaler input voltage - 1.2 - VSC Scaler offset voltage - 5 10 mV tS_SC Scaler startup time from power down - - 0.1 ms tSTART Comparator startup time Startup time to reach propagation delay specification - - 60 s Ultra-low power mode - 2 4.5 Low power mode - 0.7 1.5 Medium power mode - 0.3 0.6 VDDA 2.7 V - 50 100 VDDA 2.7 V - 100 240 Ultra-low power mode - 2 7 Low power mode - 0.7 2.1 Medium power mode - 0.3 1.2 VDDA 2.7 V - 90 180 VDDA 2.7 V - 110 300 Propagation delay for 200 mV step with 100 mV overdrive High speed mode tD Propagation delay for full range step with 100 mV overdrive High speed mode V s ns s ns Voffset Comparator offset error - 4 10 mV dVoffset/dT Offset error temperature coefficient - 18 - V/C Ultra-low power mode - 1.2 1.5 Low power mode - 3 5 Medium power mode - 10 15 High speed mode - 75 100 IDD(COMP) COMP current consumption DocID022265 Rev 4 A 85/115 94 Electrical characteristics STM32F051xx Table 57. Comparator characteristics (continued) Symbol Parameter Min(1) Typ Max(1) Conditions No hysteresis (COMPxHYST[1:0]=00) Vhys Comparator hysteresis - 0 High speed mode Low hysteresis (COMPxHYST[1:0]=01) All other power modes 3 High speed mode Medium hysteresis (COMPxHYST[1:0]=10) All other power modes 7 High speed mode High hysteresis (COMPxHYST[1:0]=11) All other power modes 18 Unit 13 8 5 10 26 15 9 mV 19 49 31 19 40 1. Data based on characterization results, not tested in production. 6.3.19 Temperature sensor characteristics Table 58. TS characteristics Symbol Parameter TL(1) Typ Max Unit - 1 2 C Average slope 4.0 4.3 4.6 mV/C Voltage at 30 C (5 C)(2) 1.34 1.43 1.52 V 4 - 10 s 17.1 - - s VSENSE linearity with temperature (1) Avg_Slope V30 tSTART Min (1) TS_temp(1)(3) Startup time ADC sampling time when reading the temperature 1. Guaranteed by design, not tested in production. 2. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byteRefer to Table 3: Temperature sensor calibration values. 3. The shortest sampling time can be determined in the application by multiple iterations. 6.3.20 VBAT monitoring characteristics Table 59. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit k R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT (for 1 mV accuracy) 5 - - s Er(1) TS_vbat(1)(2) 1. Guaranteed by design, not tested in production. 2. The shortest sampling time can be determined in the application by multiple iterations. 86/115 DocID022265 Rev 4 STM32F051xx 6.3.21 Electrical characteristics Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60. TIMx(1) characteristics Symbol tres(TIM) Parameter Conditions Timer resolution time Min Max Unit 1 - tTIMxCLK 20.8 - ns 0 fTIMxCLK/2 MHz 0 24 MHz TIMx (except TIM2) - 16 TIM2 - 32 1 65536 tTIMxCLK 0.0208 1365 s - 65536 x 65536 tTIMxCLK - 89.48 s fTIMxCLK = 48 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 48 MHz fEXT ResTIM tCOUNTER tMAX_COUNT Timer resolution 16-bit counter clock period fTIMxCLK = 48 MHz Maximum possible count with 32-bit counter fTIMxCLK = 48 MHz bit 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17 timers. Table 61. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller's internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. DocID022265 Rev 4 87/115 94 Electrical characteristics STM32F051xx Table 62. WWDG min/max timeout value at 48 MHz (PCLK) 6.3.22 Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0853 5.4613 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 Unit ms Communication interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. The I2C characteristics are described in Table 63. Refer also to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 63. I2C characteristics(1) Standard Symbol Fast mode Fast mode + Parameter Unit Min Max Min Max Min Max 0 100 0 400 0 1000 KHz - 1.3 - 0.5 - s 0.6 - 0.26 - s fSCL SCL clock frequency tLOW Low period of the SCL clock 4.7 tHIGH High Period of the SCL clock 4 tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 ns tf Fall time of both SDA and SCL signals - 300 - 300 - 120 ns tHD;DAT Data hold time 0 - 0 - 0 - s tVD;DAT Data valid time - 3.45(2) - 0.9(2) - 0.45(2) s - 3.45(2) - 0.9(2) - 0.45(2) s tVD;ACK Data valid acknowledge time tSU;DAT Data setup time 250 - 100 - 50 - ns tHD;STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - s tSU;STA Set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - s tSU;STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - s Bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - s tBUF 88/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 63. I2C characteristics(1) (continued) Standard Symbol Fast mode Fast mode + Parameter Unit Min Max Min Max Min Max Cb Capacitive load for each bus line - 400 - 400 - 550 pF tSP Pulse width of spikes that are suppressed by the analog filter 0 50(3) 0 50(3) 0 50(3) ns 1. The I2C characteristics are the requirements from the I2C bus specification rev03. They are guaranteed by design when the I2Cx_TIMING register is correctly programmed (refer to reference manual). These characteristics are not tested in production. 2. The maximum tHD;DAT could be 3.45 s, 0.9 s and 0.45 s for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. 3. The minimum width of the spikes filtered by the analog filter is above tSP(max). Table 64. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered DocID022265 Rev 4 89/115 94 Electrical characteristics STM32F051xx Figure 27. I2C bus AC waveforms and measurement circuit 9''B,& 9''B,& 5S 5S 0&8 5V 6'$ ,&EXV 5V 6&/ UG 4%" U 46%"5 US UG U )%45" US DPOUJOVFE U -08 G4$- 4 U 7%%"5 U )*() 4$- DPOUJOVFE U )%%"5 UIDMPDL U #6' TUDMPDLDZDMF 4%" U 4645" U )%45" U 7%"$, U 41 U 46450 4$4S UIDMPDL 1 4 069 Legend: Rs: Series protection resistors. Rp: Pull-up resistors. VDD_I2C: I2C bus supply. SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 65 for SPI or in Table 66 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 20: General operating conditions. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 65. SPI characteristics(1) Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) 90/115 Parameter SPI clock frequency SPI clock rise and fall time Conditions Min Max Master mode - 18 Slave mode - 18 Capacitive load: C = 15 pF - 6 DocID022265 Rev 4 Unit MHz ns STM32F051xx Electrical characteristics Table 65. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Max tsu(NSS) NSS setup time Slave mode 4Tpclk - th(NSS) NSS hold time Slave mode 2Tpclk + 10 - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 Tpclk/2 -2 Tpclk/2 + 1 Master mode 4 - Slave mode 5 - Master mode 4 - Slave mode 5 - tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) Data input setup time th(MI) Data input hold time th(SI) ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk tdis(SO)(3) Data output disable time Slave mode 0 18 tv(SO) Data output valid time Slave mode (after enable edge) - 22.5 tv(MO) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 11.5 - Master mode (after enable edge) 2 - Slave mode 25 75 th(SO) Data output hold time th(MO) DuCy(SCK) SPI slave input clock duty cycle Unit ns % 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Figure 28. SPI timing diagram - slave mode and CPHA = 0 .33 INPUT TC3#+ TH.33 3#+ )NPUT T35.33 #0(! #0/, #0(! #0/, TW3#+( TW3#+, TV3/ TA3/ -)3/ /54 0 54 -3 " / 54 TH3/ ") 4 /54 TR3#+ TF3#+ TDIS3/ ,3" /54 TSU3) -/3) ) .054 - 3" ). " ) 4 ). ,3" ). TH3) AIC DocID022265 Rev 4 91/115 94 Electrical characteristics STM32F051xx Figure 29. SPI timing diagram - slave mode and CPHA = 1 .33 INPUT 3#+ )NPUT T35.33 #0(! #0/, TC3#+ TH.33 TW3#,( TW3#,, #0(! #0/, TV3/ TA3/ -)3/ /54 0 54 TH3/ -3 " / 54 TSU3) -/3) ) .054 TR3#, TF3#, ") 4 /54 TDIS3/ ,3" /54 TH3) " ) 4 ). - 3" ). ,3" ). AI 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 30. SPI timing diagram - master mode (IGH .33 INPUT 3#+ /UTPUT #0(! #0/, 3#+ /UTPUT TC3#+ #0(! #0/, #0(! #0/, #0(! #0/, TSU-) -)3/ ).0 54 TW3#+( TW3#+, -3 "). TR3#+ TF3#+ ") 4 ). ,3" ). TH-) -/3) /54054 - 3" /54 TV-/ " ) 4 /54 ,3" /54 TH-/ AI6 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 92/115 DocID022265 Rev 4 STM32F051xx Electrical characteristics Table 66. I2S characteristics(1) Symbol fCK 1/tc(CK) Parameter 2 I S clock frequency I2S clock rise time tr(CK) Conditions Min Max 1.597 1.601 Slave mode 0 6.5 Capacitive load CL = 15 pF - 10 - 12 306 - 312 - Master mode (data: 16 bits, Audio frequency = 48 kHz) 2 I S clock fall time tf(CK) Master fPCLK= 16 MHz, audio frequency = 48 kHz tw(CKH) I2S clock high time tw(CKL) I2S clock low time tv(WS) WS valid time Master mode 2 - th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 7 - th(WS) WS hold time Slave mode 0 - I2S slave input clock duty cycle Slave mode 25 75 tsu(SD_MR) Data input setup time Master receiver 6 - tsu(SD_SR) Data input setup time Slave receiver 2 - Master receiver 4 - Slave receiver 0.5 - - 20 13 - - 4 0 - DuCy(SCK) th(SD_MR) (2) th(SD_SR)(2) Data input hold time tv(SD_ST)(2) Data output valid time th(SD_ST) Data output hold time tv(SD_MT) (2) th(SD_MT) Data output valid time Data output hold time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) Unit MHz ns % ns 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns. DocID022265 Rev 4 93/115 94 Electrical characteristics STM32F051xx Figure 31. I2S slave timing diagram (Philips protocol) #+ )NPUT TC#+ #0/, #0/, TW#+( TH73 TW#+, 73 INPUT TV3$?34 TSU73 3$TRANSMIT ,3" TRANSMIT -3" TRANSMIT TSU3$?32 ,3" RECEIVE 3$RECEIVE "ITN TRANSMIT TH3$?34 ,3" TRANSMIT TH3$?32 -3" RECEIVE "ITN RECEIVE ,3" RECEIVE AIB 1. Measurement points are done at CMOS levels: 0.3 x VDDIOx and 0.7 x VDDIOx. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 32. I2S master timing diagram (Philips protocol) TF#+ TR#+ #+ OUTPUT TC#+ #0/, TW#+( #0/, TV73 TH73 TW#+, 73 OUTPUT TV3$?-4 3$TRANSMIT ,3" TRANSMIT -3" TRANSMIT ,3" RECEIVE ,3" TRANSMIT TH3$?-2 TSU3$?-2 3$RECEIVE "ITN TRANSMIT TH3$?-4 -3" RECEIVE "ITN RECEIVE ,3" RECEIVE AIB 1. Data based on characterization results, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 94/115 DocID022265 Rev 4 STM32F051xx Package characteristics 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. DocID022265 Rev 4 95/115 110 Package characteristics STM32F051xx Figure 33. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline ! C ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% ! CCC # + , $ , $ $ 0). )$%.4)&)#!4)/. % % % B E 7?-%?6 1. Drawing is not to scale. Table 67. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D. - 7.500 - - - - 96/115 DocID022265 Rev 4 STM32F051xx Package characteristics Table 67. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e - 0.500 - - 0.0197 - k 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 34. LQFP64 recommended footprint AIC 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022265 Rev 4 97/115 110 Package characteristics STM32F051xx Figure 35. LQFP48 - 7 x 7 mm, 48 pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. % % % B E "?-%?6 1. Drawing is not to scale. Table 68. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 98/115 DocID022265 Rev 4 STM32F051xx Package characteristics Table 68. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 36. LQFP48 recommended footprint AID 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022265 Rev 4 99/115 110 Package characteristics STM32F051xx Figure 37. LQFP32 - 7 x 7mm 32-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC '!5'% 0,!.% # + $ ! , $ , $ 0). )$%.4)&)#!4)/. % % % B E 7@.&@7 1. Drawing is not to scale. Table 69. LQFP32 - 7 x 7mm 32-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol 100/115 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 DocID022265 Rev 4 STM32F051xx Package characteristics Table 69. LQFP32 - 7 x 7mm 32-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38. LQFP32 recommended footprint 6?&0?6 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022265 Rev 4 101/115 110 Package characteristics STM32F051xx Figure 39. UFBGA64 - 5 x 5 mm, 0.5 mm pitch, package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < + %277209,(: E EDOOV HHH 0 = < ; III 0 = 1. Drawing is not to scale. 102/115 DocID022265 Rev 4 7239,(: 5EB0(B9 STM32F051xx Package characteristics Table 70. UFBGA64 - 5 x 5 mm, 0.5 mm pitch, package mechanical data(1) inches(2) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Preliminary data. 2. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022265 Rev 4 103/115 110 Package characteristics STM32F051xx Figure 40. UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU ( 5W\S 'HWDLO= = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 104/115 DocID022265 Rev 4 STM32F051xx Package characteristics Table 71. UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41. UFQFPN48 recommended footprint !"?&0?6 1. Dimensions are in millimeters. DocID022265 Rev 4 105/115 110 Package characteristics STM32F051xx Figure 42. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5) !"?-%?6 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must be connected. It is referred to as Pin 0 in Table 13: Pin definitions. 106/115 DocID022265 Rev 4 STM32F051xx Package characteristics Table 72. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0.020 0.050 0 0.0008 0.0020 A3 - 0.152 - - 0.006 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D2 - 3.500 - - 0.1378 - E 4.900 5.000 5.100 0.1929 0.1969 0.2008 E2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - L 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.0800 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 43. UFQFPN32 recommended footprint $%B)3B9 1. Drawing is not to scale. 2. Dimensions are in millimeters. DocID022265 Rev 4 107/115 110 Package characteristics 7.2 STM32F051xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 20: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDDIOx - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 73. Package thermal characteristics Symbol JA 7.2.1 Parameter Value Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm 55 Thermal resistance junction-ambient LQFP32 - 7 x 7 mm 56 Thermal resistance junction-ambient UFBGA64 - 5 x 5 mm 65 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm 32 Thermal resistance junction-ambient UFQFPN32 - 5 x 5 mm 38 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. 108/115 DocID022265 Rev 4 STM32F051xx Package characteristics As applications do not commonly use the STM32F0xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Using the values obtained in Table 73 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 82 C + (45 C/W x 447 mW) = 82 C + 20.115 C = 102.115 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C) see Table 20: General operating conditions. In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Part numbering). Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (45C/W x 447 mW) = 105-20.115 = 84.885 C Suffix 7: TAmax = TJmax - (45C/W x 447 mW) = 125-20.115 = 104.885 C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 100 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW DocID022265 Rev 4 109/115 110 Package characteristics STM32F051xx Using the values obtained in Table 73 TJmax is calculated as follows: - For LQFP64, 45 C/W TJmax = 100 C + (45 C/W x 134 mW) = 100 C + 6.03 C = 106.03 C This is above the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 44 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. Figure 44. LQFP64 PD max vs. TA 3' P: 6XIIL[ 6XIIL[ 7$ & 110/115 DocID022265 Rev 4 06Y9 STM32F051xx 8 Part numbering Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 74. Ordering information scheme Example: STM32 F 051 R 8 T 6 x Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 051 = STM32F051xx Pin count K = 32 pins C = 48 pins R = 64 pins Code size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory Package H = UFBGA T = LQFP U = UFQFPN Temperature range 6 = -40 C to +85 C 7 = -40 C to +105 C Options xxx = programmed parts TR = tape and reel DocID022265 Rev 4 111/115 111 Revision history 9 STM32F051xx Revision history Table 75. Document revision history Date Revision 05-Apr-2012 1 Initial release 2 Updated Table 2: STM32F051xx family device features and peripheral counts for 1 SPI and 1 I2C in 32-pin package Corrected Group 3 pin order in Table 5: Capacitive sensing GPIOs available on STM32F051xx devices. Updated current consumptionTable 25 to Table 28. Updated Table 39: HSI14 oscillator characteristics 3 Features reorganized and Section Figure 1.: Block diagram structure changed. Added LQFP32 package. Updated Section 3.4: Cyclic redundancy check calculation unit (CRC). Modified number of priority levels in Section 3.9.1: Nested vectored interrupt controller (NVIC). Added note 3. for PB2 and PB8, changed TIM2_CH_ETR into TIM2_CH1_ETR in Table 13: Pin definitions and Table 14: Alternate functions selected through GPIOA_AFR registers for port A. Added Table 15: Alternate functions selected through GPIOB_AFR registers for port B. Updated IVDD, IVSS, and IINJ(PIN) in Table 18: Current characteristics. Updated ACCHSI in Table 38: HSI oscillator characteristics and Table 39: HSI14 oscillator characteristics. Updated Table 48: I/O current injection susceptibility. Added BOOT0 input low and high level voltage in Table 49: I/O static characteristics. Modified number of pins in VOL and VOH description, and changed condition for VOLFM+ in Table 50: Output voltage characteristics. Changed VDD to VDDA in Figure 37: Typical connection diagram using the ADC. Updated Ts_temp in Table 58: TS characteristics. Updated Figure 27: I2C bus AC waveforms and measurement circuit. 25-Apr-2012 23-Jul-2012 112/115 Changes DocID022265 Rev 4 STM32F051xx Revision history Table 75. Document revision history (continued) Date 13-Jan-2014 Revision 4 Changes Modified datasheet title. Added packages UFQFPN48 and UFBGA64. Replaced "backup domain with "RTC domain" throughout the document. Changed SRAM value from "4 to 8 Kbytes" to "8 Kbytes" Replaced IWWDG with IWDG in Figure 1: Block diagram. Added inputs LSI and LSE to the multiplexer in Figure 2: Clock tree. Added feature "Reference clock detection" in Section 3.15: Real-time clock (RTC) and backup registers. Modified junction temperature in Table 2: STM32F051xx family device features and peripheral counts. Renamed Table 4: Internal voltage reference calibration values. Replaced VDD with VDDA and VRERINT with VREFINT in Table 24: Embedded internal reference voltage. Rephrased introduction of Section 3.13: Touch sensing controller (TSC). Rephrased Section 3.5.3: Voltage regulator. Added sentence "If this is used when the voltage regulator is put in low power mode..." under "Stop mode" in Section 3.5.4: Low-power modes. Removed sentence "The internal voltage reference is also connected to ADC_IN17 input channel of the ADC." in Section 3.12: Comparators (COMP). Removed feature "Periodic wakeup from Stop/Standby" in Section 3.15: Real-time clock (RTC) and backup registers. Replaced IDD with IDDA in Table 38: HSI oscillator characteristics, Table 39: HSI14 oscillator characteristics and Table 40: LSI oscillator characteristics. Moved section "Wakeup time from low-power mode" to Section 6.3.6 and rephrased the section. Added lines D2 and E2 in Table 71: UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package mechanical data. Added "The peripheral clock used is 48 MHz." in Section Onchip peripheral current consumption. DocID022265 Rev 4 113/115 114 Revision history STM32F051xx Table 75. Document revision history (continued) Date 13-Jan-2014 114/115 Revision Changes 4 (continued) Added "Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection" in Section Functional susceptibility to I/O current injection. Replaced reference "JESD22-C101" with "ANSI/ESD STM5.3.1" in Table 46: ESD absolute maximum ratings. Merged Table 27: Typical and maximum VDD consumption in Stop and Standby modes and Table 28: Typical and maximum VDDA consumption in Stop and Standby modes into Table 27: Typical and maximum current consumption in Stop and Standby modes. Updated: - Table 3: Temperature sensor calibration values - Table 4: Internal voltage reference calibration values - Table 18: Current characteristics - Table 20: General operating conditions - Table 26: Typical and maximum current consumption from the VDDA supply - Table 33: Low-power mode wakeup timings - Table 48: I/O current injection susceptibility - Table 49: I/O static characteristics - Table 50: Output voltage characteristics - Table 52: NRST pin characteristics - Table 63: I2C characteristics - Figure 12: Power supply scheme - Figure 20: TC and TTa I/O input characteristics - Figure 21: Five volt tolerant (FT and FTf) I/O input characteristics - Figure 22: I/O AC characteristics definition - Figure 27: I2C bus AC waveforms and measurement circuit - Figure 25: Typical connection diagram using the ADC - Figure 33: LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline - Figure 34: LQFP64 recommended footprint - Figure 35: LQFP48 - 7 x 7 mm, 48 pin low-profile quad flat package outline - Figure 36: LQFP48 recommended footprint - Figure 37: LQFP32 - 7 x 7mm 32-pin low-profile quad flat package outline - Figure 38: LQFP32 recommended footprint - Figure 40: UFQFPN48 - 7 x 7 mm, 0.5 mm pitch, package outline DocID022265 Rev 4 STM32F051xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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