TS8308500CG - Atmel Corporation

Product Specification

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MAIN FEATURES

! 8-bit resolution.

! 500 Msps (min) sampling rate.

! 1.3 GHz full power input bandwidth.

! Band Flatness: TBD

! Input VSWR (packaged device): TBD

! SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc

@ FS = 500 Msps, FIN = 20 MHz :

! SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc

@ FS = 500 Msps, FIN = 250 MHz :

! SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc

@ FS = 500 Msps, FIN = 500 MHz (-3 dB FS)

! 2-tone IMD : TBD (199.5 MHz, 200. 5 MHz) @ 500 MSPS.

! DNL = ± 0.3 LSB INL = ± 0.7 LSB.

! Low Bit Error Rate (10-13 ) @ 500 Msps, Tj = 90°C

! Power consumption : 3.8 W @ Tj = 70°C Typical

! 500 mVpp differential or singl e-ended anal og inputs.

! Differential or single-ended 50Ω ECL compatible clock inputs.

! ECL or LVDS/HSTL output compatibil ity.

! ADC gain adjust.

! Data ready output with asynchronous reset.

! Gray or Binary sel ectable output data ; NRZ output mode.

APPLICATIONS

! Digital Sampling Oscilloscopes.

! Satellite receiver.

! Electronic countermeasures / Electronic warfare.

! Direct RF down–conversion.

SCREENING

! Atmel-Grenoble st andard screening level

! Temperature range: up to 0°C < Tc ; Tj < +90°C

DESCRIPTION

The TS8308500 is a monolithic 8–bit analog–to–digital converter, designed for

digitizi ng wide bandwidth analog si gnals at very high sampling rates of up to 500

Msps.

The TS8308500 is using an innovative architecture, includi ng an on chi p Sample

and Hold (S/H), and is fabricated with an advanced high speed bipolar process.

The on–chip S/H has a 1.3 GHz full power input bandwidth, providing excell ent

dynamic perf orm ance in unders am pling appl ications (High IF digitizing).

G Suffix : CBGA 72

Ceramic Ball Grid Array

With decoupling R and C on the package

ADC 8-bit 500 Msps

TS8308500

1/ Evaluation board :

TSEV8308500

Detailed specification on request.

2/ Demultiplexer : parallel 8-bit 2 Gsps

TS81102G0 : companion device available

January 2002

2TS8308500

Preliminary Spec ificat ion

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TABLE OF CONTENTS

1. SIMPLIFIED BLOCK DIAGRAM....................................................................................................................................3

2. FUNCTIONAL DESCRIPTION ........................................................................................................................................3

3. SPECIFICATIONS..............................................................................................................................................................4

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).................................................................................................................4

3.2. RECOMMENDED CONDITIONS OF USE..........................................................................................................................................4

3.3. ELECTRICAL OPERATING CHARACTERISTICS..............................................................................................................................5

3.4. TIMING DIAGRAMS ...........................................................................................................................................................................9

3.5. EXPLANATION OF TEST LEVELS ...................................................................................................................................................10

3.6. FUNCTIONS DESCRIPTION............................................................................................................................................................10

3.7. DIGITAL OUTPUT CODING.............................................................................................................................................................10

4. PACKAGE DESCRIPTION. ............................................................................................................................................11

4.1. TS8308500 PAD DESCRIPTION......................................................................................................................................................11

4.2. TS8308500 PIN DESCRIPTION .......................................................................................................................................................12

4.3. TS8308500 PINOUT OF CBGA72 PACKAGE......................................................................................... .........................................13

4.4. TS8308500 CAPACITIES AND RESISTANCES IMPLANT...............................................................................................................14

OUTLINE DIMENSIONS - 72 PINS CBGA.....................................................................................................................................................14

OUTLINE DIMENSIONS - 72 PINS CBGA.....................................................................................................................................................15

4.5. THERMAL AND MOISTURE CHARACTERISTICS................................................................................................................................16

5. TYPICAL CHARACTERIZATION RESULTS.............................................................................................................17

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ......................................................................................................................17

5.2. EFFEC TIVE NUMBER OF BITS VER SU S POWER SU PPLIES VARIA TION................................................................... .................18

5.3. TYPICAL FFT RESULTS..................................................................................................................................................................19

5.4. SPURIOUS FREE DYNAMIC RANGE VER SU S INPUT AMPLITUDE......................................................ERREUR! SIGNET NON DÉFINI.

5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ...........................................................................................21

5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY ................................................................................22

5.7. SFDR VER SUS SAM PLING FREQUEN CY......................................................................................................................................22

5.8. TS8308500 ADC PERFORM ANCES VER SUS JUNCTION TEMPERA TU R E...................................................................................23

5.9. TYPICAL FULL POWER INPUT BANDWIDT H.................................................................................................................................24

5.10. ADC STEP RESPONSE...................................................................................................................................................................25

6. DEFINITION OF TERM S................................................................................................................................................26

7. TS8308500 MAIN FEATURES.........................................................................................................................................28

7.1. TIMING IN FO R MATIO N S.................................................................................................................................................................28

7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND..........................................................................29

7.3. ANALOG INPUTS (VIN) (VINB)........................................................................................................................................................29

7.4. CLOCK INPUTS (CLK) (CLKB).........................................................................................................................................................30

7.5. NOISE IMMUNITY INFORMATIONS................................................................................................................................................32

7.6. DIGITAL OUTPUTS..........................................................................................................................................................................32

7.7. OUT OF RANGE BIT........................................................................................................................................................................35

7.8. GRAY OR BIN ARY OU TPUT DATA FO R MAT SELECT...................................................................................................................35

7.9. DIODE PIN K1..................................................................................................................................................................................35

7.10. ADC GAIN CONTROL PIN K6..........................................................................................................................................................36

8. EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................37

8.1. EQUIVALENT AN AL O G INPU T CIR C UIT AND ESD PR O TECTIONS..............................................................................................37

8.2. EQUI VALENT AN AL OG CLOC K INPUT CIR C U IT AND ES D PR O TECTIONS.................................................................................37

8.3. EQUIVALENT DA TA OUT PU T BU FFER CIRC UIT AN D ESD PR O T ECTIONS................................................................................38

8.4. ADC GAIN ADJUST EQUI VALENT IN PU T CIRCU ITS AND ESD PROT EC TIONS.............................................................. .............38

8.5. GORB EQ U I VALENT IN PUT SCHE M ATIC AND ESD PROT EC TIONS............................................................................................39

8.6. DRR B EQUIVAL EN T INPUT SCHEM ATIC AND ESD PRO TECTION S............................................................................................39

9. TSEV8308500G : DEVICE EVALUATION BOARD ....................................................................................... .............40

10. ORDERING INFORMATION ........................................................................................................ .............................41

10.1. PACKAGE DEVICE..........................................................................................................................................................................41

10.2. EVALU ATION BO AR D......................................................................................................................................................................41

Preliminary Spec ificat ion

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TS8308500

1. SIMPLIFIED B LOCK DIAGRAM

2. FUNCTIONAL D ESCRIPTION

The TS8308500 is an 8 bit 500MSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz.

The TS8308500 includes a front-end master/sl ave Track and Hol d st age (S/ H), followed by an analog encodi ng st age and interpol at ion circuitry.

Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a

resynchronization stage followed by 75 Ω differential output buffers.

The TS8308500 works in fully differenti al mode from analog inputs up to digital outputs.

The TS8308500 features a full power input bandwidth of 1.3 GHz.

Control pin GORB is provided to select either Gray or Binary data output format.

Gain control pin is provided in order to adjust the ADC gain.

A Data Ready output async hronous reset (DRRB) is available on TS8308500.

The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation

tolerance (no performance drift measured at 150kRad total dose).

VIN,VINB

CL K, CLKB

G=2 T/H G=1 T/H G=1

CLOCK

BUFFER

RESISTOR

CHAIN

ANALOG

ENCODING

BLOCK

INTERPOLATION

STAGES

REGENERATION

LATCH ES

ERROR CO RR ECTIO N &

DECODE LOGIC

OUTPU T LA TC HE S &

BUFFERS

GAIN

DRRB DR,DRB GORB DATA,DATAB OR,ORB

MASTER/SLAV E TRACK & H OLD AMPLIFIER

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3. SPECIFICATIONS

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)

Parameter Symbol Comments Value Unit

Positive supply voltage VCC GND to 6 V

Digital negative supply

voltage DVEE GND to -5.7 V

Digital posi tive supply

voltage VPLUSD GND-0.3 to 2.8 V

Negative suppl y vol tage VEE GND to -6 V

Maximum difference

between negative supply

voltages

DVEE to VEE 0.3 V

Analog input voltages VIN or VINB -1 to +1 V

Maximum difference

between VIN and VINB

VIN - VINB -2 to +2 V

Digital i nput vol t age VDGORB -0.3 to VCC +0.3 V

Digital i nput vol t age VDDRRB VEE -0.3 to +0.9 V

Digital output voltage Vo VPLUSD-3 to VPLUSD -0.5 V

Clock input voltage VCLK or VCLKB -3 to +1.5 V

Maximum difference

between VCLK and VCLKB

VCLK - VCLKB -2 to +2 V

Maximum juncti on

temperature Tj+135 oC

Storage temperature Tstg -65 t o +150 oC

Lid temperat ure

(soldering 10s ) Tleads For dry pack

(see chapter 4.5)

+300 oC

Notes : Absolute maximum ratings are l i miting values (referenced to GND=0V), to be applied individually, whil e other parameters are within

specified operating conditions. Long exposure to maximum rating may aff ect devic e reliabi l ity.

The use of a thermal heat sink is mandatory (see Thermal characteristics).

3.2. RECOMMENDED CONDITIONS OF USE

Parameter Symbol Comments Min. Typ. Max. Unit

Positive supply voltage VCC 4.75 +5 5.25 V

Positive digital supply voltage VPLUSD ECL output compatibility GND V

VPLUSD LVDS output compatibility +1.4 +2.4 +2.6 V

Negative suppl y vol tages VEE, DVEE -5.25 -5.0 -4.75 V

Different i al analog i nput voltage

(Full Scale) VIN, VINB

VIN -VINB

50 Ω differential or single-ended ±113

450

±125

500

±137

550

mVpp

Clock input power level PCLK PCLKB 50 Ω single–ended clock i nput 3 4 10 dBm

Operating tem perature range TJCommerci al grade: “C” 0 < Tc ; Tj < 90 oC

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TS8308500

3.3. ELECTRICAL OPERATING CHARACTERISTICS

VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ;

Digital outputs 75 or 50 Ω differentially terminated ;

Tj (typical) = 70°C.

Parameter Symb Test

level Min Typ Max Unit

POWER REQUIREMENTS

Positive supply voltage Analog

Digital (ECL)

Digital (LVDS)

VCC

VPLUSD

4.5

1.4

2.4

5.5

2.6

Positive supply current Analog

Digital ICC

IPLUSD

1420

130 445

145 mA

Negative suppl y vol t age VEE 1 -5.5 -5 -4.5 V

Negative suppl y current Analog

Digital AIEE

DIEE

1185

160 200

180 mA

Nominal power dissi pati on PD 13.8 4.1 W

Power supply rejec t ion ratio (note 2) PSRR 4 0.5 2 mV/V

RESOLUTION 8bits

ANALOG INPUTS

Full Scale Input Voltage range (differential mode)

( 0 Volt common mode voltage ) VIN

VINB

4 -125

-125 125

125 mV

Full Scale Input Voltage range (single–ended input opt i on )

(see Application

Notes)

VIN

VINB

4 -250 0250 mV

Analog input capacitanc e CIN 433.5pF

Input bias current IIN 41020µA

Input Resistance RIN 40.51 MΩ

Full Power input Bandwidth FPBW 4 1.2 1.3 GHz

Small Signal input B andwidth (10 % full scale) SSBW 4 1. 2 1.3 GHz

CLOCK INPUTS

Logic compatibility for clock inputs (note 10 )

(see Application Notes) ECL or specified clock input

power level in dBm

ECL Clock inputs voltages (VCLK or VCLKB) : 4

• Logic “0” volt age VIL -1.5 V

• Logic “1” volt age VIH -1.1 V

• Logic “0” current IIL 550µA

• Logic “1” current IIH 550µA

Clock input power level int o 50 Ω ter min a tion DBm into 50 Ω

Clock input power level 4 -2 4 10 dBm

Clock input c apaci t a nce CCLK 433.5pF

6TS8308500

Preliminary Spec ificat ion

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Parameter Symb Test

level Min Typ Max Unit

DIGITAL OUTPUTS (notes 1,6)

Single ended or diff erential input mode, 50 % clock duty cycl e (CLK, CLKB), B i nary output data format,

Tj (typical) = 70°C. Full temperature range : 0°C < Tc ; Tj < +90°C

Logic compatibil ity f or digit al outputs

( Depending on the value of VPLUSD )

(see Application Notes)

ECL or LVDS

Different i a l output voltage swings ( assuming VPLUSD = 0V) :

75 Ω open transmission l i nes ( ECL levels )

75 Ω differentiall y terminated

50 Ω differentiall y terminated

41.50

0.70

0.54

1.620

0.825

0.660

Output levels ( assum i ng VPLUSD = 0V)

75 Ω open transmission l i nes (note 6) 4

• Logic “0” volt age VOL -1.62 -1.54 V

• Logic “1” volt age VOH -0.88 -0.8 V

Output levels ( assum i ng VPLUSD = 0V)

75 Ω d ifferentially terminated (note 6) 4

• Logic “0” volt age VOL -1.41 -1.34 V

• Logic “1” volt age VOH -1.07 -1 V

Output levels ( assum i ng VPLUSD = 0V)

50 Ω differentiall y terminated (note 6)

• Logic “0” volt age VOL 1, 2 -1.40 -1.32 V

• Logic “1” volt age VOH 1, 2 -1.16 -1.10 V

Different i al Output Swing DOS 4 270 300 mV

Output level drift with t emperat ure 4 1.6 mV/°C

DC ACCURACY

Single ended or diff erential input mode, 50 % clock duty cycl e (CLK, CLKB), B i nary output data format,

Tj (typical) = 70°C.

Differential non linearity (notes 2,3) DNL- 1-0.6 -0.3 LSB

DNL+ 10.3 0.6 LSB

Integral non linearity (notes 2,3) INL- 1-1.0 -0.7 LSB

INL+ 1 0.7 1.0 LSB

No missing codes (note 3) Guaranteed over specified temperature range

Gain error 1, 2 -10 -2 10 % FS

Input offset volt age 1, 2 -26 -5 26 mV

Gain error drift

Offset error drift 4

100

125

150

ppm/°C

Preliminary Spec ificat ion

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TS8308500

Parameter Symb Test

level Min Typ Max Unit

TRANSIENT PERFORMANCE

Bit Error Rate (notes 2, 4)

FS = 1 Gsps Fin = 62.5 MHz BER 4 1E-12 Error/

sample

ADC sett ling time (note 2)

VIn -VinB = 400 mVpp TS 4 0.5 1 ns

Overvoltage recovery time (note 2) TOR 4 0.5 1 ns

AC PE RFORMANCE (Expected values)

Single ended or diff erenti al i nput and clock mode, 50 % clock duty c ycl e (CLK, CLKB), Binary output data format,

Tj. = 70°C, unless otherwise specified.

Signal to Noise and Dist ortion ratio (note 2) SINAD

FS = 500 Msps Fin = 20 MHz 4 44 dB

FS = 500 Msps Fin = 500 MHz (Tj = 90°C) 4 43 44 45 dB

FS = 500 Msps Fin = 1000 MHz (-1dB Fs) 4 dB

FS = 50 Msps Fin = 25 MHz 1 40 45 dB

Effecti ve Num ber Of bits ENOB

FS = 500 Msps Fin = 20 MHz 4 7.2 Bits

FS =500 Msps Fin = 500 MHz (Tj = 90°C) 4 6.8 7. 0 7.3 Bits

FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 6.4 6.6 Bits

FS = 50 Msps Fin = 25 MHz 1 7.0 7.2 Bi ts

Signal to Noise Ratio (note 2) SNR

FS = 500 Msps Fin = 20 MHz 4 45 dB

FS = 500 msps Fin = 500 MHz (Tj = 90°C) 4 44 45 46 dB

FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 40 41 dB

FS = 50 Msps Fin = 25 MHz 1 44 45 dB

Total Harmonic Distortion (note 2) THD

FS = 500 Msps Fin = 20 MHz 4 50 dB

FS = 500 Msps Fin = 500 MHz (Tj = 90°C) 4 48 49 53 dB

FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 dB

FS = 50 Msps Fin = 25 MHz 1 46 51 dB

Spurious Free Dynamic Range (note 2) SFDR

FS = 500 Msps Fin = 20 MHz 4 54 dBc

FS = 500 Msps Fin = 500 MHz (Tj = 90°C) 4 52 53 54 dBc

FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 dBc

FS = 500 Gsps Fin = 1000 MHz (-3dBFs) 4 dBc

FS = 50 Msps Fin = 25 MHz 1 48 55 dBc

Two-tone inter-modul ation distortion (note 2) IMD 4

FIN1 = 199.5 MHz @ FS = 500 Msps TBD TBD dBc

FIN2 = 200.5 MHz @ FS = 500 Msps

8TS8308500

Preliminary Spec ificat ion

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Parameter Symb Test

level Min Typ Max Unit

SWITCHING PERFORMA NCE AND CHARACTERISTICS – See Timing Diagrams Figure 1, Figure 2

Maximum clock frequency (Note 14) FS500 700 Msps

Minimum clock frequency (Note 15) FS410 50Msps

Minimum Clock pulse width (high) TC1 4 1710 2 50 ns

Minimum Clock pulse width (l ow) TC2 4 1710 2 50 ns

Aperture delay (Note 2) TA 4 100 +250 400 ps

Aperture uncertainty (Notes 2, 5) Jitter 4 0.4 0.6 ps (rms)

Data output delay (Notes 2, 10, 11, 12) TOD 4 1150 1360 1660 ps

Output rise/fall time for DATA (20 % – 80 %)

(note 11)TR/TF 4 250 350 550 ps

Output rise/fal l time for DA TA READY

(20 % – 80 % ) (note 11)

TR/TF 4 250 350 550 ps

Data ready output delay (Notes 2,10, 11, 12) TDR 4 1110 1320 1620 ps

Data ready reset delay TRDR 4 720 1000 ps

Data to data ready – clock low pulse width

(See timing diagram, notes 9, 13, 14)

TOD-

TDR 4 0 40 80 ps

Data to data ready output del ay (50% duty cycle)

(See timing diagram, notes 2, 15) @ 500 Msps

TD1 4 920 960 1000 ps

Data pipeline del ay TPD 4 4 cl ock

cycles

Note 1 : Different i al output buffers are i nternally loaded by 75

Ω

resistors. Buffer bias current = 11 mA.

Note 2 : See definiti on of terms

Note 3 : Histogram test i ng based on sampling of a 10 MHz sinewave at 50 MSPS.

Note 4 : Output error amplit ude <

4 LSB around worst code.

Note 5 : Maximum jitter value obtained for single–ended clock i nput on the JTS8308500 di e (chi p on board) : 200 fs.

(500 fs expected on TS8308500)

Note 6 : Digital output back termination options depicted in Application Notes f i gures 3, 4,5 .

Note 7 : With a typical value of TD = 465 ps, at 500 Msps, the timing safety margin for the data storing using the ECLinPS 10E452 output

registers from Motorola is of

315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB).

Note 8 : The clock inputs may be indifferently entered in differential or single–ended, using ECL levels or 4 dBm typical power level into the

Ω

termination resistor of the inphase clock input.

(4 dBm into 50

Ω

clock input correspond to 10 dBm power level for the clock generat or.)

Note 9 : At 500 MSPS, 50/50 clock duty cycle, TC2 = 1 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rat e.

Note 10 : Specified loadi ng conditions for digital outputs :

- 50

Ω

or 75

Ω

controlled impedance traces properly 50 / 75

Ω

terminated, or unterminated 75

Ω

controlled impedance traces.

- Controlled impedanc e trac es far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic

capacitanc e of 1.5 pF including package and ESD protections. )

Note 11 : Termination load parasitic capacit ance derating values :

- 50

Ω

or 75

Ω

controlled impedance traces properly 50 / 75

Ω

terminated : 60 ps / pF or 75 ps per additional ECLinPS load.

- Unterminated ( source terminat ed ) 75

Ω

controlled impedance lines : 100 ps / pF or 150 ps per additional ECLinPS terminatio n

load.

Note 12 :apply proper 50 / 75

Ω

impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8308500 Evaluation

Board.

Note 13 : Values for TOD and TDR track each other over temperature, (1 % variation for TOD - TDR per 100 oC temperature variation).

Therefore TOD - TDR variation over temperature is negligibl e. Moreover, the internal (onchip ) and package skews between each Data

TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps

apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation over

temperature in section 7).

Note 14 : Min value guarantees performance. Max value guarantees functionality.

Note 15 : Min value guarantees functionali ty . M ax value guarant ees perf ormanc e.

Preliminary Spec ificat ion

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TS8308500

3.4. TIMING DIAGRAMS

Figure 1: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE)

Data Ready Reset, Cl ock Hel d at LOW Level

Figure 2: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE)

Data Ready Reset, Cl ock Hel d at HIGH Level

DATA

READY

DR / DRB TD2 = TC2 + TOD – TDR

= TC2 + 40 ps = 1040 ps

250 ps

TD1 = TC1 + TDR – TOD

= TC1 – 40

s = 960

TC2

TC1

TC = 2 ns

TPD = 4.0 Clock Periods TOD = 1360 ps

TDR = 1320 ps 2 ns

1360 ps

TDR = 1320 ps

TRDR = 720 ps

1 ns

N -5 N -4 N -3 N -2 N -1 N + 1

N+3

N+2

N + 1

CLK / CLKB

VIN / VINB

Digital

OUTPUTS

DATA READY

RESET

TD2 = TC2 + TOD – TDR

= TC2 + 40 ps = 1040 ps

TD1 = TC1 + TDR – TOD

= TC1 – 40

s = 960

TDR = 1320 ps

1 ns

TRDR = 720 ps

DATA READY

RESET

DATA

READY

DR / DRB

TDR = 1320 ps

CLK / CLKB

250 ps

TC2

TC1

TC = 2 ns

N + 3

N + 2

N + 1

VIN / VINB

2 ns

Digital

OUTPUTS

TPD = 4.0 Clock Periods TOD = 1360 ps

360

N -5 N -4 N -3 N -2 N -1 N + 1

10 TS8308500

Preliminary Spec ificat ion

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3.5. EXPLANATION OF TEST LEVELS

1 100% production tested at +25°C (1) (for “C” Temperature range (2) ).

2 100 % production tested at +25°C (1), and sample tested at specified temperatures (for “V” and “M” Temperature ranges (2) ).

3 Sample tested only at specif i ed tem peratures

4 Parameter is guaranteed by design and charact eri zation testing (thermal steady-s t ate conditions at specified temperature).

5 Parameter is a typical value only

Only MIN and MAX values are guaranteed (typical values are issui ng from characterization results).

(1) Unless otherwise specified, al l tests are puls ed test s : therefore Tc = Ta where Tc and Ta are case and ambient temperature.

(2) Refer to ORDERING INFORMATION chapter.

3.6. FUNCTIONS DESCRIPTION

Name Function

VCC Positive power supply

VEE Analog negative power supply

VPLUSD Digital positi ve power supply

GND Ground

VIN, VINB Differential analog inputs

CLK, CLKB Different i a l clock inputs

<D0:D7>

<D0B:D7B> Differential output dat a port

DR ; DRB Different ial data ready outputs

OR ; ORB Out of range outputs

GAIN ADC gain adjust

GORB Gray or Binary di gi tal output select

DIOD/DRRB Die junction temp. measurement/

asynchronous data ready reset

3.7. DIGITAL OUTPUT CODING

NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearit y voltage errors.

Differential

analog input Vo l tage level Digital output Out of

Range

Binary

GORB = VCC or floating Gray

GORB = GND

> +251 mV > Positive full scale + 1/2 LSB 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1

+251 mV

+249 mV Positive full scale + 1/2 LSB

Positi ve full scal e – 1/2 LSB 11111111

11111110 10000000

10000001 0

+126 mV

+124 mV Positi ve 1/2 scale + 1/2 LSB

Positive1/2 scale – 1/2 LSB 11000000

10111111 10100000

11100000 0

+1 mV

-1 mV B i pol ar zero + 1/2 LSB

Bipolar zero - 1/ 2 LSB 10000000

01111111 11000000

01000000 0

-124 mV

-126 mV Negati ve 1/ 2 sc ale + 1/2 LSB

Negative 1/2 scale - 1/2 LSB 01000000

00111111 01100000

00100000 0

-249 mV

-251 mV Negati ve f ul l sc al e + 1/2 LSB

ative full sc al e - 1/2 LSB 00000001

00000000 00000001

00000000 0

< -251 mV < Negative f ull scale - 1/2 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

VPLUSD = +0 V (ECL)

VPLUSD = +2 .4V (LVDS)

VIN

VINB

CLK

CLKB

D0 →

→ →

→ D7

D0B →

→→

→ D7B

VEE=-5V

VCC = +5 V

TS8308500

ORB

GND

GORB

GAIN

DVEE=-5V

DIOD/

DRRB

DRB

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TS8308500

4. PACKAGE DESCRIPTION.

4.1. TS8308500 PAD DESCRIPTION

Pad

number Chip pad

Name Chip Pad Function

PLUSD Positive digital supply (double pad) (note 2)

2 D5 In phase (+) digital output, bit 5 (D7 is the MSB ; Bit 7, D0 is the LSB ; Bit 0)

3 D5B Inverted phase (-)digital output, bit 5

4 D4 In phase (+) digital output, bit 4

5 D4B Inverted phase (-) digital output, bit 4

6DV

EE -5V digital supply (double pad)

7 DR In phase (+) Data Ready

8 DRB Inverted Phase (-) Data Ready

9 D3 In phase (+) digital output, bit 3

10 D3B Inverted phase (-) digital output, bit 3

11 VPLUSD Positive digital supply (double pad) (note 2)

12 D2 In phase (+) digital output, bit 2

13 D2B Inverted phase (-) digital output, bit 2

14 D1 In phase (+) digital output, bit 1

15 D1B Inverted phase (-) digital output, bit 1

16 D0 In phase (+) digital output, bit 0, Least Significant Bit

17 D0B Inverted phase (-) digital output, bit 0, Least Significant Bit

18 GORB Gray or Binary data output format select. (Note 1)

19 VCC +5V supply (double pad)

20 GND Analog Ground (double pad)

21 VCC +5V supply (double pad)

22 VEE -5V analog supply (double pad)

23 VCC +5V supply (double pad)

24 GND Analog Ground (double pad)

25 CLK In phase (+) clock input (double pad)

26 GND Analog Ground

27 CLKB Inverted phase (-) clock input (double pad)

28 GND Analog Ground (double pad)

29 VEE -5V analog supply (double pad)

30 VCC +5V supply (double pad)

31 VEE -5V analog supply (double pad)

32 DIOD/DRRB Diode input for Tj monitoring / Input for asynchronous Data Ready Reset

33 GND Analog Ground

34 VIN In phase (+) analog input (double pad)

35 GND Analog Ground

36 VINB Inverted phase (-) analog input (double pad)

37 GND Analog Ground (double pad)

38 GAIN ADC gain adjust input

39 VCC +5V supply (double pad)

40 VCC +5V supply

41 OR In phase (+) Out of Range digital output

42 ORB Inverted phase (-) Out of Range digital output

43 D7 In phase (+) digital output, bit 7, Most Significant Bit

44 D7B Inverted phase (-) digital output bit 7

45 D6 In phase (+) digital output, bit 6

46 D6B Inverted phase (-) digital output, bit 6

Note 1: GORB tied to Vcc or floating : Binary output data format. GORB tied to GND : Gray output data format

Note2: The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuit ry can withst and a l ower level for input common mode, it is rec ommended to lower the positive digital

supply level i n the name proporti on in order to spare power dissi pation.

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4.2. TS8308500 PIN DESCRIPTION

Symbol Pin number Function

GND A2, A5, B1, B5, B10, C2, C9, D2,

E1, E2, E11 , F1 , F2 , G 1 1 , J3 , J9 ,

K2, K3, K4, K5, K10, L2, L5

Ground pins.

To be connected to external ground plane.

VCC A4, A6, B2, B4, B6, C3, H1, H2,

L6, L7 +5 V positive supply.

VEE A3, B3, G1, G2, J1, J2 5 V analog negative supply

DVEE F10, F11 -5 V di gital negative supply.

VIN L3 In phase (+) analog input signal of the sample and Hold

different i al preampl ifi er.

VINB L4 Inverted phase (-) of ECL clock input signal (CLK).

CLK C1 In phase (+) ECL clock input signal. The analog input is sampled

and held on the rising edge of the CLK signal.

CLKB D1 Inverted phase (-) of ECL clock input signal (CLK).

B0, B1, B2 , B3 , B4 , B5 , B6 ,

B7 A8, A9, A10, D10, H11, J11, K9,

K8 In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

B0B, B1B, B2B, B3B, B4B,

B5B, B6B, B7B B7, B8, B9, C11, G10, H10, L10,

L9 Inverted phas e (-) Di gital outputs .

B0B is the inverted LSB. B7B is the inverted MSB.

OR K7 In phase (+) Out of Range Bit.

Out of Range is high on the leading edge of code 0 and code 256.

ORB L8 Inverted phase (+) of Out of Range Bit (OR).

DR E10 In phase (+) output of Data Ready Signal.

DRB D11 Inverted phas e (-) output of Dat a Ready Signal (DR).

GORB A7 Gray or Binary s el ect output format control pin.

– Binary output format if GORB is floati ng or VCC.

– Gray output format if GORB is connected at ground (0 V).

GAIN K6 ADC gain adj ust pin.

The gain pin is by default grounded, the ADC gain transfer fuction

is nominally close to one.

DIOD/DRRB K1 Die funct i on tem perat ure meas urem ent pin and asynchronous

data ready reset acti ve l ow, single ended ECL input.

VPLUSD B11, C10, J10, K11 + 2.4 V for LVDS output levels otherwise to GND (1)

NC A1, A11, L1, L11 Not connected.

Note 1 : The common mode level of the output buffers is 1.2V below t he positi ve digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground ).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital

supply level i n the same proportion i n order to spare power dissipat i on.

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4.3. TS8308500 PINOUT OF CBGA72 PACKAGE

BOTTOM VIEW

14 TS8308500

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4.4. TS8308500 CAPACITIES AND RESISTANCES IMPLANT

100

Ohm

100100 100 50

Ohm

100

Ohm

100

Only on-package marking

ect

ated

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OUTLINE DIMENSIONS - 72 PINS CBGA

100

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4.5. THERMAL AND MOISTURE CHARACTERISTICS

4.5.1. THERMAL RESIS T ANCE FROM JUNCTION TO AMBI ENT : RTHJA

The following table lists the convec tor thermal performances parameters of the devic e itself, with no external heatsink added.

4.5.2. THERMAL RESIST ANCE FROM JUNCTION TO CASE : RTHJC

Typical val ue for Rt hjc is given to 1. 56° C/W.

This value does not include thermal c ontact resi st ance between package and external component (heatsink or PCBoard).

As an example, 2.0°C/W can be taken for 50 µm of thermal grease.

4.5.3. CBGA72 BOARD ASSEMBLY WITH EXTERNAL HEATSINK

It is recommended to use an external heatsink or P CBoard s peci al desi gn.

Cooling syst em effi ci ency can be monitored using the Temperature Sensing Diode, integrat ed in the devic e.

Note: Units = mm

4.5.4. MOISTURE CHARACTERISTICS

This device is very sensitive to the moisture (MSL6 according JEDEC standard).

W hen receiving t he devic es (i n dry pack), you must follow strictl y the instructions on the stick er.

The devices must be mounted within 6 hours at factory conditions of ≤ 30°C/60% Relative Humidity (RH).

These devices, if subjected to infrared reflow, vapor-phase refl ow, or equival ent processing (peak package body temp. 220°C), must be baked

before mounting for :

- 192 hours at 40°C + 5°C/-0°C and <5% RH for low-temperature devic e containers, or

- 24 hours at 125°C ± 5°C for high-temperature device cont ai ners.

Note : in case of reworking of a component on a board containing this device, the board could need to be heated. In this case and to preserve

the TS8308500, it is important t o bake the board first, acc ordi ng to the instruct i ons above.

012345

Air flow (m/ s)

Rthja (deg.C/W)

Air flow Esti mated ja thermal resistance

(m/s) (oC / W)

045

0,5 35,8

1 30,8

1,5 27,4

2 24,9

2,5 23

3 21,5

4 19,3

5 17,7

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5. TYPICAL CHARACTERIZATION RESULTS

50/50 clock duty cycle, Binary output codi ng, Tj = 70°C, single-ended analog and clock inputs, unl ess ot herwise spec ifi ed.

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ

5.1.1. INTEGRAL NON LINEARITY

5.1.2. DIFFERENTIAL NON LINEARITY

LSB

INL = +/- 0.7 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.68 LSB Negative peak : -0.69 LSB

LSB

DNL = +/- 0.3 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.3 LSB Negative peak : -0. 29 LSB

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5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION

-7 -6,5 -6 -5,5 -5 -4,5 -4

Effective number of bits = f

(

VEEA

)

; Fs = 500 MSPS ; Fin = 100 MH z

VEEA (V)

ENOB (bits)

33,544,555,566,57

Effective number of bits = f

(

VCC

)

; Fs = 500 MSPS ; Fin = 100 MHz

VCC (V)

ENOB (bits)

-6 -5,5 -5 -4,5 -4 -3,5 -3

Effective number of bits = f

(

VEED

)

; Fs = 500 MSPS ; Fin = 100 MHz

VEED (V)

ENOB (bits)

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5.3. TYPICAL FFT RESULTS

5.3.1 SPECTRUM FOR FS = 500 MSPS, FIN = 498 MHZ (FULL SCALE INPUT)

Acquisition of 4096 points THD = -49.67 dBc

Fs = 500 MSPS SINAD = 44.01 dB

Fin = 498 MHz SFDR = -54.31 dBc

SFSR = -0.94 dB ENOB = 7.13 bits

SNR = 45.39 dB

5.3.2. RECONSTRUCTED SIGNAL FOR FS = 500 MSPS, FIN = 498 MHZ (FULL SCALE INPUT)

Acquisition of 4096 sampl es

Fs = 500 MSPS Amplitude: 0.221V (114.5 LSB)

Fin = 498 MHz Offset: 0V (122.5 LSB)

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5.3.1. SPECTRUM FOR FS = 500 MSPS, FIN = 250 MHZ (FULL SCALE INPUT)

Acquisition of 4096 points THD = -49.81 dBc

Fs = 500 MSPS SINAD = 44.38 dB

Fin = 250 MHz SFDR = -52.78 dBc

SFSR = -1.02 dB ENOB = 7.19 bits

SNR = 45.84 dB

5.3.2. RECONSTRUCTED SIGNAL FOR FS = 500 MSPS; FIN = 250 MHZ (FULL SCALE INPUT)

Acquisition of 4096 sampl es

Fs = 500 MSPS Amplitude: 0.189V (113.5 LSB)

Fin = 250 MHz Offset: 0V (122.5 LSB)

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5.4. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY

Fs=500 Msps, Fin = 20MHz up to 1000 MHz, -1dB Full Scale input,

To be completed: ENOB, SNR and SFDR plots

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5.5. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 250 MHz and Fs = 20 Msps to 1300 Msps

To Be Completed

5.6. SFDR VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 250 MHz and Fs = 20 Msps to 1300 Msps

To Be Completed

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5.7. TS8308500 ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE

Fs = 500 Msps, Fin = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 120°C.

ENOB, SNR and THD plots to be completed

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5.8. TYPICAL FULL POWER INPUT BANDWIDTH

1.3 GHz at -3 dB (-2dBm full power input)

Band Flatness / 8Bit 500Msps (-1 dB FS)

-6

-5

-4

-3

-2

-1

0 200 400 600 800 1000 1200 1400 1600

Frequency (MHz)

SFSR (dB FS)

-40 -20 0 20 40 60 80 100 120 140 160

Power consumption versus junction temperature

Fs = 500M SPS ; Fin = 250 MHz ; Duty c yc le = 50%

Temperature ( oC)

Power consumption (W)

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5.9. ADC STEP RESPONSE

Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps.

Note : This step response was obtained with the TSEV8308500 on board (device in die form).

5.9.1. TEST PULSE DIGITIZED WITH 20 GHZ DSO

5.9.2. SAME TEST PULSE DIGITIZED WITH TS8308500 ADC

N.B. : ripples are due to the test setup (they are present on bot h measurements )

50 mV/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00time (ns)

Vpp ~ 260 mV

Tr ~ 270 ps

50 mV/div

600 ps/div

0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.00

200

150

100

ADC code

time (ns)

Tr ~ 330 ps

50 codes/div (Vpp ~260 mV)

600 ps/div

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6. DEFINITION OF TERMS

(BER) Bi t Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs

by more than +/- 4 LSB from the correct code.

(BW) Full power i nput

bandwidth A nalog input f requency at which the fundamental component in the di gitally rec onstructed output

has fallen by 3 dB with respect to its low frequenc y value (determined by FFT analysis ) for input

at Full Scale.

(SINAD) S i gnal to noise and

distortion ratio Ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale, to the RMS

sum of all other spectral c omponents, including the harmonics except DC.

(SNR) Signal to noise ratio Ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale, to the RMS

sum of all other spectral c omponents excludi ng the five first harmonics.

(THD) Total harmonic

distorsion Rat io expressed i n dBc of the RMS sum of the first five harmonic com ponents, to the RMS value

of the measured fundamental spectral component.

(SFDR) Spurious free dynamic

range Ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale, to the RMS

value of the next highest spectral component (peak spurious s pectral component). SFDR is the

key parameter for selecting a converter to be used in a frequency domain application ( Radar

systems, digital receiver, network analyzer ….). It may be reported in dBc (i.e., degrades as

signal l evels is lowered), or in dBf s (i.e. always related back to converter full scale).

(ENOB) Effective Number Of Bits Where A is the actual input amplitude and V

is the full scale range of the ADC under test

(DNL) Differential non

linearity The Differential Non Linearity for an output code i is the difference between the measured step

size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum

value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no

missing output c odes and that the transfer function is monotonic.

(INL) Integral non lineari ty The Integral Non Linearity for an output code i is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(DG) Differential gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. FIN = 5 MHz . (TBC)

(DP) Diff erential phase Peak Phase variat ion (in degrees) at five different DC levels for an A C signal of 20% Full Sc ale

peak to peak amplitude. FIN = 5 MHz. (TBC)

(TA) Apert ure del ay Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero c rossing point),

and the time at which (VIN,VINB) is sampled.

(JITTER) Aperture uncert ainty Sam ple to sample variation in aperture delay. The voltage error due to jitter depends on t he slew

rate of the signal at the sampling point.

(TS) Settling tim e Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step

function is appli ed to the differential anal og input.

(ORT) Overvoltage recov ery

time Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is

reduced to midscal e.

(TOD) Digital data

Output delay Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to

the next point of change in the differenti al out put data (zero crossing) with specified load.

(TD1) Time delay from Data to

Data Ready Time delay from Data transition to Data ready.

(TD2) Time delay from Data

Ready to Data General expression i s TD1 = TC1 + TDR – TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding clock period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipel i ne Del ay Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8308500 the TPD is 4

clock periods.

(TRDR) Data Ready reset delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero trans iti on of the Data Ready output si gnal (DR).

SINAD - 1.76 + 20 log (A/V/2)

ENOB = 

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(TR) Rise time Tim e delay for the output DATA signals to rise from 20% to 80% of delta between low level and

high level.

(TF) Fall time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power supply

rejection ratio Ratio of input offset variat i on to a change in power supply voltage.

(NRZ) Non return to zero When the input signal is larger than the upper bound of the ADC input range, the output code is

identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to the

minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal

amplitude rem ains within the absolute maximum ratings).

(IMD) InterModul ati on Distortion The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the

worst third order int erm odulati on products . The input tones levels are at – 7dB Full Scale.

(NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

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7. TS8308500 MAIN FEATURES

7.1. TIMING INFORMATIONS

7.1.1. TIMING VALUE FOR TS8308500

Timing values as defined in 3.3 are advanc ed data, issuing f rom electric simulat i ons and first c haract eri zation results fitted with measurements.

Timing values are given for CBGA72 package inputs / outputs , taki ng i nto account pack age internal cont rol l ed impedance traces propagation

delays, and specified termination loads.

Propagation delays i n 50/75 ohms impedance traces are NOT taken into account for TOD and TDR.

Apply proper derati ng val ues corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following conditions :

Note 1 : Specified Terminati on Load (Different i al output Data and Data Ready) :

50 ohms resistor in paralle l with 1 standard ECLinPS register from Motorola, (e.g : 10E452)

(Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protect i ons)

If addressi ng an output Dmux, take care if some Digit al outputs do not have the same terminat i on load and apply corres pondi ng d erati ng val ue

given below.

Note 2 : Output Termination Load derating values f or TOD and TDR :

~ 35 ps/pF or 50 ps per additional ECLinPS load.

Note 3 :Propagation tim e delay derati ng val ues have also to be appl i ed for TOD and TDR :

~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board.

Apply proper time delay derating value if a different dielectric l ayer is used.

7.1.2. PROPAGATION TIME CONSIDERATIONS

TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and

input/output termination loads. For the TSEV8308500 Evaluation Board, the propagation time delay is 6ps/mm (155ps/inch) corresponding to

3.4 (@10GHz) dielect ric const ant of the RO4003 used for the Board.

If a different dielect ri c l ayer is used (f or inst ance Teflon), please use appropriate propagation time values.

TD does NOT depend on propagation times because it is a differential data.

(TD is the time difference between Data Ready output delay and di gital Data output delay)

TD is also the most straightforward data to measure, again because i t is differenti al :

TD can be measured directly onto termination loads, with matched Oscillosc opes probes.

7.1.3. TOD - TDR VARIATION OVER TEMPERATURE

Values for TOD and TDR track each other over temperature (1 perc ent variation for TOD - TDR per 100 degrees Celsius temperature variati on).

Therefore TOD - TDR variation over temperature is negligibl e. Moreover, the internal (on-chip) and pack age skews between each Data TODs

and TDR effect can be considered as negligi bl e.

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values.

In other terms :

If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ).

If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD - TDR values may be dictated by total

digital data ske ws between every TODs (each digital data) and TDR :

MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches.

The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR.

7.1.4. PRINCIPLE OF OPERATION

The Analog input is sampled on the rising edge of external clock input (CLK,CLKB ) after TA (aperture delay) of typically 250ps .

The digitized data is avai l abl e after 4 clock periods l atency (pipeline delay (TPD)), on clock risi ng edge, aft er 1360 ps typical propagation delay

TOD.

The Data Ready different i al output signal frequency (DR,DRB) is half the external clock frequency, that is it switches at the s ame rat e as the

digital outputs.

The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation del ay TDR of typically 1320 ps.

A Master Asynchronous Reset input command DRRB ( ECL compatible single-ended input) is available for initiali zing the diff erential Data

Ready output signal ( DR,DRB ) .This feature is mandatory in certain applications us i n g interl eaved ADCs or usi ng a single ADC with

demultipl exed outputs. Actually, without Data Ready signal initi al i zat i on, it is impossibl e t o store the output digital data i n a defined order.

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7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND

7.2.1. DATA READY OUTPUT SIGNAL RESET

The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V

for Data Ready out put signal Master Reset . S o long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains

at logical zero and is independent of th e external free running enc odi ng clock.

The Data Ready output signal (DR, DRB) is reset to logic al zero after TRDR= 720 ps typical.

TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data

Ready output signal (DR,DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

7.2.2. DATA READY OUTPUT SIGNAL RESTART

The Data Ready output signal rest arts on DRRB command rising edge, ECL logical hi gh levels (-0. 8V ).

DRRB may also be Grounded, or is allowed to float, for norm al free running Data Ready output signal.

The Data Ready signal restart s equence depends on the logical level of the external encoding clock, at DRRB rising edge instant :

1) The DRRB rising edge occurs when external encoding cl ock input (CLK,CLKB) is LOW :

The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already

defined hereabove.

2) The DRRB rising edge occurs when external encoding cl ock input (CLK,CLKB) is HIGH :

The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps.

Consequently, as the analog input is sampled on clock risi ng edge, the fi rst digitized data corresponding to the first acquisit i on ( N ) after Data

Ready signal rest art ( ri si ng edge ) is always strobed by the third rising edge of the data ready signal.

The time delay (TD1) is specified between the last point of a change in the differenti al output dat a (zero cross i ng point) to the rising or falling

edge of the differenti al Data Ready si gnal (DR,DRB) (zero crossing point).

Note 1 : For normal initializat i on of Data Ready output signal , t he external encoding clock signal frequency and level must be controlled.

It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.

Note 2 : One single pin is used for both DRRB input command and die junction temperature monitori ng.

Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. )

Temperature monitori ng and Data Ready control by DRRB is not possible simultaneousl y.

7.3. ANALOG INPUTS (VIN) (VINB)

The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor.

In differenti al mode input configurat i on, t hat means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common m ode is

GROUND.

The typical input capacitanc e is 3 pF for TS8308500 in CBGA package.

Differential inputs voltage span

-125

125

[mV]

-250 mV250 mV

VIN

500mV

Full Scale

analog input

VINB

(VIN,VINB) = +/- 250 mV = 500 mV diff

0 Volt

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Differential versus single ended analog input operation

The TS8308500 can operate at full speed in either differential or single ended confi guration.

This is explained by the fact the ADC uses a high input impedance differenti al preampl ifi er st age, (prec edi ng the Sample and hold stage), which

has been designed in order to be entered either in differential m ode or single–ended mode.

This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins

(52, 53, 58, 59) which constitut e the local ground reference for the inphase analog input pin (VIN).

Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

In typical singl e–ended conf i guration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through t he 50 ohms

terminat i on resist or.

In single–ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak, centered on 0V. (or -2 dBm into 50 ohms.)

The inverted phase input is at ground potenti al through the 50 ohms terminati on resist or.

However, dynam ic performances can be somewhat improved by entering either analog or clock inputs in differential mode.

Typical Single ended analog input configuration

VIN or VINB VIN or VINB double pads

50 Ω

(on packagel)

50 Ω reverse terminati on

1MΩ 3 pF

-250

250

[mV]

500 mV

Full Scale

analog input

VINB

VIN

VINB = 0V

VIN = +/- 250 mV ⇔ 500 mV diff

7.4. CLOCK INPUTS (CLK) (CLKB)

The TS8308500 can be clocked at full speed without noticeable performance degradation i n either different i al or si ngl e ended configuration.

This is explained by the fact the ADC uses a differential pream pl ifi er stage for the clock buffer, which has been designed in order to be entered

either in diff erential or singl e–ended mode.

Recommended sinewave generator c haracteristics are typically -120 dBc/Hz phase noise floor spectral density, @ 1 KHz from carrier ,

assuming a singl e tone 4 dBm input for the clock signal.

7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)

Although the clock inputs were intended t o be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8308500 cl ock buffer can

manage a single–ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not

require the use of a power splitter.

No performance degradation ( e.g. : due to timing jitter) is observed in this particular single–ended configuration up to 500 MSPS Nyquist

conditi ons ( Fin = 250 MHz ).

This is all the more so true since the inverted phase clock input pin is 50 ohms terminated on the package (that is very close to one of the

neighboring shiel d ground pi n, which consti tutes the local Ground reference for the inphase clock input ).

Thus the TS8308500 differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

Moreover, a very low phase noise sinewave generator must be used for enhanced jitter perf orm ance.

The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.

This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.

Do not exceed 10 dBm to avoid saturation of the preamplifier i nput t ransi st ors.

Preliminary Spec ificat ion

ββ

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TS8308500

Single ended Clock input (Ground common mode)

VCLK common mode = 0 Volt

VCLKB=0 Volt

4 dBm typical clock input power level

(into 50 ohms terminati on resistor)

[V]

VCLK

VCLKB = ( 0 V )

-0.5V

+0.5V CLK or CLKB

50 Ω

(on package)

50 Ω reverse terminati on

1MΩ 0.4 pF

CLK or CLKB double pad

Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock i nput pow er lev el.

7.4.2. DIFFERENTIAL ECL CLOCK INPUT

The clock inputs can be driven differential l y with nominal –0.8V / -1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol lowed by a power splitter (hybrid j unction) in order

to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offsetting the common mode voltage to ECL levels.

Note: As the biasing tees propagation times are not matching, a tunable del ay line is required in order to ensure the signals t o be 180 degrees

out of phase especiall y at fast clock rates in the 500 MSPS range.

Differential Clock inputs (ECL Levels)

-0.8V

[mV]

-1.8V

VCLKB

VCLK

Common mode = -1.3 V

CLK or CLKB

50 Ω reverse terminati on

1MΩ 0.4 pF

GND

50 Ω

(on package)

CLK or CLKB double pad

7.4.3. SINGLE ENDED ECL CLOCK INPUT

In single–ended c onfiguration enter on CLK ( resp. CLKB ) pin , with the i nverted phase Clock input pin CLKB (respectively CLK ) connected to -

1.3V through the 50 ohms termination res ist or (on package).

The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode.

Single ended Clock input (ECL):

VCLK common mode = -1.3 Volt.

VCLKB = -1.3 Volt

-0.8V

[V]

-1.8V

VCLK

VCLKB = -1.3 V

32 TS8308500

Preliminary Spec ificat ion

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7.5. NOISE IMMUNITY INFORMATIONS

Circuit nois e immunity performance begins at design level.

Efforts have been m ade on the design in order to make the device as insensiti ve as poss i bl e to chip environment perturbations resulting from

the circuit it self or induced by external circuitry.

(Cascode st ages isol ation, in t ernal damping resi stors, clamps, int ernal (onc hi p) decoupl i ng capacitors.)

Furthermore, the fully diff erential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode

noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifi e rs.

Moreover, proper active signals shielding has been provided on the chi p to reduce the amount of coupled noise on the active inputs :

The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground pins , which must be direct l y connect e d to the

external ground plane.

7.6. DIGITAL OUTPUTS

The TS8308500 differential out put buffers are i nternall y 75 ohms loaded. The 75 ohms resistors are connected to the digit al ground pi ns through

a -0.8v level shift di ode (see Figures 3,4, 5 on next page).

The TS8308500 output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminat ed impedanc e lines or coaxial cabl es.

An 11 mA bias current flowing alternatel y i nto one of the 75 ohms resis tors when switc hi ng ensures a 0. 825 V voltage drop across the resistor

(unterm i nated outputs).

The VPLUSD positive suppl y voltage al l ows the adjustment of the output common mode level from -1.2V (VPLUSD=0V for ECL output

compatibil ity) t o +1.2V (VPLUSD=2.4V for LVDS output compatibility).

Therefore, the single ended output voltages vary approximatel y between -0.8V and -1.625V, ( outputs unterminated ), around -1.2V common

mode voltage.

Three possible line driving and back-termination scenari os are proposed (assuming VPLUSD=0V) :

1 ) 75 Ohms impedance transmission lines, 75 ohms different i al l y termi nated (Fig. 3) :

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V

(respect i vel y +1.21V) common mode for VPLUSD=0V (respectively 2.4V).

2 ) 50 ohms impedance transmission li nes, 50 ohms different i al l y termi nation (Fi g. 4) :

Each output voltage vari es between -1.02V and -1.35V (respectively +1.3 8V and +1.05V), leading to +/- 0.33V=660 mV in differential, around -

1.18V (respectivel y +1. 21V) common mode for VPLUSD=0V (respectively 2.4V).

3 ) 75 ohms impedance open transmission lines (Fig. 5) :

Each output voltage vari es between -1.6 V and -0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, leading to +/- 0.8V=1.6V in

different i al, around -1. 2V (respect i vel y +1. 2V) c ommon mode for VPLUSD=0V (respectively 2.4V).

Therefore, it is possibl e to drive di rect l y high input impedance st ori ng registers, without terminating the 75 ohms transmissi on lines.

In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the

75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflecti on will occur.

Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance.

Each differential output termi nation l ength must be kept identical .

It is recommended to decouple the midpoint of the different i al term i nation with a 10 nF capacitor to avoid common mode perturbation in case of

slight mismatc h i n the differenti a l output line lengths.

Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor

leading to switchi ng ground noise.

The differential output volt age l evels ( 75 or 50 ohms termination ) are not ECL standard voltage level s, however it is possible to drive standard

logic ECL circuitry like the ECLinPS logic line from MOTOROLA.

Preliminary Spec ificat ion

ββ

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TS8308500

DIFFE RENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR ECL COMPATIBILITY)

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out -1V / -1.41V

OutB -1.41V / -1V

Differential out put :

± 0.41V = 0.825V

Common m ode level : -1.2V

(-1.2V below VPLUSD level)

Figure 3 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

-0.8V

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω50 Ω

50 Ω

impedance 10 nF

50 Ω

Out -1.02V / -1.35V

OutB -1.35V / -1.02V

Differential out put :

± 0.33V = 0.660V

Common m ode level : -1.2V

(-1.2V below VPLUSD level)

Figure 4 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

-0.8V

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

75 Ω

impedance

Out -0.8V / -1.6V

OutB -1.6V / -0.8V

Differential out put :

± 0.8V = 1.6V

Common mode level : -1.2V

(-1.2V bel ow V PLUSD level)

Figure 5 : DIFFERENTIAL OUTPUT : OPEN LOADED

-0.8V

34 TS8308500

Preliminary Spec ificat ion

ββ

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DIFFE RENTI AL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR LVDS COMPATIBILITY)

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out 1.4V / 0.99V

OutB 0.99V / 1 .4V

Differential out put :

± 0.41V = 0.825V

Common m ode level : -1.2V

(-1.2V below VPLUSD level)

Figure 6 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

1.6V

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω50 Ω

50 Ω

impedance 10 nF

50 Ω

Out 1.38V / 1.05V

OutB 1.05V / 1.38V

Differential out put :

± 0.33V = 0.660V

Common m ode level : -1.2V

(-1.2V below VPLUSD level)

Figure 7 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

1.6V

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω75 Ω

75 Ω

impedance

Out 1.6V / 0.8V

OutB 0.8V / 1.6 V

Differential out put :

± 0.8V = 1.6V

Common m ode level : -1.2V

(-1.2V below VPLUSD level)

Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED

1.6V

Preliminary Spec ificat ion

ββ

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TS8308500

7.7. OUT OF RANGE BIT

An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive f ull scale or falls bel ow the

negative full sc al e.

When the analog input exceeds the positive ful l scal e, the digital output data remai n at high logical stat e, with (OR, ORB) at logical one.

When the analog input falls below the negative full scal e, the digital outputs rem ai n at logic al low state, with (OR,ORB) at logical one agai n.

7.8. GRAY OR BINARY OUTPUT D AT A FORMAT SELECT

The TS8308500 internal regenerati on l atc hes indecisi on (for inputs very cl ose to latches threshold) may produce errors in the logic encoding

circuitry and l eadi ng to large ampli tude out put errors.

This is due to the fact that the latches are regenerating the internal analog resi dues i nt o logical states with a finite voltage gai n value (Av) withi n

a given positive amount of time ∆(t) :

Av= exp(∆(t)/τ) , with τ the positive feedback regenerati on tim e const ant.

The TS8308500 has been designed for reducing the probability of occurrenc e of such errors to approxim ately 10 -13 (target ed for the TS8308500

at 500 MSPS).

A standard technique for reduc i ng the amplitude of such errors down to +/-1 LSB consists to output the digit al data in Gray code f orm at.

Though the TS8308500 has been designed for featuring a Bit Error Rate of 10-13 with a binary output form at, it is possibl e for t he user to select

between the Binary or Gray output dat a format, in order to reduc e the amplitude of s uch errors when occu rri ng, by st ori ng Gray output codes.

Digital Data format selection :

BINARY output format if GORB is floating or VCC.

GRAY output format if GORB is connected to ground (0V).

7.9. DIODE PIN K1

One single pin is used for both DRRB input command and die junction monitori ng. The pin denomination is DRRB/ DIOD. Temperat ure

monitori ng and Data Ready c ontrol by DRRB is not poss i bl e simult aneously.

(See section 7.2 for Data Ready Res et input command).

The operating die junction tem perat ure must be kept below145°C, therefore an adequate cooling system has to be set up.

The diode mounted transistor measured Vbe value versus junction temperature is given below.

600

640

680

720

760

800

840

880

920

960

1000

-55 -35 -15 5 25 45 65 85 105 125

Junct i on temperature (deg.C)

VBE (mV)

36 TS8308500

Preliminary Spec ificat ion

ββ

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7.10. ADC GAIN CONTROL PIN K6

The ADC gain is adjustable by the means of the pin K6 (input impedance is 1MΩ in parallel with 2pF)

The gain adjust transfer function is gi ven bel ow :

0,80

0,85

0,90

0,95

1,00

1,05

1,10

1,15

1,20

-500 -400 -300 -200 -100 0 100 200 300 400 500

Vgain (com m and voltage) (mV )

ADC Gain

Preliminary Spec ificat ion

ββ

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TS8308500

8. EQUIVALENT INPUT / OUTPUT SCHEM ATICS

8.1. EQUIV ALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS

8.2. EQUIV ALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS

GND=0V

VCC=+5V VCLAMP= +2.4V

+1.65V

-1.55V

VEE VEE

VCC

GND

VIN VINB

VEE=-5V

Pad

capacitance

340fF

Pad

capacitance

340fF

-0.8V

-5.8V

5.8V

0.8V

200 Ω200 Ω

50 Ω50 Ω

Note : the ESD protection equival ent capac itance is 150 fF.

E21VE21V

-0.8V

-5.8V

VCC=+5V +0.8V

GND=0V

VEE

VEE=-5V

CLK

VCC

VEE

CLKB

Pad

capacitance

340fF

Pad

capacitance

340fF

-5.8V

-5.8V -5.8V

-5.8V

5.8V5.8V

0.8V 0.8V

150 Ω150 Ω

380 µA 380 µA

Note : the ESD protection equival ent capac itance is 150 fF.

38 TS8308500

Preliminary Spec ificat ion

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8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS

8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS

VPLUSD=0V to 2.4V

DVEE=-5V VEE=-5VVEE=-5V

VEE VEE

OUT OUTB

-5.8V -5.8V

5.8V 5.8V

0.8V

0.8V 0.8V

0.8V

I=11mA

75 Ω75 Ω

-3.7V

Pad

capacitance

180 fF

Pad

capacitance

180 fF

Note : the ESD protection equival ent capac itance is 150 fF.

VEE

VEE VEE=-5V

VCC=+5V

+1.6V

Pad

capacitance

180 fF

-0.8 V

-5.8 V

-0.8 V

-5.8 V

0.8V

5.8V

0.8V

5.8V

1 kΩ1 kΩ

2 pF 2 pF

GND GND

VEE

VCC

Pad

capacitance

180 fF

500 µA500

GA GAB

NP1032C2 NP1032C2

Note : the ESD protection equival ent capac itance is 150 fF.

Preliminary Spec ificat ion

ββ

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TS8308500

8.5. GORB EQUIV ALENT INPUT SCHEMATIC AND ESD PROTECTIONS

GORB: gray or binary select input; floating or tied to VCC -> binary

8.6. DRRB EQUIV ALENT INPUT SCHEMATIC AND ESD PROTECTIONS

VCC=+5V

VEE=-5V GND=0V

-0.8V

-5.8V

5.8V

5 kΩ

1 kΩ1 kΩ

1 kΩ

250

A 250

Pad

capacitance

180fF

GORB

VEE

Note : the ESD protection equival ent capac itance is 150 fF.

VEE=-5V

VEE

VCC=+5V

GND=0V

-1.3V

-2.6V

10 kΩ

200 Ω

DRRB

5.8 V

Pad

capacitance

180 fF

Actual protection range: 6.6V above VEE,

In fact stress above GND are clipped by

the CB diode used for Tj monitoring

0.8 V

NP1032C2

Note : the ESD protection equival ent capac itance is 150 fF.

40 TS8308500

Preliminary Spec ificat ion

ββ

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9. TSEV8308500G : DEVICE EVALUATION BOARD

For complete specification, see separate TSEV8308500 document.

GENERAL DESCRIPTION

The TSEV8308500 Evaluation Board (CEB) is a board which has been designed in order to facilit ate the evaluat i on and the characteri zat i on of

the TS8308500 device up to its 1.3 GHz full power bandwidth at up to 500 Msps in the commercial temperature range.

The high speed of the TS8308500 requires careful attention t o circ uit design and layout t o achieve opti m al perform ance.

This four metal layer board with internal ground pl ane has the adequate functi ons i n order to allow a quick and simple evaluation of the

TS8308500 ADC performances over the temperat ure range.

The TSEV8308500 Evaluation Board is very straightforward as it only implements the TS8308500 ADC, SMA connectors for input / output

access es and a 2.54 mm pitch connector compati bl e with HP16500C high frequenc y probes.

The board also implements a de–embedding fixture in order to fac ili tate the evaluation of the high frequency inserti on loss of t he i nput microst ri p

lines, and a die junction temperature measurem ent s ett i ng.

The board is constituted by a sandwich of two dielectri c l ayers, featuring low insertion loss and enhanced thermal charact eris tics for operation in

the high frequency domai n and extended temperat ure range.

The board dimensions are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8308500 and its heatsink installed.

Preliminary Spec ificat ion

ββ

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TS8308500

10. ORDERING INFORMATION

10.1. PACKAGE DEVICE

10.2. EVALUATION BOARD

The evaluation board is delivered with an ADC and incl udes the heat sink.

Manufacturer prefix

Device or family

Temperature range : Package :

C : 0 < Tc ; Tj < 90°CG : CBGA72 with C and R

TS 8308500 C G

Screening level :

___ : standard

TSEV 8308500 G ZA2

• ZA2 : with MC100EL16

digital recei vers

• ---- : No digital receiver

Evaluation board pref i x G : CBGA72 with C and R

42 TS8308500

Preliminary Spec ificat ion

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-site

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