Features
•
Fast Read Access Time – 120 ns
•
Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
•
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
•
Low Power Dissipation
– 40 mA Active Current
– 200 µA CMOS Standby Current
•
Hardware and Software Data Protection
•
DATA Polling for End of Write Detection
•
High Reliability CMOS Technology
– Endurance: 10
4
or 10
5
Cycles
– Data Retention: 10 Years
•
Single 5V ± 10% Supply
•
CMOS and TTL Compatible Inputs and Outputs
•
JEDEC Approved Byte-wide Pinout
•
Industrial Temperature Ranges
•
Green (Pb/Halide-free) Packaging Option
1. Description
The AT28C010 is a high-performance electrically-erasable and programmable read-
only memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Man-
ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 200 µA.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28C010 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
128 bytes of EEPROM for device identification or tracking.
1-megabit
(128K x 8)
Paged Parallel
EEPROM
AT28C010
0353G–PEEPR–10/06
2
0353G–PEEPR–10/06
AT28C010
2. Pin Configurations
2.1 32-lead TSOP Top View
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2.2 32-lead PDIP Top View
2.3 32-lead PLCC Top View
Note: PLCC package pin 1 is Don’t Connect.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
DC
VCC
WE
NC
3
0353G–PEEPR–10/06
AT28C010
3. Block Diagram
4. Device Operation
4.1 Read
The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
WC
, a read operation will effectively be a polling operation.
4.3 Page Write
The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 127 additional
bytes. Each successive byte must be written within 150 µs (t
BLC
) of the previous byte. If the
t
BLC
limit is exceeded the AT28C010 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the
page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
4.4 DATA Polling
The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O
7
. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
4
0353G–PEEPR–10/06
AT28C010
4.5 Toggle Bit
In addition to DATA Polling the AT28C010 provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
®
has incorporated both hardware and software features that will protect
the memory against inadvertent writes.
4.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28C010 in the following ways:
(a) V
CC
sense – if V
CC
is below 3.8V (typical) the write function is inhibited; (b) V
CC
power-on
delay – once V
CC
has reached 3.8V the device will automatically time out 5 ms (typical) before
allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter—pulses of less than 15 ns (typical) on the WE or CE inputs will not
initiate a write cycle.
4.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28C010. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP
disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after t
WC
the entire AT28C010 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C010. This is done by preceding the data to
be written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power
transitions do not disable SDP and SDP will protect the AT28C010 during power-up and
power-down conditions. All command sequences must conform to the page write timing spec-
ifications. The data in the enable and disable command sequences is not written to the device
and the memory addresses used in the sequence may be written with data in either a byte or
page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device; however, for the dura-
tion of t
WC
, read operations will effectively be polling operations.
4.7 Device Identification
An extra 128 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be
written to or read from in the same manner as the regular memory array.
4.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see Software Chip
Erase application note for details.
5
0353G–PEEPR–10/06
AT28C010
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
5. DC and AC Operating Range
AT28C010-12 AT28C010-15
Operating Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C
V
CC
Power Supply 5V ± 10% 5V ± 10%
6. Operating Modes
Mode CE OE WE I/O
Read V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit V
IH
X
(1)
X High Z
Write Inhibit X X V
IH
Write Inhibit X V
IL
X
Output Disable X V
IH
X High Z
7. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
8. DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
Input Load Current V
IN
= 0V to V
CC
+ 1V 10 µA
I
LO
Output Leakage Current V
I/O
= 0V to V
CC
10 µA
I
SB1
V
CC
Standby Current CMOS CE = V
CC
- 0.3V to V
CC
+ 1V 200 µA
I
SB2
V
CC
Standby Current TTL CE = 2.0V to V
CC
+ 1V 3 mA
I
CC
V
CC
Active Current f = 5 MHz; I
OUT
= 0 mA 40 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 2.1 mA 0.45 V
V
OH1
Output High Voltage I
OH
= -400 µA 2.4 V
V
OH2
Output High Voltage CMOS I
OH
= -100 µA; V
CC
= 4.5V 4.2 V
6
0353G–PEEPR–10/06
AT28C010
10. AC Read Waveforms
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
9. AC Read Characteristics
Symbol Parameter
AT28C010-12 AT28C010-15
UnitsMin Max Min Max
t
ACC
Address to Output Delay 120 150 ns
t
CE(1)
CE to Output Delay 120 150 ns
t
OE(2)
OE to Output Delay 0 50 0 55 ns
t
DF(3)(4)
CE or OE to Output Float 0 50 0 55 ns
t
OH
Output Hold from OE, CE or Address, Whichever
Occurred First 00ns
8
0353G–PEEPR–10/06
AT28C010
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
14. AC Write Characteristics
Symbol Parameter Min Max Units
t
AS
, t
OES
Address, OE Set-up Time 0 ns
t
AH
Address Hold Time 50 ns
t
CS
Chip Select Set-up Time 0 ns
t
CH
Chip Select Hold Time 0 ns
t
WP
Write Pulse Width (WE or CE)100ns
t
DS
Data Set-up Time 50 ns
t
DH
, t
OEH
Data, OE Hold Time 0 ns
9
0353G–PEEPR–10/06
AT28C010
17. Page Mode Write Waveforms
(1)(2)
Notes: 1. A7 through A16 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
16. Page Mode Characteristics
Symbol Parameter Min Max Units
t
WC
Write Cycle Time 10 ms
t
AS
Address Set-up Time 0 ns
t
AH
Address Hold Time 50 ns
t
DS
Data Set-up Time 50 ns
t
DH
Data Hold Time 0 ns
t
WP
Write Pulse Width 100 ns
t
BLC
Byte Load Cycle Time 150 µs
t
WPH
Write Pulse Width High 50 ns
t
S
= 5 µsec (min.)
t
W
= t
H
= 10 msec (min.)
V
H
= 12.0V ± 0.5V
10
0353G–PEEPR–10/06
AT28C010
19. Software Data Protection
Enable Algorithm
(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 128 bytes of data are loaded.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS ENTER DATA
PROTECT STATE
WRITES ENABLED(2)
20. Software Data Protection
Disable Algorithm
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT DATA
PROTECT STATE(3)
21. Software Protected Write Cycle Waveforms
(1)(2)(3)
Notes: 1. A0 through A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
11
0353G–PEEPR–10/06
AT28C010
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
23. Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
25. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
22. Data Polling Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
Data Hold Time 10 ns
t
OEH
OE Hold Time 10 ns
t
OE
OE to Output Delay
(2)
ns
t
WR
Write Recovery Time 0 ns
24. Toggle Bit Characteristics
(1)
Symbol Parameter Min Typ Max Units
t
DH
Data Hold Time 10 ns
t
OEH
OE Hold Time 10 ns
t
OE
OE to Output Delay
(2)
ns
t
OEHP
OE High Pulse 150 ns
t
WR
Write Recovery Time 0 ns
12
0353G–PEEPR–10/06
AT28C010
26. Ordering Information
(1)
Note: 1. See “Valid Part Numbers” on page 13.
26.1 Standard Package
t
ACC
(ns)
I
CC
(mA)
Ordering Code Package Operation RangeActive Standby
120 40 0.2
AT28C010(E)-12JI
AT28C010(E)-12PI
AT28C010(E)-12TI
32J
32P6
32T Industrial
(-40° to 85°C)
150 40 0.2
AT28C010(E)-15JI
AT28C010(E)-15PI
AT28C010(E)-15TI
32J
32P6
32T
26.2 Green Package Option (Pb/Halide-free)
t
ACC
(ns)
I
CC
(mA)
Ordering Code Package Operation RangeActive Standby
120 40 0.2
AT28C010-12JU
AT28C010-12TU
32J
32T
Industrial
(-40° to 85°C)
AT28C010(E)-12JU
AT28C010(E)-12PU
AT28C010(E)-12TU
32J
32P6
32T
150 40 0.2
AT28C010-15JU
AT28C010-15TU
32J
32T
AT28C010(E)-15JU
AT28C010(E)-15PU
AT28C010(E)-15TU
32J
32P6
32T
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP)
W
Die
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
EHigh-endurance Option: Endurance = 100K Write Cycles
13
0353G–PEEPR–10/06
AT28C010
27. Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28C010 12 JI, JU, PI, TI, TU, PU
AT28C010E 12 JI, PI, TI, JU, PU, TU
AT28C010 15 JI, JU, PI, TI, TU, PU
AT28C010E 15 JI, PI, TI, JU, PU, TU
28. Die Products
Reference Section: Parallel EEPROM Die Products
14
0353G–PEEPR–10/06
AT28C010
29. Packaging Information
29.1 32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
15
0353G–PEEPR–10/06
AT28C010
29.2 32P6 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
32P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.826
A1 0.381 – –
D 41.783 – 42.291 Note 1
E 15.240 – 15.875
E1 13.462 – 13.970 Note 1
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
16
0353G–PEEPR–10/06
AT28C010
29.3 32T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
32T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
Printed on recycled paper.
0353G–PEEPR–10/06
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High-Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
© 2006 Atmel Corporation. All rights reserved. Atmel
®
, logo and combinations thereof, Everywhere You Are
®
and others are registered trade-
marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
