APPLICATION NOTES A V A I L A B L E AN99 * AN115 * AN120 * AN124 * AN133 * AN134 * AN135 Low Noise/Low Power/2-Wire Bus X9409 Preliminary Information Quad Digitally Controlled Potentiometers (XDCPTM) FEATURES DESCRIPTION * Four potentiometers per package * 64 resistor taps * 2-wire serial interface for write, read, and transfer operations of the potentiometer * 50 Wiper resistance, typical at 5V. * Four non-volatile data registers for each potentiometer * Non-volatile storage of multiple wiper position * Power on recall. Loads saved wiper position on power up. * Standby current < 1A typical * System VCC: 2.7V to 5.5V operation * 10K, 2.5K End to end resistance * 100 yr. data retention * Endurance: 100,000 data changes per bit per register * Low power CMOS * 24-lead SOIC, 24-lead TSSOP, and 24-lead CSP (Chip Scale Package) Packages The X9409 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Pot 0 VCC R0 R1 VSS R2 R3 WP SCL SDA A0 A1 A2 A3 Interface and Control Circuitry VH0/RHO R0 R1 VL0/ RLO R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 2 VH2/RH2 VL2/RL2 VW0/ RWO VW2/RW2 VW1/ RW1 VW3/RW3 8 Data R0 R1 R2 R3 REV 1.6 1/30/03 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/ RH1 R0 R1 VL1/RL1 R2 R3 www.xicor.com Wiper Counter Register (WCR) Resistor Array Pot 3 VH3/RH3 VL3/RL3 Characteristics subject to change without notice. 1 of 21 X9409 - Preliminary Information PIN DESCRIPTIONS VW0/RW0-VW3/RW3 The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9409. Hardware Write Protect Input (WP) Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. PIN NAMES The WP pin when low prevents nonvolatile writes to the Data Registers. Symbol Device Address (A0-A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9409. A maximum of 16 devices may occupy the 2-wire serial bus. Description SCL Serial Clock SDA Serial Data A0-A3 Device Address VH0/RH0-VH3/RH3, VL0/RL0-VL3/RL3 Potentiometer Pin (terminal equivalent) VW0/RW0-VW3/RW3 Potentiometer Pin (wiper equivalent) WP Hardware Write Protection VCC System Supply Voltage VSS System Ground (Digital) NC No Connection Potentiometer Pins VH0/RH0-VH3/RH3, VL0/RL0-VL3/RL3 The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. PIN CONFIGURATION SOIC CSP VCC 1 24 NC VL0/RL0 2 23 VL3/RL3 VH0/RH0 3 22 VH3/RH3 21 VW3/RW3 VW0/RW0 4 5 A2 WP 6 SDA 7 A1 8 X9409 20 A0 19 NC 18 A3 17 SCL VL1/RL1 9 16 VL2/RL2 VH1/RH1 10 15 VH2/RH2 VW1/RW1 V SS 11 14 12 13 REV 1.6 1/30/03 VW2/RW2 NC 1 A B C D E F VW0/RW0 VL0/RL0 TSSOP 2 3 A2 A1 WP SDA 4 VL1/RL1 VW1/RW1 VH0/RH0 VH1/RH1 VCC VSS VH3/RH3 VH2/RH2 NC VL3/RL3 VW3/RW3 NC A0 A3 NC VW2/RW2 SCL VL2/RL2 Top View-Bumps Down www.xicor.com SDA 1 24 WP A1 2 23 A2 VL1/RL1 VH1/RH1 3 22 VW0/RW0 4 21 VH0/RH0 VW1/RW1 5 20 VL0/RL0 VSS 6 19 VCC X9409 NC 7 18 NC VW2/RW2 8 17 VL3/RL3 VH2/RH2 9 16 VH3/RH3 VL2/RL2 10 15 VW3/RW3 SCL 11 14 A0 12 13 NC A3 Characteristics subject to change without notice. 2 of 21 X9409 - Preliminary Information PRINCIPLES OF OPERATION The X9409 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9409 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9409 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9409 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9409 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. REV 1.6 1/30/03 The X9409 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9409 will respond with a final acknowledge. Array Description The X9409 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9409 this is fixed as 0101[B]. Figure 1. Slave Address Device Type Identifier 0 1 0 1 A3 A2 A1 A0 Device Address The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9409 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9409 to respond with an acknowledge. The A0-A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. www.xicor.com Characteristics subject to change without notice. 3 of 21 X9409 - Preliminary Information Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9409 is still busy with the write operation no ACK will be returned. If the X9409 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence Issue START ACK Returned? Issue STOP NO YES Further Operation? YES Issue STOP Proceed Proceed I3 I2 I1 Instructions I0 R1 R0 P1 P0 Pot Select The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9409; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. NO Issue Instruction Register Select Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Nonvolatile Write Command Completed Enter ACK Polling Issue Slave Address Figure 2. Instruction Byte Format Instruction Structure The next byte sent to the X9409 contains the instruction and register pointer information. The format is shown in Figure 2. REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 4 of 21 X9409 - Preliminary Information Figure 3. Two-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 The Increment/Decrement command is different from the other commands. Once the command is issued and the X9409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one I2 I1 I0 R1 R0 P1 P0 A C K S T O P resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Table 1. Instruction Set I3 I2 Instruction Set I1 I0 R1 R0 P1 P0 Operation 1 0 0 1 0 0 P1 P0 1 0 1 0 0 0 P1 P0 1 0 1 1 R1 R0 P1 P0 Write Data Register 1 1 0 0 R1 R0 P1 P0 XFR Data Register to Wiper Counter Register 1 1 0 1 R1 R0 P1 P0 XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register 1 1 1 0 R1 R0 P1 P0 0 0 0 1 R1 R0 0 0 1 0 0 0 R1 R0 0 0 0 0 1 0 0 0 P1 P0 Read the contents of the Wiper Counter Register pointed to by P1-P0 Write new value to the Wiper Counter Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective Data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the WCR Latch pointed to by P1-P0 Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Note: (7) 1/0 = data is one or zero REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 5 of 21 X9409 - Preliminary Information Figure 4. Three-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P Figure 5. Increment/Decrement Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued tWRID SCL SDA VW/RW REV 1.6 1/30/03 Voltage Out www.xicor.com Characteristics subject to change without notice. 6 of 21 X9409 - Preliminary Information Figure 7. Acknowledge Response from Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver START Acknowledge Figure 8. Detailed Potentiometer Block Diagram Serial Data Path Serial Bus Input From Interface Circuitry Register 0 If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH C o u n t e r Register 1 8 Register 2 VH/RH 6 Parallel Bus Input Wiper Counter Register (WCR) Register 3 D e c o d e INC/DEC Logic UP/DN Modified SCL UP/DN VL/RL CLK VW/RW REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 7 of 21 X9409 - Preliminary Information DETAILED OPERATION All XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and 4 Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9409 contains four Wiper Counter Registers, one for each XDCP potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of the four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9409 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. REV 1.6 1/30/03 If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-Bit), Nonvolatile: D5 D4 D3 D2 D1 NV NV NV NV NV (MSB) D0 NV (LSB) Four 6-bit Data Registers for each XDCP. (sixteen 6-bit registers in total). - {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. Wiper Counter Register, (6-Bit), Volatile: WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V (MSB) (LSB) One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers in total.) - {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register R0. The contents of the WCR can be loaded from any of the other Data Register or directly by command. The contents of the WCR can be saved in a DR. www.xicor.com Characteristics subject to change without notice. 8 of 21 X9409 - Preliminary Information Instruction Format Notes: (1) (2) (3) (4) (5) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 1 0 0 1 0 0 1 0 wiper position S (sent by slave on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 M A C K S T O P wiper position S (sent by master on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 S A C K S T O P Write Wiper Counter Register (WCR) S device type device identifier addresses T A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 1 0 1 0 0 0 1 0 Read Data Register (DR) device S device type identifier addresses T A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR and WCR S opcode addresses A C R R P P K 1 0 1 1 1 0 1 0 wiper position S (sent by slave on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 M A C K S T O P Write Data Register (DR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C R R P P R 0 1 0 1 A A A A 1 1 0 0 3 2 1 0 K 1 0 1 0 T wiper position S (sent by master on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P Transfer Data Register (DR) to Wiper Counter Register (WCR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C R R P P R 0 1 0 1 A A A A 1 1 0 1 3 2 1 0 K 1 0 1 0 T S A C K S T O P Write Wiper Counter Register (WCR) to Data Register (DR) S device type device addresses T identifier A R 0 1 0 1 A A A A 3 2 1 0 T REV 1.6 1/30/03 instruction DR and WCR S opcode addresses A C R R P P 1 1 1 0 K 1 0 1 0 S A C K S T O P www.xicor.com HIGH-VOLTAGE WRITE CYCLE Characteristics subject to change without notice. 9 of 21 X9409 - Preliminary Information Increment/Decrement Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 0 0 1 0 0 0 1 0 increment/decrement S (sent by master on SDA) A C I/ I/ I/ I/ K D D . . . . D D S T O P Global Transfer Data Register (DR) to Wiper Counter Register (WCR) S device type device identifier addresses T A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR S opcode addresses A C R R K 0 0 0 1 1 0 0 0 S A C K S T O P Global Transfer Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR S opcode addresses A C R R 1 0 0 0 0 0 K 1 0 SYMBOL TABLE WAVEFORM S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance 120 REV 1.6 1/30/03 Resistance (K) 100 80 60 V RMIN = CC MAX =1.8K IOL MIN RMAX = tR CBUS Max. Resistance 40 20 Min. Resistance 0 0 20 40 60 80 100 120 Bus Capacitance (pF) www.xicor.com Characteristics subject to change without notice. 10 of 21 X9409 - Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature under bias ....................-65C to +135C Storage temperature .........................-65C to +150C Voltage on SDA, SCL or any address input with respect to VSS ......................... -1V to +7V V = |VH - VL |........................................................ 5V Lead temperature (soldering, 10 seconds).........300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Device Supply Voltage (VCC) Limits Commercial 0C +70C X9409 5V 10% Industrial -40C +85C X9409-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Typ. Max. Unit Test Conditions End to end resistance tolerance 20 % Power rating 15 mW +3 mA 150 IW = 3mA, VCC = 3V to 5V VCC V VSS = 0V -120 dBV Ref: 1kHz 1.6 % IW Wiper current RW Wiper resistance VTERM Min. -3 50 Voltage on any VH/RH or VL/RL pin VSS Noise Resolution (4) Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL -1 +1 -0.2 +0.2 300 Ratiometric temp. coefficient Potentiometer capacitances 10/10/25 IAL RH, RL, RW leakage current 0.1 (3) MI Vw(n)(actual)--Vw(n)(expected) Vw(n + 1)--[Vw(n) + MI] ppm/C 20 CH/CL/CW MI(3) 25C, each pot @5V, 2.5K 10 ppm/C pF See Macro Model A VIN = VSS to VCC. Device is in stand-by mode. Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH--VL)/63, single pot REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 11 of 21 X9409 - Preliminary Information D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. ICC1 VCC supply current (Active) ICC2 Typ. Max. Unit Test Conditions 100 A fSCL = 400kHz, SDA = Open, Other Inputs = VSS VCC supply current (Nonvolatile Write) 1 mA fSCL = 400kHz, SDA = Open, Other Inputs = VSS ISB VCC current (standby) 1 A SCL = SDA = VCC, Addr. = VSS ILI Input leakage current 10 A VIN = VSS to VCC ILO Output leakage current 10 A VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V VIL Input LOW voltage -0.5 VCC x 0.1 V VOL Output LOW voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years CAPACITANCE Symbol (4) (4) CI/O CIN Test Max. Unit Test Conditions Input/output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V POWER-UP TIMING Symbol tr VCC(6) Parameter VCC power-up rate Min. Max. Unit 0.2 50 V/ms POWER UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, RH, RL, and RW. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC reaches its final value. Notes: (4) This parameter is periodically sampled and not 100% tested (5) tPUR and tPUW are the delays required from the time the (last) power supply (VCC) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) Sample tested only. REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 12 of 21 X9409 - Preliminary Information A.C. TEST CONDITIONS Circuit #3 SPICE Macro Model Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 RTOTAL RH RL CL CH CW 10pF EQUIVALENT A.C. LOAD CIRCUIT 10pF 25pF 5V RW 1533 SDA Output 100pF AC TIMING (over recommended operating condition) Symbol Parameter fSCL Clock frequency tCYC Clock cycle time tHIGH tLOW Min. Max. Unit 400 kHz 2500 ns Clock high time 600 ns Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns tR SCL and SDA rise time tF 300 ns SCL and SDA fall time 300 ns tAA SCL low to SDA data output valid time 900 ns tDH SDA data output hold time 50 ns Noise suppression time constant at SCL and SDA inputs 50 ns 1300 ns TI tBUF Bus free time (prior to any transmission) tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR REV 1.6 1/30/03 Parameter High-voltage write cycle time (store instructions) www.xicor.com Typ. Max. Unit 5 10 ms Characteristics subject to change without notice. 13 of 21 X9409 - Preliminary Information XDCP TIMING Symbol Typ. Max. Unit Wiper response time after the third (last) power supply is stable 2 10 s tWRL Wiper response time after instruction issued (all load instructions) 2 10 s tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 2 10 s tWRPO Note: Parameter Min. (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS START and STOP Timing g (START) (STOP) tF tR SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tDH tAA REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 14 of 21 X9409 - Preliminary Information XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx XDCP Timing (for Increment/Decrement Instruction) SCL SDA Wiper Register Address Inc/Dec Inc/Dec tWRID VW/RW Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 A2, A3 REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 15 of 21 X9409 - Preliminary Information APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS - + VO 100K - VO + } } TL072 R1 R2 10K 10K 10K VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) VS REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 16 of 21 X9409 - Preliminary Information Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO - - R VO + R3 R4 R2 All RS = 10k R1 GO = 1 + R2/R1 fc = 1/(2pRC) VO = G VS -1/2 G +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 - VS VO + + - R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 - + R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 17 of 21 X9409 - Preliminary Information PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45 0.020 (0.50) 0.050" Typical 0 - 8 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 18 of 21 X9409 - Preliminary Information PACKAGING INFORMATION 24-Lead Plastic, TSSOP Package Type V .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0-8 (4.16) (7.72) Seating Plane .020 (.50) .030 (.75) (1.78) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) ALL MEASUREMENTS ARE TYPICAL See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 19 of 21 X9409 - Preliminary Information PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing a 9409WRR YWW I2.7 LOT # f j m A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 F4 F3 F2 b F1 e k l Top View (Sample Marking) d Bottom View (Bumped Side) Side View e c Side View Package Dimensions Ball Matrix: Min Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter Ball Pitch - Width Ball Pitch - Length Ball to Edge Spacing - Width Ball to Edge Spacing - Length REV 1.6 1/30/03 Symbol a b c d e f j k l m 2.595 3.814 0.644 0.444 0.200 0.300 0.538 0.647 Nominal Millimeters 2.625 3.844 0.677 0.457 0.220 0.320 0.5 0.5 0.563 0.672 Max 2.655 3.874 0.710 0.470 0.240 0.340 A B C D E F X9409W/X9409Y 4 3 2 RL1 A1 A2 RW1 SDA WP VSS RH1 RH0 NC RH2 RH3 RW2 A3 NC RL2 SCL A0 1 RW0 RL0 VCC NC RL3 RW3 0.588 0.697 www.xicor.com Characteristics subject to change without notice. 20 of 21 X9409 - Preliminary Information Ordering Information X9409 Device Y P T V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP B241 = 24-Lead CSP Z24 = 24-Lead XBGA Contact Factory for Availability Potentiometer Organization Pot 0 Pot 1 Pot 2 Pot 3 W= 10K 10K 10K 10K Y= 2.5K 2.5K 2.5K 2.5K LIMITED WARRANTY (c)Xicor, Inc. 2003 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.6 1/30/03 www.xicor.com Characteristics subject to change without notice. 21 of 21