1-1659577-0 - TE CONNECTIVITY

FN6264.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL97634

White LED Driver with Wide PWM

Dimming Range

The ISL97634 represents an efficient and highly integrated

PWM boost LED driver that is suitable for 1.8” to 3.5” LCDs

that emplo y 2 to 7 whi t e LED s fo r ba ckl ig h t i n g. Wit h

integrated Schottky diode, OVP, and wide range of PWM

dimming capability, the ISL97634 provides a simple, reliable,

and flexible solution to the backlight designers.

The ISL97634 features a wide range of PWM dimming

control capability. It allows dimming frequency as low as DC

to 32kHz beyond audible spectrum. The ISL97634 al so

features a feedback disconnect switch to prevent the output

from being modulated by the PWM dimming signal that

minimizes system disturbance.

The ISL97634 is available in the 8 Ld TDFN (2mmx3mm)

package. There are 14V, 18V, and 26V OVP options that are

suitable for 3 LEDS, 4 LEDs, and 7 LEDs (3.5V/20mA type)

backlight applications respecti vely. The ISL97634 is

specified for operation over the -40°C to +85°C ambient

temperature at input voltage from 2.4V to 5.5V.

Pinout ISL97634

(8 LD TDFN)

TOP VIEW

Typical Application Circuit

Features

• Drives Up to 7 LEDs in Series (3.5V/20mA type)

• OVP (14V, 18V, and 26V for 3, 4 and 7 LEDs Applications)

• PWM Dimming Control From DC to 32kHz

• Output Disconnect Switch

• Integrated Schottky Diode

• 2.4V to 5.5V Input

• 85% Ef fi ci en cy

• 1.4MHz Switching Frequency Allows Small LC

• 1µA Shutdown Current

• Internally Compensated

• 8 Ld TDFN (2mmx3mm)

• Pb-Free (RoHS Compliant)

Applications

• LED Backlighting for:

- Cell phones

- Smartphones

-MP3

-PMP

- Automotive Navigation Panel

- Portable GPS

GND

VIN

PWM/EN

VOUT

FBSW

VIN

FBSW

GND

VIN

PWM/EN

VOUT

10µH or 22µH

Ordering Information

PART

NUMBER

(Note) PART

MARKING

PACKAGE

(Pb-free)

Tape & Reel

PKG.

DWG.

ISL97634IRT14Z-T ELE 8 Ld 2x3 TDFN L8.2x3A

ISL97634IRT14Z-TK ELE 8 Ld 2x3 TDFN L8.2x3A

ISL97634IRT18Z-T ELF 8 Ld 2x3 TDFN L8.2x3A

ISL97634IRT18Z-TK ELF 8 Ld 2x3 TDFN L8.2x3A

ISL97634IRT26Z-T ELG 8 Ld 2x3 TDFN L8.2x3A

ISL97634IRT26Z-TK ELG 8 Ld 2x3 TDFN L8.2x3A

*Please refer to TB347 for details on reel specifications

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets; molding compounds/die attach

materials and 100% matte tin plate PLUS ANNEAL - e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-fr ee products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020..

Data Sheet March 7, 2008

2FN6264.3

March 7, 2008

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V

LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 28V

FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 28V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.3V to 6V

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance θJA (°C/W) θJC (°C/W)

8 Ld TDFN Package (Notes 1, 2). . . . . 77 12

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40°C to +85°C unless otherwise stated. Typ values are for

information purposes only at TJ = TC = TA = +25°C.

NOTE:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VIN = VPWM/EN = 3V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

VIN Supply Voltage 2.4 5.5 V

IIN Supply Current PWM/EN = 3V, enabled, not switching 0.8 1.5 mA

PWM/EN = 0V, disabled 1 µA

fSW Switching Frequency 1,300 1,450 1,600 kHz

DMAX Maximum Switching Duty

Cycle 90 95 %

ILIM LX Current 400 470 mA

RSW(LX) LX Switch ON-Resistance ILX = 100mA 900 mΩ

ILEAK LX Sw itch Leakage Current VLX = 28V 0.01 1 µA

VFB Feedback Voltage 90 95 100 mV

IFB FB Pin Bias Current VFB = 95mV 1 µA

RSW(FBSW) FBSW Switch ON-Resistance 10 Ω

VDIODE Schottky Diode Forward

Voltage IDIODE = 100mA, TA = +25°C 600 850 mV

OVP Overvoltage Protection ISL97634IRT14Z 14 V

ISL97634IRT18Z 18 V

ISL97634IRT26Z 26 28 V

VIL Logic Low Voltage of

PWM/EN 0.6 V

VIH Logic High Voltage of

PWM/EN 1.5 V

PWM_on Minimum PWM On-Time 1.5 µs

EN_delay EN to Vout Delay 200 µs

ISL97634

3FN6264.3

March 7, 2008

Block Diagram

Pin Description

PIN NUMBER PIN NAME DESCRIPTION

1 GND Ground Pin. Connect to local grou nd.

2 VIN Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling capacitor .

3 PWM/EN PWM or Enable Pin. Connect external PWM signal allows pulse width modulation curren t operation. Enable

signal allows peak current operation or disable signa l sh uts down the device.

4 NC No Connect

5 FB Feedback Pin. Connect the sense resistor between FB an d gro und. The ca thode of bottom LED ca n also

be connected at th is pin if th e ou tput current is not to b e P WMe d.

6 FBSW FB Disconnect Switch. Connect to the cathode of the bottom LED if the output current to be PWMed.

7 VOUT Output Pin. Connect to t he a node of the top LED and the out put filter capacitor.

8 LX Sw it chin g P in. Con nect t o indu ct or.

FET PWM LOGIC

CONTROLLER

AMPLIFIER 95mV

GM AMP

COMPENSATION

PWM

COMPARATOR

VIN PWM/EN LX

GND

RSET

COUT

VIN (2.4V TO 5.5V)

2 LEDs to 7 LEDS

CIN

ISL97634

VOUT

BANDGAP

REFERENCE

GENERATOR

FBSW

PWM/EN

DRIVER

GM AMP

COMPENSATION

CURRENT

SENSE

1.4MHZ OSCILLATOR AND RAMP

GENERATOR

ISL97634

4FN6264.3

March 7, 2008

Typical Performance Curves

FIGURE 1. EFFICIENCY vs PWM DUTY CYCLE FIGURE 2. QUIESCENT CURRENT vs VIN (PWM/EN = HI)

FIGURE 3. LOAD REGULATION (VIN = 4V) FIGURE 4. LINE REGULATION

FIGURE 5. DIMMNG LINEARITY (FB VOL TAGE) vs DUTY

CYCLE FIGURE 6. PWM DIMMING AT 1kHz, D = 1%

0 20406080100

EFFICIENCY (%)

PWM DUTY CYCLE (%)

3 LEDs, 10µH

3 LEDs, 22µH 7 LEDs, 10µH

7 LEDs, 22µH

4 LEDs, 10µH

VIN = 4V

RSET = 4Ω

fPWM = 1kHz

ILED_peak = 25mA

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0246

Iq (mA)

135

VIN (V)

19.92

19.96

20.00

20.04

20.08

0 5 10 15 20 25 30

IO (mA)

VOUT (V)

19.62

19.64

19.66

19.68

19.70

19.72

19.74

19.76

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V)

IO (mA)

100

0 20 40 60 80 100 120

DUTY CYCLE (%)

7 LEDs

VIN = 4V

RSET = 4Ω

L = 10µH

FB VOLTAGE (mV)

20kHz

32kHz

1kHz

ILED

PWM/EN

OUT

VIN = 4V

R1 = 4Ω

L1 = 22µH

ISL97634

5FN6264.3

March 7, 2008

Detailed Description

The ISL97634 uses a constant frequency, current mode

control scheme to provide excellent line and load

reg ul ation. There are three OVP models for driving 3, 4

and 7 LEDs (3.5V/20mA type) and their OVP thresholds

are set at 14V, 18V and 26V respectively. The ISL97634

operates from an input voltage of 2.4V to 5.5V and ambient

temperature from -40°C to +85°C. The switching frequency

is around 1.45MHz and allows the driver circuit to employ

small LC components. The peak forward current of the LED

is set using the RSET resisto r. In the steady state mode, the

LED peak current is given by Equation1:

PWM Dimming

The ISL97634’s PWM/EN pin can be tied permanently to

high for a fixed current operation. On the other hand, the

ISL97634 can be applied with an external PWM signal to

pulse width modulated output current. It is well understood

that the LED brightness is a linear function of the LED

current. In addition, the average LED current corresponds to

the duty cycle “D” of the PWM signal as shown in

Equation 2:

As a result, PWM signal provides a means to dim the LED

brightness. PWM dimming offers the best LEDs matching

over DC dimming. It is because the LED peak current

operating point is far away from the knee of the diode I-V

curve where part to part variations are high. The PWM

dimming test results are shown in Figure 6 with two PWM

frequencies, 1kHz and 20kHz. Th e vertical scale parameter

FB is proportional to the current and therefore the

brightness.

For the ISL97634, PWM dimming provides linear dimming

adjustment with low frequency signal, such as 1kHz and

FIGURE 7. PWM DIMMING AT 1kHz, D = 1% ZOOM IN FIGURE 8. PWM DIMMING AT 1kHz, D = 99%

FIGURE 9. PWM DIMMING AT 20kHz, D = 50%

ILED

PWM/EN

VOUT

VIN = 4V

R1 = 4

L1 = 22µH ILED

PWM/EN

VOUT

VIN = 4V

R1 = 4

L1 = 22µH

ILED

PWM/EN

VOUT

VIN = 4V

L1 = 22µH

R1 = 4

ILED VFB

RSET

---------------

=(EQ. 1)

ILED-AVG VFB

RSET

--------------- D⋅=(EQ. 2)

ISL97634

6FN6264.3

March 7, 2008

below. The applied PWM dimming signal can be up to

32kHz; however, the dimming linearity is compromised at

low duty cycles as their durations are too short for the

ISL97634’s control loop to respond properly. This

non-ideality behavior does no t cause any functional

problem. The PWM dimming linear responses in Figure 5

are expanded in Figure 10. At 1kHz PWM dimming, the duty

cycle can virtually vary from below 1% to DC. On the other

hand, at 20kHz PWM dimming, the linearity range is from

5% to DC only.

The low level non-linearity effects at high frequency PWM

dimming is also reflected in the efficiency measurements in

Figure 11.

Feedback Disconnect Switch

The ISL97634 functions properly without using the FBSW.

However, the output capacitor will discharge during the PWM

off ti me resulting in poo r dimmin g line arity at low duty cycles.

The output discharge ef fe ct can be seen in Figure 12.

Moreover, the output is modulated by the PWM signal that

may create interference to other systems.

The FBSW should be used for PWM dimming as illustrated

in “Typical Application Circuit” on page 1. During the PWM

off time, the FBSW is opened. The LEDs are floating and

therefore the output capacitor has no path to discharge. The

LED current responds accurately with the PWM signal (see

Figure 13). The output switches very quickly to the target

current with minimal settling ringi ng and without being

modulated by the PWM signal, and therefore minimizes any

system disturbance.

Overvoltage Protection

The ISL97634 comes with ove rvolt age pro tectio n. The OVP

trip point s are at 14V, 18V and 26V for ISL97634IRT14Z,

ISL97634IR T18Z and ISL97634IRT26Z respectively. The

maximum numbers of LEDs a nd OVP threshold are shown in

Table 1. When the device reaches the OVP, the LX stops

switching, disabling the boost ci rcuit until VOUT falls about 7%

below the OVP threshold. At this point, LX will be allo wed to

switch again. The OVP event will not cause the device to

shutdown.

There are three OVP options so that the 3 LEDs application

should use the 14V OVP device and the 7 LEDs application

should use the 26V OVP device. An output capa citor that is

FIGURE 10. DIMMING LINEARITY vs DUTY CYCLES ZOOM IN

024681012

DUTY CYCLE (%)

7 LEDs

VIN = 4V

RSET = 4Ω

L = 10µH

FB VOLTAGE (mV)

20kHz

32kHz

1kHz

FIGURE 11. EFFICIENCY vs PWM DIMMING FREQUENCIES

0 5 10 15 20 25 30

ILED (mA)

EFFICIENCY (%)

= 4V

RSET = 4

L = 22µH

3 LEDs

ILED

PWM/EN

VOUT

VIN = 4V

R1 = 4Ω

L1 = 22µH

FIGURE 12. PWM DIMMING AT 1kHz WITHOUT USING FBSW

FIGURE 13. PWM DIMMING AT 1kHz USING FBSW

ILED

PWM/EN

VOUT

VIN = 4V

R1 = 4

L1 = 22µH

ISL97634

7FN6264.3

March 7, 2008

only rated for the required voltage range can therefore be

used, which will optimi ze the co mponent cost s in so me cases.

Shutdown

When PWM/EN is taken low the ISL97634 enters into the

power-down mode where the supply current is reduced to

less than 1µA. The device resumes normal when the

PWM/EN goes high.

Components Selection

The input capacitance is typically 0.22µF. The output

capacitor should be in the range of 0.22µF to 1µF. X5R or

X7R type of ceramic capacitors of the appropriate voltage

rating are recommended.

When choosing an inductor, make sure the average and

peak current ratings are adequate by using Equations 3, 4 an d

5 (80% efficiency assumed):

Where:

•ΔIL is the peak-to-peak inductor current ripple in Amps

• L is the inductance in H

•f

OSC is the switching frequency, typically 1.45MHz

The ISL97634 supports a wide range of inductance values

(10µH to ~82µH). For lower inductor values or lighter loads,

the boost inductor current may become disco ntinuous. For

high boost inductor values, the boost inductor current will be

in continuous mode.

In addition to the inductor value and switching frequency , the

input voltage, number of LEDs and the LED current also

affects whether the converter operates in continuous

conduction or discontinuous conduction mode.

Both operating modes are allowe d and normal. The

discontinuous conduction mode yields lower efficiency due

to higher peak current.

Compensation

The product of the output capacitor and the load create a

pole while the inductor creates a right hal f plane zero. Both

of these attributes degrade the phase margin but the

ISL97634 has internal compensati on network that ensures

the device operates reliably under the specified conditions.

The internal compensation and the highly integrated

functions of the ISL97634 make it a design friendly device to

be used in high volume, high reliability appl ications.

Applications

Analog Dimming

Analog dimming is usually not recommended because of the

brightness non-linearity at low leve ls dimming. However,

some systems are EMI or noise sensitive that analog

dimming may be more suitable than PWM dimming under

those situations. The ISL97632 is part of the same family as

the ISL97634 and has been designe d with a serial interface

to give access to 32 separate dimming levels. Alternatively

analog dimming can be achieved by applying a variable DC

voltage (VDim) at FB pin (see Figure 14) to adjust the LED

current. As the DC dimming signal voltage increases above

VFB, the voltages drop on R1 and R2 increase and the

voltage drop on RSET decreases. Thus, the LED current

decreases as shown in Equation 6:

If VDIM is taken below FB, the inverse will happen and the

brightness will increase.

The DC dimming signal voltage can be a variable DC voltage

from a POT, a DCP (Digitally Controlled Potentiometer), or a

DC voltage generated by filtering a high frequency PWM

control signal.

As brightness is directly proportional to LED currents, VDim

may be calculated for any desired “relative brightness” (F)

using Equation 7:

Where F = ILED (dimmed)/ILED (undimmed).

TABLE 1.

PART NO. OVP MAX NO. OF

LEDS MAX ILED

ISL97634IRT14Z 14V 3 70mA

ISL97634IRT18Z 18V 4 50mA

ISL97634IRT26Z 26V 7 30mA

ILAVG ILED VOUT

⋅

0.8 VIN

⋅

---------------------------------

=(EQ. 3)

ILPK ILAVG 1

---IL

Δ⋅+= (EQ. 4)

ΔVIN VOUT VIN

–()⋅

OUT fOSC

⋅⋅

---------------------------------------------------

=(EQ. 5)

ILED VFB R1R2

+()VDim R1

⋅–⋅

R2R⋅SET

--------------------------------------------------------------------------

=(EQ. 6)

FIGURE 14. ANALOG DIMMING CONTROL APPLICA TION

CIRCUIT

ISL97634

VIN LX

PWM FB

GND

22µH

0.22µF

RSET

4.75Ω

LEDs

1µF

VIN

3.3V

VDim

VOUT

3.3k

VDim R2

-------VFB 1R1

-------F–+

⎝⎠

⎜⎟

⎛⎞

⋅⋅=(EQ. 7)

ISL97634

8FN6264.3

March 7, 2008

These equations are valid for values of R1 and R2 such that

both R1>>RSET and R2>>RSET.

The analog dimming circuit can be tailored to a desired

relative brightness for different VDim ranges using

Equation 8.

Where VDim_max is the maximum VDim voltage and Fmin is

the minimum relative brightness (i.e., the brigh tn ess with

VDim_max applied).

i.e., VDim_max = 5V, Fmin = 10% (i.e., 0.1), R2 = 189k

i.e., VDim_max = 1V, Fmin = 10% (i.e., 0.1), R2 = 35k

Efficiency Improvement

Figure 1 shows the ef ficie ncy measure ment s du ring PWM

operation. The choice of the inductor ha s a significa nt imp act

on the power ef ficiency. As shown in Equation 4, the high er

the inductance, the lower the peak current, th erefore, the

lower the conduction and switch ing losses. On the other hand,

it has also a higher serie s resist a nce . Neve rtheless, the

efficiency improvement ef fect by low ering the peak curre nt is

greater than the resistance increases with larger val ue of

inductor. Efficiency can also be improved for systems that

have high supply volt age s. Since the ISL97634 can only

supply from 2.4V to 5.5V, VIN must be sepa rated from the

high supply volt age for the boost circuit as shown in Figure 15

and the ef fici ency im provement is shown in Figure 16.

8 LEDs Operation

For medium size LCDs that need more than 7 low power LEDs

for backlighting, such as a portable media player or automotive

navigation panel displays, the voltage range of the ISL97634 is

not sufficient. However, the ISL97634 can be used as an LED

controller with an external protection MOSFET connected in

cascode fashion to achieve higher output voltage. A conceptual

8 LEDs driver circuit is shown in Figure 17. A 60V logic level N-

Channel MOSFET is configured such that its drain ties between

the inductor and the anode of Schottky diode, its gate ties to the

input, and its source ties to the ISL97634 LX node connecting

to the drain of the internal switch. When the internal switch

turns on, it pulls the source of M1 down to ground and LX

conducts as normal. When the internal switch turns off, the

source of M1 will be pulled up by the follower action of M1,

limiting the maximum voltage on the ISL97634 LX pin to below

VIN, but allowing the output voltage to go much higher than the

breakdown limit on the LX pin. The switch current limit and

maximum duty cycle will not be changed by this setup, so input

voltage will need to be carefully considered to make sure that

the required output voltage and current levels are achievable.

Because the source of M1 is effectively floating when the

internal LX switch is off, the drain-to-source capacitance of M1

may be sufficient to capacitively pull the node high enough to

break down the gate oxide of M1. To prevent this, VOUT should

be connected to VIN, allowing the internal Schottky diode to

limit the peak voltage. This will also hold the VOUT pin at a

known low voltage, preventing the built in OVP function from

causing problems. This OVP function is effectively useless in

this mode as the real output voltage is outside its intended

range. If the user wants to implement their own OVP protection

(to prevent damage to the output capacitor), they should insert

a zener diode from VOUT to the FB pin. In this setup, it would

be wise not to use the FBSW to FB switch, as otherwise, the

zener diode will have to be a high power one capable of

dissipating the entire LED load power . Then the LED stack can

then be connected directly to the sense resistor via a 10kΩ

resistor to FB. A zener can be placed from VOUT to the FB pin

allowing an overvoltage event to pull-up on FB with a low

breakdown current (and thus low power zener diode) as a

result of the 10k Ω resistor.

R2VDim_max VFB

–()R1

•[]

VFB 1F

min

–()•[]

-------------------------------------------------------------------

=(EQ. 8)

FIGURE 15. SEPARATE HIGH INPUT VOLTAGE FOR HIGHER

EFFICIENCY OPERATION

Vs = 12V L1

22µH

1 2

R1 4Ω

C3 0.22µF

ISL97634

FBSW

VOUT

PWM/EN

VIN

GND

C1 1µF

C2 0.1µF

VIN = 2.7V TO 5.5V

FIGURE 16. EFFICIENCY IMPROVEMENT WITH 9 AND 12V

INPUTS

VS = 9V

VS = 12V

0 5 10 15 20 25 30

ILED (mA)

EFFICIENCY (%)

VIN = 4V

7 LEDs

L1 = 22µH

R1 = 4Ω

fPWM

ISL97634

9FN6264.3

March 7, 2008

SEPIC Operation

For applications where the output voltage is not always

above the input voltage, a buck or boost regulation is

needed. A SEPIC (Single Ended Primary Inductance

Converter) topology, shown in Figure 18, can be considered

for such an application. A single cell Li-ion battery operating

a cellular phone backlight or flashlight is on e example. The

battery voltage is between 2.5V and 4.2V, depending on the

state of charge. On the other hand, the output may require

only one 3V to 4V medium power LED for illumination

because the light guard of the backl ight assembly is

optimized for cost efficiency trade-off reason.

In fact, a SEPIC configured LED driver is flexible enough to

allow the output to be well above or below the input voltage,

unlike the previous example. Another example is when the

number of LEDs and input requirements are different from

platform to platform, a common circuit and PCB that fit all the

platforms in some cases may be beneficial enough that it

outweighs the disadvantage of adding additional component

cost. L1 and L2 can be a coupled inductor in one package.

The simplest way to underst and SEPIC topology is to think

about it as a boost regulator where the input volt age is le vel

shifted downward at th e same magn itude and the low est

reference level starts at -VIN rather than 0V.

The SEPIC works as follows; assume the circuit in Figure 18

operates normally when the ISL97634 internal switch opens

and it is in the PWM off state. Af ter a short duration where few

LC time constant s elapsed, the circuit is considere d in the

steady-state with in the PWM of f period that L1 and L2 are

shorted. VB is therefore shorted to the ground and C3 is

charged to VIN with VA = VIN. When the ISL97634 inte rn al

switch closes and the circuit is in the PWM on -state, V A is no w

pulled to ground. Since the volt age in C3 cannot be changed

instant aneously, VB is shif ted downward and be comes -VIN.

The next cycle when the ISL97634 switch opens, VB boosts

up to the targeted output li ke the st andard boost regulator

operation, except the lowest reference point is at -VIN. The

output is approximated in Equation 9:

where D is the on-time of the PWM duty cycle.

The convenience of SEPIC comes with some trade-of f in

addition to the additional L and C co st s. Th e ef fi cie ncy is

usually lowered because of the rela tive ly la rge ef ficien cy loss

through the Schottky diode if the output volt age is low. The L2

series resistance also contributes additio nal loss. Figure 19

shows the ef ficiency measurement of a single LED application

as the input varies between 2.7V and 4.2V.

Note VB is conside red the level-shifted L X node of a st andard

boost regulator. The higher the input volt age, the lower the V B

voltage will be during PWM on period . The result is that the

effici ency will be lower at higher input voltages because the

SEPIC has to work harder to boost up to the required level.

This behavior is the opposite to the st andard boost regulator’s

and the comp ari son is shown in Figu re 19 .

PCB Layout Considerations

The layout is very important for the converter to function

properly. RSET must be located as close as possible to the FB

and GND pins. Longer traces to the LEDs are acceptable.

Similarly, the supply decoupling cap and the output filter cap

should be as close as possible to the VIN and VOUT pins.

The heat of the IC is mainly dissipated through the thermal pad

of the package. Maximizing the copper area connected to this

pad if possible. In addition, a solid ground plane is always

helpful for the EMI performance.

FIGURE 17. CONCEPTUAL 8 LEDs HIGH VOLTAGE DRIVER

VOUT

ISL97634

PWM/EN

VIN

FBSW

GND

R1 6.3Ω

2.2µ

VIN = 2.7V TO 5.5 V C3 4.7µF

10BQ100

FQT13N06L

1µF

SK011C226KAR

0.1µF

FIGURE 18. SEPIC LED DRIVER

1µF

22µH

12VAVB

VIN = 2.7V TO 5.5V

22µH

1µF C4 0.22µF

R1 1Ω

0.1µF

VIN

SDIN

VOUT

FBSW

GND

ISL97634

VOUT VIN D

1D–()

------------------

=(EQ. 9)

05101520

ILED (mA)

EFFICIENCY (%)

1 LED

L1 = L2 = 22µH

C3 = 1µF

R1 = 4.7Ω

FIGURE 19. EFFICIENCY MEASUREMENT OF A SINGLE LED

SEPIC DRIVER

VIN = 4.2V

VIN = 2.7V

ISL97634

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6264.3

March 7, 2008

ISL97634

Thin Dual Flat No-Lead Plastic Package (TDFN)

NX (b)

SECTION "C-C"

(A1)

BOTTOM VIEW

AREA

INDEX

0.10

0.08

SIDE VIEW

0.15

C0.15

TOP VIEW

AREA

INDEX

NX L

E2/2

REF.

(Nd-1)Xe

(DATUM A)

(DATUM B)

0.10

N-1

PLANE

SEATING

NX b

D2/2

NX k

FOR EVEN TERMINAL/SIDE

TERMINAL TIP

L8.2x3A

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.70 0.75 0.80 -

A1 - - 0.05 -

A3 0.20 REF -

b 0.20 0.25 0.32 5,8

D 2.00 BSC -

D2 1.50 1.65 1.75 7,8

E 3.00 BSC -

E2 1.65 1.80 1.90 7,8

e 0.50 BSC -

k0.20 - - -

L 0.30 0.40 0.50 8

N82

Nd 43

Rev. 0 6/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.25mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.