© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 1
CM1231CM1231
Issue X-1
Two-Channel PicoGuard XP
TM
ESD Clamp Protection Array
Features
Two channels of ESD protection
Exceeds ESD protection to IEC61000-4-2 Level 4:
±12kV contact discharge (OUT pins)
Two-stage matched clamp architecture
Matching-of-series resistor (R) of ±10mΩ typical
Flow-through routing for high-speed signal integrity
Differential channel input capacitance matching of
0.02pF typical.
Improved powered ASIC latchup protection
Dramatic improvement in ESD protection vs. best
in class single-stage diode arrays
40% reduction in peak clamping voltage
40% reduction in peak residual current
Withstands over 1000 ESD strikes*
Available in a SOT23-6 package
Applications
USB devices data port protection
General high-speed data line ESD protection
Product Description
The CM1231 is a member of the XtremeESDTM
product family and is specifically designed for next
generation deep submicron ASIC protection. These
devices are ideal for protecting systems with high data
and clock rates and for circuits requiring low capacitive
loading such as USB 2.0.
The CM1231 incorporates the PicoGuard XPTM dual
stage ESD architecture which offers dramatically
higher system level ESD protection compared with
traditional single clamp designs. In addition, the
CM1231 provides a controlled filter roll-off for even
greater spurious EMI suppression and signal integrity.
The CM1231 protects against ESD pulses up to ±12kV
contact on the “OUT” pins per the IEC 61000-4-2
standard.
The device also features easily routed "pass-through"
differential pinouts in a 6-lead SOT23 package.
*Standard test condition is IEC61000-4-2 level 4 test circuit with each (AOUT/BOUT) pin subjected to ±12kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one
continuous test run.
Electrical Schematic
VP
VNG r ound Rail
CM1231
Circuitry
Under
Protection
Positive Supply Rail VCC
1Ω
1ΩAIN
AOUT
BIN
BOUT
VP
VN
Connector
© 2007 California Micro Devices Corp. All rights reserved.
2490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07
CM1231
Issue X-1
Single and Dual Clamp ESD Protec-
tion
The following sections describe the standard single
clamp ESD protection device and the dual clamp ESD
protection architecture of the CM1231.
Single Clamp ESD Protection
Conceptually, an ESD protection device performs the
following actions upon a strike of ESD discharge into
the protected ASIC (see Figure 1).
1. When an ESD potential is applied to the system
under test (contact or air-discharge), Kirchoffs
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path.
2. Ideally, the classic shunt ESD clamp will switch
within 1ns to a low-impedance path and return the
majority of the EOS current to the chassis shield/
reference ground. In actuality, if the ESD compo-
nent's response time (tCLAMP) is slower than the
ASIC it is protecting, or if the Dynamic Resistance
(RDYN) is not significantly lower than the ASIC's I/O
cell circuitry, then the ASIC will have to absorb a
large amount of the EOS energy, and may be more
likely to fail.
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original specifica-
tions, ready for an additional strike. Any deteriora-
tion in parasitics or clamping capability should be
considered a failure, as it can affect signal integrity
or subsequent protection capability (this is known
as "multi-strike" capability.)
Figure 1. Single Clamp ESD Protection Block Diagram
Dual Clamp ESD Protection
In the CM1231 dual clamp PicoGuard XPTM
architecture, the first stage begins clamping
immediately, as it does in the single clamp case. The
dramatically reduced IRES current from stage one
passes through the 1Ω series element and then
gradually feeds into the stage two ESD device (see
Figure 2). The series inductive and resistive elements
further limit the current into the second stage, and
greatly attenuate the resultant peak incident pulse
presented at the ASIC side of the device.
This disconnection between the outside node and the
inside ASIC node allows the stage one clamps to turn
on and remain in the shunt mode before the ASIC
begins to shunt the reduced residual pulse. This gives
the advantage to the ESD component in the current
division equation, and dramatically reduces the
residual energy that the ASIC must dissipate.
Figure 2. Dual Clamp ESD Protection Block
Diagram
Connector
I/O
ESD
PROTECTION
DEVICE
ASIC
ESD
Protection
Device
ESD Strike
IRESIDUAL
ISHUNT
ASIC
DUT
ASIC
ESD
Protection
Stage 1
I
SHUNT1
ESD
Protection
Stage 2
I
SHUNT2
I
RESIDUAL
I/O
Connector
ESD Str ike 1Ω
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 3
CM1231CM1231
Issue X-1
CM1231 Architecture Overview
The PicoGuard XPTM two-stage per channel matched
clamp architecture with isolated clamp rails features a
series element to radically reduce the residual ESD
current (IRES) that enters the ASIC under protection
(see Figure 3). From stage 1 to stage 2, the signal lines
go through matched dual 1Ω resistors.
The function of the series element (dual 1Ω resistors
for the CM1231) is to optimize the operation of the
stage two diodes to reduce the final IRES current to a
minimum while maintaining an acceptable insertion
impedance that is negligible for the associated
signaling levels.
Each stage consists of a traditional low-cap Dual Rail
Clamp structure which steer the positive or negative
ESD current pulse to either the positive (VP) or
negative (VN) supply rail.
A zener diode is embedded between VP and VN,
offering two advantages. First, it protects the VCC rail
against ESD strikes. Second, it eliminates the need for
an additional bypass capacitor to shunt the positive
ESD strikes to ground.
The CM1231 therefore replaces as many as 7 discrete
components, while taking advantage of precision
internal component matching for improved signal
integrity, which is not otherwise possible with discrete
components at the system level.
Figure 3. CM1231 Block Diagram (IESD Flow During
a Positive Strike)
Advantages of the CM1231 Dual
Stage ESD Protection Architecture
Figure 4 illustrates a single stage ESD protection
device. The inductor element represents the parasitic
inductance arising from the bond wire and the PCB
trace leading to the ESD protection diodes.
Figure 4. Single Stage ESD Protection Model
Figure 5 illustrates one of the two CM1231 channels.
Similarly, the inductor elements represent the parasitic
inductance arising from the bond wire and PCB traces
leading to the ESD protection diodes as well.
Figure 5. CM1231 Dual Stage ESD Protection
Model
VCC
VP
VN
Positive Supply Rail
Ground Rai l
IRESIDUAL
IESD
1ΩCircuitry
Under
Protection
ESD
Stage
Bond W ir e
Inductance
ASICConnector
Bond Wire
Inductance
ASICConnector
Series
Element
1
st
Stage 2
nd
Stage
Bond Wire
Inductance
© 2007 California Micro Devices Corp. All rights reserved.
4490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07
CM1231
Issue X-1
CM1231 Inductor Elements
In the CM1231 dual stage PicoGuard XPTM
architecture, the inductor elements and ESD protection
diodes interact differently compared to the single stage
model.
In the single stage model, the inductive element
presents high impedance at high frequency, i.e. during
an ESD strike. The impedance increases the
resistance of the conduction path leading to the ESD
protection element. This limits the speed that the ESD
pulse can discharge through the single stage
protection element.
In the PicoGuard XPTM architecture, the inductance
elements are in series to the conduction path leading
to the protected device. The elements actually help to
limit the current and voltage striking the protected
device.
The reactance of the series and the inductor elements
in the second stage forces more of the ESD strike
current to be shunted through the first stage. At the
same time the voltage drop across series element
helps to lower the clamping voltage at the protected
terminal.
The inductor elements also tune the impedance of the
stage by cancelling the capacitive load presented by
the ESD diodes to the signal line. This improves the
signal integrity and makes the ESD protection stages
more transparent to the high bandwidth data signals
passing through the channel.
The innovative PicoGuard XP architecture turns the
disadvantages of the parasitic inductive elements into
useful components that help to limit the ESD current
strike to the protected device and also improves the
signal integrity of the system by balancing the
capacitive loading effects of the ESD diodes.
Graphical Comparison and Test Setup
The following graphs (see Figure 6, Figure 7, and Figure 8) show that the CM1231 (dual stage ESD protector) low-
ers the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a
standard single stage device. This data was derived using the test setups shown in Figure 9 and Figure 10.
Figure 6. IEC 61000-4-2 Vpeak vs.
Loading (RDUP*)
Figure 7. IEC 61000-4-2 Vclamp vs.
Loading (RDUP*)
* RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a vari-
able resistor.
Normalized Vclamp Initial (0-50ns)
0
0.2
0.4
0.6
0.8
1
0 5 10 15 20 25
Voltage
Si ngl e St age E S D
Device
CM1231
RDUP ( Ω)
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 5
CM1231CM1231
Issue X-1
Figure 8. IEC 61000-4-2 IRES (Residual ESD Peak Current) vs. Loading (RDUP)
Figure 9. Single Stage ESD Device Test Setup Figure 10. CM1231 Test Setup
I
RES
0
2
4
6
8
10
12
0 5 10 15 20 25
RDUP(Ω)
Current (A)
Singl e S tage ESD
Device
CM1231
Voltage
Probe
Current
Probe
Single Stage
ESD Device
I
RESIDUAL
IEC 6100-4 -2
Tes t Standar ds
R
VARIABLE
Device Under
Prot ect ion (DUP )
Voltage
Probe
Current
Probe
CM1231
I
RESIDUAL
I E C 6100-4- 2
T est S tandards
R
VARIABLE
Device Under
Prot ection (DUP )
© 2007 California Micro Devices Corp. All rights reserved.
6490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07
CM1231
Issue X-1
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
Note 1: Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE / PINOUT DIAGRAMS
Note:
1) This drawing is not to scale.
131 2
64
D312
5
VPBIN
BOUT
AOUT VNAIN
PIN DESCRIPTIONS
PIN PIN NAME PIN DESCRIPTION NOTES
1A
OUT Bidirectional clamp to Connector (Outside the system)
2V
NGround return to Shield
3A
IN Bidirectional clamp to ASIC (Inside the system)
4B
IN Bidirectional clamp to ASIC (Inside the system)
5V
PBias voltage (optional)
6B
OUT Bidirectional clamp to Connector (Outside the system)
PART NUMBERING INFORMATION
PIN PACKAG E LEAD-FREE FINISH Part Marking
6 SOT23-6 CM1231-02SO D312
ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING UNITS
Operating Supply Voltage (VP)6.0V
Diode Forward DC Current (AOUT/BOUT Side) 8.0 mA
Continuous Current through Signal Pins (IN to OUT) 1000 hours 125 mA
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -65 to +150 °C
DC Voltage at any channel input (VN - 0.5) to (VP + 0.5) V
Package Power Rating (SOT23-6) 225 mW
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 7
CM1231CM1231
Issue X-1
Note 1: All parameters specified at TA = –40°C to +85°C unless otherwise noted.
Note 2: This parameter is guaranteed by design and verified by device characterization
Note 3: Capacitance measured from OUT to VN with IN floating.
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VPOperating Supply Voltage 5 5.5 V
ICC5 Operating Supply Current VP = 5V 1 μA
VF Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8mA, TA = 25°C;
Note 2 0.60
0.60
0.80
0.80
0.95
0.95
V
V
VESD ESD Protection, Contact Discharge per
IEC 61000-4-2 Standard
OUT-to-VN Contact
IN-to-VN Contact
TA = 25°C;
Note 2
±12
±4
kV
kV
IRES Residual ESD Peak Current on RDUP
(Resistance of Device Under Protection)
IEC 61000-4-2 8kV;
RDUP = 5Ω, TA = 25°C;
Note 2
2.3 A
VCL Channel Clamp Voltage
Positive Transients
Negative Transients
IPP = 1A, TA = 25°C, tP = 8/20µs,
Zap at OUT, Measure at IN;
Note 2
+9
–1.4
V
V
RDYN Dynamic Resistance
Positive Transients
Negative Transients
IPP = 1A, TA = 25°C, tP = 8/20µs,
Zap at OUT, Measure at IN;
Note 2
0.4
0.3
Ω
Ω
COUT OUT Capacitance f=1 MHz, VP=5.0V, VIN=2.5V,
VOSC=30mV;
Note 2, 3
1.5 pF
ΔCOUT Channel to Channel Capacitance Match f=1 MHz, VP=5.0V, VIN=2.5V,
VOSC=30mV
Note 2
0.02 pF
RSSeries Resistance Note 2 1 Ω
ΔRSChannel to Channel Resistance Match Note 2 ±10 ±30 mΩ
© 2007 California Micro Devices Corp. All rights reserved.
8490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07
CM1231
Issue X-1
Performance Information
Figure 11. Clamping Voltage vs. Peak Current Figure 12. Capacitance vs. Bias Voltage
Typical Filter Performance (nominal conditions unless specified otherwise, 0V DC bias, 50Ω environment)
Figure 13. Typical Single-Ended S21 Plot (1dB/div, 3MHz to 6GHz)
Clamping Voltage vs . Peak Current
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
12345
I E C61000-4-5 8/20 uS P eak Cu r ren t ( A)
Clam pi ng Voltage (V)
Z ap at OU T; M eas ur e at
OUT
Z ap at OU T ; Measure at
IN
OUT-to-Vn Capacitance, IN Floating, Vp=5V
0.0
0.5
1.0
1.5
2.0
2.5
012345
Bias Voltage (V)
Capacitance (pF)
OUT-to-VN Capacitance, IN Floating, VP=5V
0 d B
-1 d B
-2 d B
-3 d B
3 10 100 1000 2000 6000
FREQUENCY (MHz)
-4 d B
-5 d B
-6 d B
-7 d B
-8 d B
-9 d B
-10 dB
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 9
CM1231CM1231
Issue X-1
CM1231 Application and Guidelines
The CM1231 has an integrated zener diode between
VP and VN (for each of the two stages). This greatly
reduces the effect of supply rail inductance L2 on VCL
by clamping VP at the breakdown voltage of the zener
diode. However, for the lowest possible VCL, especially
when VP is biased at a voltage significantly below the
zener breakdown voltage, it is recommended that a
0.22μF ceramic chip capacitor be connected between
VP and the ground plane. With the CM1231, this
additional bypass capacitor is generally not required.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the VP pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Figure 14. Typical Layout with Optional VP Cap
Footprint
Additional Information
See also California Micro Devices Application Note AP-209, “Design Considerations for ESD Protection,” in the
Applications section at www.calmicro.com.
© 2007 California Micro Devices Corp. All rights reserved.
10 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 12/17/07
CM1231
Issue X-1
Mechanical Details
SOT23-6 Mechanical Specifications, 6 pin
The CM1231 is supplied in a 6-pin SOT23 package.
Dimensions are presented below.
Dimensions for SOT23-6 Package
PACKAGE DIMENSIONS
Package SOT23-6
JEDEC No. MO-178 (Var. AB)
Pins/Leads 6
Dimensions Millimeters Inches
Min Max Min Max
A-- 1.45 -- 0.0571
A1 0.00 0.15 0.0000 0.0059
b0.30 0.50 0.0118 0.0197
c0.08 0.22 0.0031 0.0087
D2.75 3.05 0.1083 0.1201
E2.60 3.00 0.1024 0.1181
E1 1.45 1.75 0.0571 0.0689
e0.95 BSC 0.0374 BSC
e1 1.90 BSC 0.0748 BSC
L0.30 0.60 0.0118 0.0236
L1 0.60 REF 0.0236REF
# per tape
and reel
3000 pieces
Controlling dimension: millimeters
Mechanical Package Diagrams
TOP VIEW
A
SIDE VIEW
D
A1
L1
END VIEW
c
L
12 3
65 4
e1 e
E1 E
b
Pin 1
Marking
© 2007 California Micro Devices Corp. All rights reserved.
12/17/07 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 11
CM1231CM1231
Issue X-1
Tape and Reel Specifications
Figure 15. Tape and Reel Specifications
PART N U MBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL P0P1
CM1231 3.05 X 3.00 X 1.45 3.20 X 3.20 X 1.40 8mm 178mm (7") 3000 4mm 4mm
Top
For Tape Feeder Reference
Cover
Tape
P
1
Only including Draft.
Concentric Around B.
K
o
Embossment
User Direction of Feed
±
0.2 mm
P
o
Center Lines
of Cavity
W
10 Pitches Cumulative
Tolerance On Tape
A
o
B
o