PEB3332HTV2.2 - Lantiq - Product.Network

Integrated

Circuit

Systems, Inc.

ICS950401

0499C—11/01/04

Block Diagram Functionality

Pin Configuration

Recommended Application:

AMD K8 Systems

Output Features:

• 2 - Differential pair push-pull CPU clocks @ 3.3V

• 7 - PCI (Including 1 free running) @3.3V

• 3 - Selectable HT/PCI 66/33MHz @3.3V

• 1 - 48MHz, @3.3V fixed.

• 1 - 24/48MHz @ 3.3V

• 3 - REF @3.3V, 14.318MHz.

Features:

• Up to 220MHz frequency support

• Support power management: PCI stop and stop

clocks controlled by I2C.

• Spread spectrum for EMI reduction

• Uses external 14.318MHz crystal

•I

2C programmability features

• Supports Hypes transport technology (HT66 output).

AMD - K8™ System Clock Chip

*FS0/REF0 1 48 REF1/FS1*

VDDREF 2 47 GND

X1 3 46 VDDREF

X2 4 45 REF2/FS2*

GND 5 44 SPREAD*

*PCI33/HT66SEL# 6 43 VDDA

PCICLK33/HT66_0 7 42 GNDA

PCICLK33/HT66_1 8 41 CPUCLKT0

VDDPCI 9 40 CPUCLKC0

GND 10 39 GND

PCICLK33/HT66_2 11 38 VDDCPU

NC 12 37 CPUCLKT1

PCICLK0 13 36 CPUCLKC1

PCICLK1 14 35 VDD

GND 15 34 GND

VDDPCI 16 33 GNDA

PCICLK2 17 32 VDDA

PCICLK3 18 31 48MHz

VDDPCI 19 30 GND

GND 20 29 VDD

PCICLK4 21 28 24_48MHz/Sel24_48#*

PCICLK5 22 27 GND

PCICLK_F 23 26 SDATA

*PCI_STOP# 24 25 SCLK

48-S SOP/ T S S O P

* Internal P ull-Up Resistor

** Internal Pull-Down Resistor

ICS950401

FS2 FS1 FS0 PCI33_HT66

SEL# CPU PCI33 PCI33_HT66 COMMENTS

0 0 0 X Hi-Z Hi-Z Hi-Z Tri-St at e Mode

0 0 1 0 X X/6 X/3 Bypas s Mode

0 0 1 1 X X/6 X/6 Bypas s Mode

0 1 0 X 180.00 30.00 60.00 10% under-cl k

0 1 1 X 220.00 36.56 73.12 10% over-clk

1 0 0 X 100.00 33.33 33.33/ 66. 66 At hl on Compati ble

1 0 1 X 133.33 33.33 33.33/ 66. 66 At hl on Compati ble

1 1 0 X 166.66 33.33 33.33/66.66 Reserved

1 1 1 X 200.00 33.33 33.33/ 66. 66 Hammer Operati on

PLL2

PLL1

Spread

Spectrum

PCICLK (5:0)

CPUCLKT (1:0)

CPUCLKC (1:0)

X2 XTAL

OSC

CPU

DIVDER

PCI

DIVDER

Stop

SDATA

SCLK

FS (2:0)

SPREAD

24_48SEL#

PCI33/HT66SEL#

PCI_STOP#

Control

Logic

REF (2:0)

48MHz

24_48MHz

/ 2

PCICLK_F

PCICLK33/HT66(2:0)

X 2

Config.

Reg.

ICS950401

0499C—11/01/04

Pin Descriptions

PIN PIN PIN

# NAME TYPE

1*FS0/REF0 I/O Frequency select latch inp ut pin / 14.318 MHz reference clock.

2 VDDREF PWR Ref, XTAL power supply, nominal 3.3V

3 X1 IN Crystal input, Nominally 14.318 MHz.

4 X2 OUT Crystal output, Nominally 14.31 8MHz

5 GND PWR Ground pin.

6 *PCI33/HT66SEL# IN Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,

7 PCICLK33/HT66_0 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.

8 PCICLK33/HT66_1 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.

9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

10 GND PWR Ground pin.

11 PCICLK33/HT66_2 IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.

12 NC NC No Connect

13 PCICLK 0 OUT PCI cl ock output.

14 PCICLK 1 OUT PCI cl ock output.

15 GND PWR Ground pin.

16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

17 PCICLK 2 OUT PCI cl ock output.

18 PCICLK 3 OUT PCI cl ock output.

19 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

20 GND PWR Ground pin.

21 PCICLK 4 OUT PCI cl ock output.

22 PCICLK 5 OUT PCI cl ock output.

23 PCICLK_F I/O Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.

24 *PCI_STOP# I/O Input select pin, Stops all PCICLKs besides the PCICLK _F clocks at logic 0 level, when

i nput low.

25 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.

26 SDATA I/O Data pin for SMBu s circuit ry, 5V tolerant.

27 GND PWR Ground pin.

28 24_48MHz/Sel24_48#* I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

24MHz.

29 VDD PWR Power supply, nominal 3.3V

30 GND PWR Ground pin.

31 48MHz OUT 48MHz clock output.

32 VDDA PWR 3.3V power for the PLL core.

33 GNDA PWR Ground pin for the PLL core.

34 GND PWR Ground pin.

35 VDD PWR Power supply, nominal 3.3V

36 CPUCLKC1 OUT Complementory clock of differential CPU outpu ts. Push-pull requires external

termination.

37 CPUCLKT1 OUT True clock of di fferential CPU ou tputs. Push-pull requires external termination.

38 VDDCPU PWR S upply for CPU clocks, 3.3V nominal

39 GND PWR Ground pin.

40 CPUCLKC0 OUT Complementory clock of differential CPU outpu ts. Push-pull requires external

termination.

41 CPUCLKT0 OUT True clock of di fferential CPU ou tputs. Push-pull requires external termination.

42 GNDA PWR Ground pin for the PLL core.

43 VDDA PWR 3.3V power for the PLL core.

44 SPREAD* IN Asynchronous, acti ve high input, with i nternal 120Kohm pull-up resi stor, to enable

spread spectrum functionality.

45 REF2/FS2* I/O 14.31 8 MHz reference clock / Frequency sele ct latch i nput pin.

46 VDDREF PWR Ref, XTAL power supply, nominal 3.3V

47 GND PWR Ground pin.

48 REF1/FS1* I/O 14.31 8 MHz reference clock / Frequency sele ct latch i nput pin.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Driv e Strength

DESCRIPTION

ICS950401

0499C—11/01/04

General Description

The ICS950401 is a main clock synthesizer chip for AMD-K8. This provides all clocks required for Clawhammer and

Sledgehammer systems.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB

to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS950401

employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and

temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.

Power Groups

VDDA = PLL2 Pin 32

VDDA = VDD for Core PLL Pin 43

VDDREF = REF, Xtal Pin 2

Skew Characteristics

Param eter Description Test Condi tons Skew

Window Unit

Tsk_CPU_CPU m eas ur ed at x - ing of CP U, 250 ps

Tsk_CPU_PCI

m eas ur ed at x - ing of CP U,

1.5V of PCI c loc k 2000 ps

Tsk_PCI_PCI

m eas ur ed between ris ing

edge at 1.5V 500 ps

Tsk_PCI33-HT66

m eas ur ed between ris ing

edge at 1.5V 500 ps

Tsk_CPU_HT66

m eas ur ed between ris ing

edge at 1.5V 2000 ps

Tsk_CPU_HT66

m eas ur ed at x - ing of CP U,

1.5V of PCI c loc k 500 ps

Tsk_CPU_CPU m eas ur ed at x - ing of CP U, 200 ps

Tsk_CPU_PCI

m eas ur ed at x - ing of CP U,

1.5V of PCI c loc k 200 ps

Tsk_PCI_PCI

m eas ur ed between ris ing

edge at 1.5V 200 ps

Tsk_PCI33-HT66

m eas ur ed between ris ing

edge at 1.5V 200 ps

Tsk_CPU_HT66

m eas ur ed between ris ing

edge at 1.5V 200 ps

Tsk_CPU_HT66

m eas ur ed at x - ing of CP U,

1.5V of PCI c loc k 200 ps

t i m e independent

skew

not dependent on

V , T changes

time variant skew

v ari es ov er

V , T changes

ICS950401

0499C—11/01/04

General I2C serial interface information

How to Write:

•Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

WR ACK

ACK

PstoP bit

X Byte

Index Block Write Oper ation

Slave Address D2(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D3(H)

Index Block Read Operation

Slave Address D2(H)

Beginning Byte = N ACK

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

ICS950401

0499C—11/01/04

Byte0: Functionality and Frequency Select

tiB#niPDWPnoitpircseD

)ecnoetirW(elbasidetirW

0=0.elbanEmurtcepSdaerpS elbanE=1;elbasiD

0devreseR

5402SF

8401SF

10 0SF

0elbanEetirW

Notes:

1. Wr ite Disable. A '1' written to this bit after a '1' is wr itten to BYTE0/bit 0 will permanently disable writing to I2C until

the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and

acknowledge subsequent write cycles but it should not modify any of the registers.

3. A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable

modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently

disabled until the device power cycles. Block write transactions to the interface will complete, however unless the

interf ace has been previously unloc ked, the writes will have no effect. The effect of writing to this bit does not take effect

until the subsequent block write command.

4. Clarification on frequency select on power-up:

i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings.

ii. A '1' is written to Byte0, bit 0 to enable software control.

iii. Every time Byte0 is written, frequency input defaults will be affected.

iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the

contents of Byte0 to default back to hardware setting for FS(4:0).

niPdaerpStiBSSelbanEdaerpS

00 delbasiD

01 delbanE

10 delbanE

11 delbanE

ICS950401

0499C—11/01/04

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB63,731 )etoN(1_C/TKLCUPC

6tiB04,141 0_C/TKLCUPC

5tiB541 2FER

4tiB841 1FER

3tiB110FER

2tiB821 zHM84_42

1tiB131 zHM84

0tiB111 2_66/33KLCICP

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

Byte 4: Read-Back Register

(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-0

DIRODNEV6tiB-0

5tiB-1

4tiB-0

DINOISIVER

3tiB-0

2tiB-0

1tiB-0

0tiB-0

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-0 )etoN(7etyB

6tiB-0 )etoN(6etyB

5tiB-0 )etoN(5etyB

4tiB-0 )etoN(4etyB

3tiB-0 )etoN(3etyB

2tiB-1 )etoN(2etyB

1tiB-1 )etoN(1etyB

0tiB-1 )etoN(0etyB

Byte 6: Byte Count Register

(1= enable, 0 = disable)

Note: Writing to this register will configure byte count

and how many bytes will be read back. Default

state is 07H = 7 bytes.

TIB#NIPDWPNOITPIRCSED

7tiB-0 )devreseR(

6tiB-0 )devreseR(

5tiB220 )etoN(5KLCICP

4tiB120 )etoN(4KLCICP

3tiB810 )etoN(3KLCICP

2tiB710 )etoN(2KLCICP

1tiB410 )etoN(1KLCICP

0tiB310 )etoN(0KLCICP

TIB#NIPDWPNOITPIRCSED

7tiB71 1_66/33KLCICP

6tiB81 0_66/33KLCICP

5tiB221 5KLCICP

4tiB121 4KLCICP

3tiB811 3KLCICP

2tiB711 2KLCICP

1tiB411 1KLCICP

0tiB311 0KLCICP

TIB#NIPDWPNOITPIRCSED

7tiB

1)etoN(F_KLCICP

6tiB

1DAERPS

5tiB

1LES84_42

4tiB

1#LES66/33ICP

3tiB

1etatsnipdehctalpu-rewop2SF

2tiB

1etatsnipdehctalpu-rewop1SF

1tiB

1etatsnipdehctalpu-rewop0SF

0tiB

0)devreseR(

Note: This bit can be optional to disable the CPUCLKT/

C1 clock pair; CPUCLKT=L, CPUCLKC=H.

Note: Can be optionally used as PCI33_F enable

control.

Note: The above individual free running enable/disable

controls are intended to allow individual clock

outputs to be made free running. A clock output

that has it's free running bit enabled will not be

turned off with the assertion of either PCI_STOP#.

ICS950401

0499C—11/01/04

TIB#NIPDWPNOITPIRCSED

7tiB-0 devreseR

6tiB-0 devreseR

5tiB-0 devreseR

4tiB-1 devreseR

3tiB-0 devreseR

2tiB-0 devreseR

1tiB-0 devreseR

0tiB-0 devreseR

Byte 7: Reserved, Active/Inactive Register

(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-0 reggirTesluPelgniS

6tiB-0 etavitcAesluPelgniS

5tiB-0 )devreseR(

4tiB-0 )devreseR(

3tiB-0 )devreseR(

2tiB-0 )devreseR(

1tiB-0 )devreseR(

0tiB-0 )devreseR(

Byte 8: Single Pulse Mode Control Register

(1= enable, 0 = disable)

Notes:

ATPG Function: This feature is only used during processor Burn-In and is an optional feature

for the clk vendor to implement.

Two SMBus register bits are required to implement this feature:

ATPG Mode Bit: Enables/Disables ATPG mode

ATPG Pulse Bit: Triggers a single CPUclk pulse when set

Assuming that the clock synthesizer is operating either in Normal mode or PLL bypass

mode, following sequence may be followed to generate an ATPG pulse.

1. Set the Write Enable Bit (Byte/Bit 0) to program the Clock Synthesizer registers using

the SM Bus.

2. Use the ATPG Mode Bit in the clock synthesizer configuration space to enable/disable

the ATPG mode. When this bit is set, the ATPG mode is enabled and the differential

CPU clock outputs are pulled in differential low state (CPUT = 0 and CPUC = 1). The

ATPG mode also requires the USBclk (48MHz) to run as usual. All other clks (PCI,

Ref, PCI33_66, SuperIO are not used by the ATPG mode therefore can either be left

running or shut off.

3. Use the ATPG Pulse Bit in the clock synthesizer program space to generate the ATPG

pulse. When the ATPG Pulse Bit is set, a differential ATPG pulse will be generated on

the differential CPU clock pins. The pulse width of the ATPG pulse will be one CPU

clock period. The CPU clock period in the ATPG mode is same as the one in Normal

mode or PLL bypass mode.

4. Clear the ATPG Pulse Bit, as the clock synthesizer only recognizes 0 to 1 transition of

the ATPG pulse bit for next ATPG pulse generation.

5. Use the ATPG Pulse Bit to generate the next ATPG pulse (set to 1).

6. If the ATPG Pulse bit is not set and the ATPG Mode Bit is cleared then the synthesizer

should work in normal or PLL bypass mode.

ICS950401

0499C—11/01/04

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 3.8V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . –65°C to +150°C

ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electri cal Charact erist ics - Input/ Supply/ C om m on Output Parameters

TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unle ss othe rwise stat ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD+0.3 V

Input L ow Voltag e VIL VSS-0.3 0.8 V

Input High C urrent IIH VIN = VDD 5µA

Input Low Current IIL1 VIN = 0 V; Inputs with n o pul l -up resis t ors -5 µA

Input Low Current IIL2 VIN = 0 V; Inputs with pul l-up res i s t ors -200 µA

Operating IDD3.3OP66 CL = 0 pF; Sele ct @ 66MHz

Supply C urrent IDD3.3OP100 CL = 0 pF; Sel e ct @ 100MHz

IDD3.3OP133 CL = 0 pF; Sel e ct @ 133MHz

Power Down PD 600 µA

Input fr e que nc y FiVDD = 3.3 V; 10 14.318 16 M Hz

CIN L ogi c Inputs 5 pF

CINX X1 & X2 pins 27 45 pF

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3ms

1Guarant eed by d e sign, not 100% teste d i n produc t i on.

180 mA

Input C a pacit anc e 1

ICS950401

0499C—11/01/04

Elect rical C haracterist ics - CPUCLK

TA = 0 - 70º C ; VDD = 3.3 V +/-5%; C L = 20 pF (unle ss o the rwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance ZOVO = VX15 55 Ω

Output High Voltage VOH2B 11.2V

Output Low Voltage VOL2B 0.4 V

Output Low Curren t IOL2B VOL = 0.3 V 18 mA

Rise E dge Rate1Me asured from 20-80% 2 7 V/ns

F a ll Edge Rate1Measured from 80-20% 2 7 V/ns

VDIFF

Dif f e rential V oltage,

Measured @ the Ham mer

te st load (single -e nde d

measurement)

0.4 2.3 V

∆VDIFF

Change in VDIFF_DC

ma gnit ude , Me a sured @ the

Hammer test load (single-

e nde d measurement )

-150 150 mV

VCM

Comm on M ode Volt a ge,

Measured @ the Ham mer

te st load (single -e nde d

measurement)

1.05 1.45 V

∆VCM

Cha nge in Comm on M ode

Voltage, Measur ed @ the

Hammer test load (single-

e nde d measurement )

-200 200 mV

Duty Cycle1dt2B VT = 50% 45 53 %

J itte r, Cycle-to- c ycle 1tjcyc-cyc2B VT = VX0 200 ps

Notes:

1 - Guarante ed by de sign, not 100% t es ted in produc ti on.

3 - Vpullup(external) = 1.5V, M i n = Vpullup(external)/2-150mV; Max=(Vpull up(external)/2)+150m

2 - VDIF s pe cifies the minim um input dif ferential voltages (VTR-VCP) required for switching, where VTR is the "true"

i nput le vel a nd VCP i s the "complement" input le vel.

ICS950401

0499C—11/01/04

Electrical C h aracteristi c s - PC ICLK , PCICLK 33/HT66 (33MHz)

TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless othe rwis e s tate d)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Vol tage VOH1 IOH = -12 m A 2.4 V

Output L ow Voltage VOL1 IOL = 9.0 mA 0.4 V

Output High Current IOH1 VOH = 2.0 V -15 mA

Output L ow Current IOL1 VOL = 0.8 V 10 mA

Rise E dge Rate1Mea sure d from 20-60% 1 4 V/ns

Fall Edge Rate 1Me a sur e d from 60-20% 1 4 V/ns

Duty Cycle1dt1 VT = 50% 45 55 %

Jitter, Cycle-to- cycle1tjcyc-cyc2B Me a sur e d on rising edge @ 1.5V 250 ps

J i tt e r, Acc umulate d1-1000 1000 ps

Output Im peda nc e Z OVO = VX12 55 Ω

1Guarant e ed by de sign, not 100% t e sted in produc tion.

Electrical C h aracteristi c s - PCICLK 33/HT66 (66MHz)

TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unle ss othe rwis e s tate d)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Hi gh Voltage VOH1 IOH = -12 m A 2.4 V

Output L ow Voltage VOL1 IOL = 9.0 mA 0.4 V

Output High Current IOH1 VOH = 2.0 V -15 mA

Output L ow Current IOL1 VOL = 0.8 V 10 mA

Rise E dge Rate1Mea sure d from 20-60% 1 4 V/ns

Fall Edge Rate 1Me a sur e d from 60-20% 1 4 V/ns

Duty Cycle1dt1 VT = 50% 45 55 %

Jitter, Cycle-to-cycle1tjcyc-cyc2B Me a sur e d on ris i ng e dge @ 1. 5V 250 ps

J i tt e r, Acc umulate d1-1000 1000 ps

Output Im peda nc e Z OVO = VX12 55 Ω

1Guarant ee d by de sign, not 100% t ested in production.

ICS950401

0499C—11/01/04

Elect rical Ch aracterist ics - 24MHz, 48MHz

TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless ot he rwise sta t e d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH5 IOH = -1 2 mA 2.4 V

Output L ow Voltage VOL5 IOL = 9 mA 0.4 V

Output High Curre nt IOH5 VOH = 2.0 V -22 mA

Output L ow C urrent IOL5 VOL = 0.8 V 16 mA

Rise Edge Rate1Measured from 20 -80% 0.5 2 V/ns

Fall Edge Rate1Measured from 80-20 % 0.5 2 V/ns

Duty C ycle1dt5 VT = 50% 45 55 %

J itter , Absolute1tjabs5 VT = 1.5 V -1 1 ns

J itte r, Cycle-to-cycle1tjcyc-cyc2B VT = VX, for 24_48M Hz c l ock 0 500 ps

J itte r, Cycle-to-cycle1tjcyc-cyc2B VT = VX, for 48MHz c l o c k 0 200 ps

Output I mpedance ZOVO = VX20 60 Ω

Elect rical Ch aracterist ics - REF

TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 p F (unless othe rwise stat ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Volta ge VOH5 IOH = -12 mA 2.4 V

Output L ow Voltage VOL5 IOL = 9 mA 0.4 V

Output High Curre nt IOH5 VOH = 2.0 V -22 mA

Output L ow C urrent IOL5 VOL = 0.8 V 16 mA

Rise Edge Rate1Measured from 20 -80% 0.5 2 V/ns

Fall E dge Rate1Measured from 80-20 % 0.5 2 V/ns

Duty C ycle1dt5 VT = 50% 45 55 %

J itte r, Cycle-to-cycle1tjcyc-cyc2B Mesured o n rising edg e @ 1.5V 0 1000 ps

J itte r, Acc um ulated1-1000 1000 ps

1Gua rant eed by de sign, not 100% t e sted in production.

ICS950401

0499C—11/01/04

Fig. 1

Shared Pin Operation -

Input/Output Pins

The I/O pins designated by (input/output) on the ICS9248-

175 serve as dual signal functions to the device. During initial

power-up, they act as input pins. The logic level (voltage)

that is present on these pins at this time is read and stored

into a 5-bit internal data latch. At the end of Power-On reset,

(see AC characteristics for timing values), the device changes

the mode of operations for these pins to an output function.

In this mode the pins produce the specified buffered clocks

to external loads.

T o program (load) the internal configuration register for these

pins, a resistor is connected to either the VDD (logic 1) power

supply or the GND (logic 0) voltage potential. A 10 Kilohm

(10K) resistor is used to provide both the solid CMOS

programming voltage needed during the power-up

programming period and to provide an insignificant load on

the output clock during the subsequent operating period.

Via to

VDD

Clock trace to load

Series Term. Res.

Programming

Header

Via to Gnd

Device

Pad

2K 

8.2K 

Figure 1 shows a means of implementing this function when

a switch or 2 pin header is used. With no jumper is installed

the pin will be pulled high. With the jumper in place the pin

will be pulled low . If programmability is not necessary , than

only a single resistor is necessary. The programming resistors

should be located close to the series termination resistor to

minimize the current loop area. It is more important to locate

the series termination resistor close to the driver than the

programming resistor.

ICS950401

0499C—11/01/04

Ordering Information

ICS950401yFLF-T

INDEX

AREA

INDEX

AREA

1 2

h x 45°

E1 E



SEATING

PLANE

SEATING

PLANE

-C-

- C -

.10 (.004) C

300 mil SSOP Package

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291 .299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

α0° 8° 0° 8°

MIN MAX MIN MAX

48 15.75 16.00 .620 .630

10-0034

Reference Doc.: JEDEC Publication 95, MO-118

VARIATIONS

SEE VARIATIONS SEE VARIATIONS

ND mm. D (inch)

SEE VARIATIONS SEE VARIATIONS

0.635 BASIC 0.025 BASIC

SYMBOL In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

Example:

Designation for tape and reel packaging

Lead Free (Optional)

Packag e Typ e

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y F LF- T

ICS950401

0499C—11/01/04

Ordering Information

ICS950401yGLF-T

INDEX

AREA

INDEX

AREA

1 2

E1 E



SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa

6.10 mm. Body, 0.50 mm. pitch TSSOP

(240 mil) (0.020 mil)

MIN MAX MIN MAX

A -- 1.20 -- .047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008

E1 6.00 6.20 .236 .244

L 0.45 0.75 .018 .030

α0° 8° 0° 8°

aaa -- 0.10 -- .004

ARIATIONS

MIN MAX MIN MAX

48 12.40 12.60 .488 .496

10-0039

SYMBOL In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS SEE VARIATIONS

8.10 BASIC 0.319 BASIC

0.50 BASIC 0.020 BASIC

SEE VARIATIONS SEE VARIATIONS

ND mm. D (inch)

Reference Doc.: JEDEC Publication 95, MO-153

Example:

Designation for tape and reel packaging

Lead Free (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y G LF- T