Multi-Output, Low-Noise Power Supply Controller for Notebook Computers June 20, 2000 SC1402 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1402 is pin compatible with the MAX1632 with improved load regulation performance. The SC1402 is a multiple-output power supply controller designed to power logic supply components in battery operated systems. The SC1402 utilizes synchronous rectified buck topologies to generate two voltages, (3.3V and 5V fixed or adjustable) with up to 95% efficiency. It also provides two linear regulators for system housekeeping functions. The 12V linear regulator output is generated from a coupled inductor of the 5V switching regulator. Control functions include: power up sequencing, soft start, power-good signaling, automatic bootstrapping for high side MOSFETs, and frequency synchronization. An internal precision 2.5V reference ensures 2% output voltage. The internal oscillator can be adjusted to 200kHz, 300kHz or synchronized to an external clock. The MOSFET drivers provide 1A peak drive current for fast MOSFET switching. The SC1402 includes a PSAVE enable input to select a pulse skipping mode for high efficiency or a fixed frequency mode for low noise operation. FEATURES * 6V to 30V Input range * Dual synchronous rectified outputs * Fixed frequency or PSAVE mode for maximum * * * * * * * * * * efficiency over wide load current range 5V/50mA linear regulator 12V/120mA linear regulator Precision 2.5V reference output Programmable power-up sequence Power-good output (RESET) Output over-current protection Output over-voltage protection Output under-voltage shutdown 4A typical shutdown current 7mW typical quiescent power APPLICATIONS * Notebook and subnotebook computers * PDAs and Mobile communicators * Desktop DC-DC converters ORDERING INFORMATION: DEVICE TEMP. (TA) SSOP-28 -40 to +85C SC1402ISSTR TYPICAL APPLICATION CIRCUIT (Fig. 1) (1) PACKAGE Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. 1 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 ABSOLUTE MAXIMUM RATINGS PARAMETERS V+, BST3, BST5 to GND PGND to GND PHASE3 to BST3, and PHASE5 to BST5 VL to GND REF,SYNC,SEQ,PSAVE,TIME_ON5,RESET to GND RUN/ON3, SHDN to GND VDD to GND 12OUT to GND VL, REF Short to GND 12OUT Short to GND REF Current VL Current 12OUT Current VDD Shunt Current Operating Ambient Temperature Range, TA Storage Temperature, TS Lead soldering temperature, TL ELECTRICAL CHARACTERISTICS MAXIMUM -0.3, +36 0.3 -6 to +0.3 -0.3 to 6 -0.3 to (VL + 0.3V) -0.3 to (V+ + 0.3V) -0.3 to +30V -0.3 to (VDD + 0.3V) Continuous Continuous +5 +50 +200 +15 -40 to 85 -65 to +150 +300, 10 seconds UNITS V V V V V V V V sec. sec. mA mA mA mA C C C (1) (Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C). PARAMETER CONDITIONS MAIN SMPS CONTROLLERS Input Voltage Range 3V Output Voltage in V+ = 6V to 30V, CSH3-CSL3 = 0V, Adjustable Mode CSL3 tied to FB3 3V Output Voltage in Fixed Mode V+ = 6V to 30V, 0mV < CSH3-CSL3 < 80mV, FB3 = 0V 5V Output Voltage in Adjustable V+ = 6V to 30V, CSH5-CSL5 = 0V, Mode CSL5 tied to FB5 5V Output Voltage in Fixed Mode V+ = 6V to 30V, 0mV < CSH5-CSL5 < 80mV, FB5 = 0V Output Voltage Adjust Range Either SMPS Adjustable-Mode Threshold Dual Mode comparator Voltage Load Regulation Either SMPS, 0V < CSH_-CSL_ < 80mV Line Regulation Current-Limit Threshold PSAVE Mode Threshold Soft-Start Ramp Time Oscillator Frequency Maximum Duty Factor Either SMPS, 6V < V+ < 30V CSH3-CSL3 or CSH5-CSL5 PSAVE = VL or 12OUT < 11.9V PSAVE = 0V, not tested From enable to 95% full current limit with respect to fOSC (Note 2). SYNC = VL SYNC = 0V SYNC = VL SYNC = 0V MIN TYP MAX UNITS 6.0 2.45 2.5 30.0 2.55 V V 3.17 3.3 3.43 V 2.45 2.5 2.55 V 4.82 5.0 5.18 V 5.5 1.3 V V REF 0.5 80 -50 10 270 170 -0.8 % 0.03 100 -100 25 512 %/V 300 200 94 96 120 -150 40 330 235 mV mV clks kHz % 2 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA = -40 to +85C Typical values are at TA = +25C). PARAMETER SYNC Input High Pulse CONDITIONS 2 TYP MAX UNITS 300 2 SYNC Input Low Pulse Width SYNC Rise/Fall Time MIN 300 ns 2 200 SYNC Input Frequency Range Current-Sense Input Leakage Current 240 V+ = VL = 0V, CSL3 = CSH3 = CSL5 = CSH5 = 5.5V 0.01 350 kHz 10 A 20 V 30 mA 30 A FLYBACK CONTROLLER VDD Shunt Threshold Rising edge, hysteresis = 1% 18 VDD Shunt Sink Current VDD = 20V 5 VDD Leakage Current VDD = 5V , Standby mode 10 12V LINEAR REGULATOR 12OUT Output Voltage 0mA < Load < 120mA 11.55 12.1 12.50 12OUT Current Limit 12OUT forced to 11V 150 mA 12OUT Regulation Threshold Falling edge 11.9 V Quiescent VDD Current Run mode, no 12OUT load 50 100 V A INTERNAL REGULATOR AND REFERENCE VL Output Voltage SHDN = V+, 6V < V+ < 30V, 0mA < ILOAD < 50mA, RUN/ON3 = TIME/ON5 = 0V 4.6 Undervoltage Fault Lockout Threshold Falling edge, hysteresis = 0.9V 3.5 Switchover Threshold Switch over at startup REF Output Voltage No external load, Standby Mode REF Load Regulation 0A < Load < 50A 12.5 0mA < Load < 5mA 50 5.2 3.7 V 4.5 2.45 REF Sink Current 2.5 2.55 10 REF Fault Lockout Voltage Falling edge V+ Operating Supply Current VL switched over to CSL5, 5V SMPS on 10 V+ Standby Supply Current V+ = 6V to 30V, SMPS off, includes current into SHDN 180 V+ = 6V to 30V, SHDN = 0V 4 V+ Shutdown Supply Current 4.0 1.8 Quiescent Power Consumption Both SMPSs enabled, FB3 = FB5 = 0V, CSL3 = CSH 3 = 3.5V, CSL5 = CSH5 = 5.5V mV A 2.2 V 50 A 7.0 20 mW 3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA = -40 to +85C Typical values are at TA = +25C). PARAMETER CONDITIONS MIN TYP MAX UNITS 3.5 7 10 % FAULT DETECTION Overvoltage Trip Threshold With respect to unloaded output voltage Overvoltage-Fault Propagation Delay CSL_ driven 2% above overvoltage trip threshold Output Undervoltage Threshold With respect to unloaded output voltage Output Undervoltage Lockout Time From each SMPS enabled, with respect to fOSC Thermal Shutdown Threshold Typical hysteresis = +10C 1.5 s 60 70 80 % 5000 6144 7000 clks 150 C RESET RESET Trip Threshold With respect to unloaded output voltage, falling edge; typical hysteresis = 1% RESET Propagation Delay Falling edge, CSL_ driven 2% below RESET trip threshold RESET Delay Time With respect to fOSC -10 -7 -4 % 1.5 s 27,000 32,000 37,000 clks INPUTS AND OUTPUTS Logic Input Low Voltage RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC 0.6 Logic Input High Voltage RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC Input Leakage Current RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHDN, SYNC, SEQ = 0V or 3.3V +1 A Logic Output Low Voltage RESET, ISINK = 4mA 0.4 V Logic Output High Current RESET = 3.5V 1 TIME/ON5 Input Trip Level SEQ = 0 or VL 2.4 TIME/ON5 Source Current TIME/ON5 = 0V, SEQ = 0 or VL TIME/ON5 On-Resistance TIME/ON5, RUN/ON3 = 0V, SEQ = 0 or VL Gate Driver Sink/Source Current DL3, DH3, DL5, DH5, forced to 2V Gate Driver On-Resistance High or low 2.4 2 V V mA 3 2.6 V 4 A 100 1 A 1.5 7 Note 1: This device is ESD sensitive. Use of standard ESD handling precautions is required. Note 2: Guaranteed by design. 4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 BLOCK DIAGRAM 5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION Top View SSOP-28 PWM CONTROLLER DIAGRAM (Fig. 2) 6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 PIN DESCRIPTION Pin # Pin Name Pin Function 1 CSH3 Current Sense Input for the 3.3V SMPS. Current limit level is 100mV referred to CSL3. 2 CSL3 Current Sense Input. Also serves as the feedback input in fixed output mode. 3 FB3 Feedback Input for the 3.3V SMPS; Connect FB3 to a resistor divider for adjustable output mode and FB3 is regulated to REF (approx. 2.5V). FB3 selects the 3.3V fixed output voltage setting when tied to GND. 4 12OUT 12V, 120mA Linear Regulator Output. Input supply comes from VDD. Bypass 12 OUT to GND with 1F minimum capacitor. 5 VDD Supply Voltage Input for the 12 OUT Linear Regulator. Also connects to a 18V overvoltage shunt regulator clamp. 6 SYNC Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz. Driven externally to SYNC between 240kHz and 350kHz. 7 TIME/ON5 8 GND Low noise Analog Ground and Feedback reference point. 9 REF 2.5V Reference Voltage Output. Bypass to GND with 1F minimum capacitor. 10 PSAVE Logic Control Input that disables PSAVE Mode when high. Connect to GND for power save mode. 11 RESET Active Low Timed Output. RESET swings from GND to VL. Goes high after 32,000 clock cycle delay following power up as a power good signal. 12 FB5 Feedback Input for 5V SMPS; Connect FB5 to a resistor divider for adjustable output mode and FB5 regulates to REF (approx. 2.5V). FB5 selects the 5V fixed output voltage setting when tied to GND. 13 CSL5 Current Sense Input for 5V SMPS. Current limit level is 100mV referred to CSL5. 14 CSH5 Current Sense Input for 5V SMPS. Also serves as the feedback input in fixed output mode. 15 SEQ Input that selects SMPS power up sequence. 16 DH5 Gate Drive Output for the 5V, high side N-Channel MOSFET. 17 PHASE5 18 BST5 19 DL5 20 PGND 21 VL 5V, Internal Linear Regulator Output. 22 V+ Battery Voltage Input. 23 SHDN 24 DL3 25 BST3 26 PHASE3 27 DH3 28 RUN/ON3 Dual Purpose Timing Capacitor Pin or 5V SMPS ON/OFF Control Input. Input resistor of 1K is required when using ON/OFF control input. Switching Node inductor connection. Boost capacitor connection for 5V, SMPS high-side gate drive. Connect a 0.1F capacitor. Gate Drive Output for the 5V, SMPS low-side N-Channel MOSFET. Power Ground. Shutdown Control Input, active low. Gate Drive Output for the 3.3V, SMPS low-side N-Channel MOSFET. Boost Capacitor Connection for high side gate drive. Connect a 0.1F capacitor. Switching Node inductor Connection. Gate Drive Output for the 3.3V, high-side N-Channel MOSFET. Dual purpose run or 3.3V ON/OFF control input. Note: All logic level inputs and outputs are open collector TTL compatible. 7 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 DETAILED DESCRIPTION The SC1402 is a multiple-output, high efficiency, versatile power supply controller designed to power battery operated systems. Four high-current gate drive outputs are supplied to control all MOSFETs in two synchronous rectified buck converters. These buck converters can be programmed to operate at either fixed or adjustable output voltages. The power save feature of the SC1402 achieves high efficiency over a wide range of load current. The control and fault monitoring circuitry associated with each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with slope compensation, pulse width modulator, power save, over-current and over-voltage and under-voltage fault protection. Two linear regulators and a precision reference voltage are also provided by the SC1402. PWM Control Block The two PWM control blocks for the 3V and 5V power supply outputs are identical. The SC1402 employs peak current mode control with slope compensation to provide fast output response to load and line transients. The PWM control block consists of an analog PWM modulator followed by PWM logic control. The analog modulator combines the output current, slope compensation signal and error voltage to generate a PWM pulse train. The PWM logic uses the pulse train from the modulator and other control signals to generate the output states for the high and low side gate driver outputs. A block diagram of the PWM control block is shown in Fig. 2. The error amplifier compares the difference between the reference voltage and the feedback voltage to generate the error voltage for the peak current mode comparator. A nominal gain of 8 is used in the error amplifier to increase the system loop gain and to reduce the load regulation error typically seen in low loop-gain, current-mode controllers. The increased gain in the voltage loop is compensated by pole-zero-pole response of the voltage error amplifier. The current feedback signal is summed with the slope compensation signal and compared to the error voltage at the PWM comparator. When the power supply is operating in continuous conduction mode, the high-side MOSFET is turned on at the beginning of each switching cycle. The high-side MOSFET is turned off when the desired duty cycle is reached. Active shoot-through protection delays the turn-on of the low-side MOSFET until the phase node drops below 2.5V. The low-side MOSFET remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the low-side MOSFET has dropped low before the high-side MOSFET is turned on. When PSAVE is enabled (low) and the output current drops below 25% of its peak level, the PWM logic will automatically enter PSAVE mode to improve efficiency. When the controller enters power save, it increases the regulation point by 0.8%, typically issuing one more high-side pulse as the converter enters PSAVE. The PWM control then disables switching cycles until the FB falls below the reference. At light loads the effective switching frequency will drop dramatically and efficiency will increase because of the reduced gatecharge current required to switch the power stage. Boosting the regulation point when entering PSAVE gives the output improved dynamic regulation because the output voltage is not allowed to droop below the nominal regulation point. Load-current steps, that cause the converter to come out of PSAVE, will not cause as large a negative dip in the output voltage. Gate Drive/Control The gate drivers on the SC1402 are designed to switch large MOSFETs up to 350kHz. The high-side gate drivers are required to drive the gates of the high-side N-MOSFETs above the V+ input. The supply for each high-side gate driver is generated by charging a bootstrap capacitor from the VL supply when the low-side driver is on. Monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous-conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side drivers are off. Under light-load conditions the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. Internal Bias Supply The VL linear regulator provides a 5V output that is used to power the gate drivers, the 2.5V reference, and 8 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 internal control sections of the SC1402. The regulator is capable of supplying up to 50mA (including MOSFET gate-charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak current requirements of the gate-driver outputs. This regulator receives its input power from the V+ battery input. Efficiency is improved by providing a bootstrapping mode for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency switch-mode power supply. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA maximum and should be bypassed with 1uF minimum capacitor. Loading the REF output will reduce the REF voltage decreasing the output accuracy of both SMPS outputs slightly. Current Sense (CSH,CSL) The output current of the power supply is sensed as the voltage drop across an external resistor between the CSH and CSL pins. Over-current is detected when the current-sense voltage exceeds +/-100mV. The negative current limit (i.e. -100mV) is required for operation with PSAVE mode disabled, and also to limit the output current when charging the bulk supply capacitor of the 12V regulator. A positive over-current will turn off the high-side drivers, a negative over-current will turn off the low-side driver, each on a cycle by cycle basis. The current sense is also used for peak current feed back in the main PWM loop and for determining the current level for entering power save mode and the turn-off time for the synchronous rectifier. ceeds 150C with 10C of hysteresis. If either SMPS output is greater than 7% above its nominal value, both SMPSs are latched off and synchronous rectifiers are latched on. To prevent the output from ringing below ground, a 1A Schottky diode should be placed across each output, anode at GND. Two different levels of undervoltage are detected. If the output falls 5% below its nominal output, the RESET output is pulled low. If the output falls 30% below its nominal output following a startup delay, both SMPSs are latched off. Both of the latched fault modes will remain in effect until SHDN or RUN/ON3 is toggled or the V+ input is brought below 1V. Shutdown and Operating Modes Holding the SHDN pin low disables the SC1402, reducing the V+ input current to <10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SHDN RUN/ ON3 TIME/ ON5 MODE Low X X Shutdown High Low Low High High High DESCRIPTION Minimum bias current Standby VREF and VL regulator enabled Run Mode Both SMPS Running Oscillator The SC1402 oscillator frequency is trimmed to +/10%. When the SYNC pin is set high the oscillator runs at 300kHz; when SYNC is set low the frequency is 200kHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240kHz and 350kHz. In general, 200kHz operation is used for highest efficiency, and the 300kHz for minimum output ripple and/or smaller inductor and output capacitor sizes. SMPS will put the SC1402 in run mode. Fault Protection The 12OUT linear regulator is capable of supplying 120mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS inductor. In addition to cycle-by-cycle current limit, the SC1402 monitors over-temperature, and output over-voltage and under-voltage conditions. The over-temperature detect will shut the part down if the die temperature ex- Output Voltage Selection If FB is connected to ground, internal resistors set up 3.3V and 5V output voltages. If external resistors are used, the internal feedback is disabled and the output is regulated based on 2.5V at the FB pin. 12OUT Supply 9 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 A heavy load on the 12OUT regulator when the 5V SMPS is in PSAVE will cause the VDD input to drop, browning out the regulator. If the output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into continuous conduction mode for 8 cycles. This recharges the bulk input capacitor on VDD. The 12OUT linear regulator has a current limit to prevent damage under short-circuit conditions. Over-voltage protection is provided on the VDD input. If the VDD input is above 19V, an over-voltage is detected and a 10mA current shunt load is applied to VDD. The over-voltage threshold has 0.5V of hysteresis. Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent input surge currents. The current limit is increased from 0 to 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. A RESET output is also generated at startup. The RESET pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles at which time the SMPSs should be in regulation. When SEQ is set to REF, the RESET only monitors the 3.3V SMPS in regulation. The 5V SMPS is ignored. Power-up Sequence and Soft Start The user has control of the SC1402 startup sequence by setting the SEQ, RUN/ON3 and TIME/ON5 pins as described in Table 1. SEQ RUN/ON3 TIME/ON5 RESET DESCRIPTION REF LOW LOW Low. Both SMPSs off. REF LOW HIGH Low. 5V SMPS on, 3.3V SMPS off. REF HIGH LOW Follows 3.3V SMPS. 3.3V SMPS on, 5V SMPS off. REF HIGH HIGH Follows 3.3V SMPS. Both SMPSs on. GND LOW TIMING CAP Low. Both SMPSs off. GND HIGH TIMING CAP High after both outputs are in regulation. 5V starts on rising edge of RUN/ON3, 3V starts when TIME/ON5 > REF. VL LOW TIMING CAP Low. Both SMPSs off. VL HIGH TIMING CAP High after both outputs are in regulation. 3.3V starts on rising edge of RUN/ON3, 5V starts when TIME/ON5 > REF. Table 1 10 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 APPLICATION INFORMATION Introduction The SC1402 is a versatile dual switching regulator adjustable from 2.5V to 5.5V with fixed 5V and 3.3V modes. In addition, there are two on-chip 12V and 5V linear regulators capable of supplying 120mA and 50mA of output current, respectively. The SC1402 is designed for notebook applications but has applications anywhere high efficiency, small size and low cost are required. The Semtech SC1402 EVAL (P/N SC1402EVB) board consists of a 3.3V, 3A switcher, a 5.0V, 3A switcher, an onboard 12V linear regulator. A 15V flyback supply developed off the 5V SMPS inductor delivers the input voltage to the onboard 12V linear regulator. Design Guidelines The schematic for the EVAL board is shown in Fig. 3. The EVAL board is configured as follows: Be sure that the two output capacitors can handle this ripple current. Ripple current specifications are found in the capacitor data sheet for high quality capacitors intended for use in switching power supplies. The inductance can now be found: L1 = (VINMAX - VO ) * D * t AI O These inductance and duty cycle equations exclude any resistive drops due to winding resistance and MOSFET on resistance. Where: For f = 300KHz, t = 1/f V D = O ; L1 = VIN (28 - 3.3) * 3.3 * 3.33 * 10 - 6 28 1 From this calculation we choose L1 to be 10uH. Switching Regulator 1 Vout1 = 3.3V, 3A Switching Regulator 2 Vout2 = 5.0V, 3A For a 200kHz operating frequency, L1 calculates to be 14.5uH. Linear Regulator 1 Vout3 = 12V, 120mA Choosing Inductor & FET Current Rating Linear Regulator 2 Vout4 = 5V, 50mA The current-carrying capability of the inductor and MOSFETs should be sized to handle the maximum current of the supply set by the current-sense resistor, R9. Here we use the minimum current threshold value: Designing the Output Filter Before calculating the output filter inductance and output capacitor, an acceptable amount of output ripple current is to be determined. The ESR of the output capacitor multiplied by the ripple current sets the maximum allowable ripple voltage. So once the ripple voltage specification is selected, the capacitor ESR is chosen, usually based on capacitor cost and size constraints. This then sets the maximum output ripple current through the capacitor and inductor. For the EVAL board 3.3V switcher, we selected a maximum ripple voltage of 50mV. Choosing two 220uF, 6.3V tantalum capacitors C22 & C23, each having an ESR of 100m, their combined ESR equaling 50m, sets the maximum ripple current as follows: A IO = A VO ESR A IO = 0.05 = 1A 0.05 R9 = 80mV I PEAK Where Ipeak equals: I PEAK = I OUT + AI O 2 Ipeak = 3.5 A R9 = 0.080 = 0.023 U 3.5 Here we choose a sense resistor of 20m. Now we can determine FET and inductor current carrying capability by using the maximum current limit threshold: 11 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 I PEAK = 0.120 R9 = 0.120 0.020 Step 2: Determine the Maximum & Minimum ESR Capacitance = 6 From this value choose an inductor with Isat > 6A, and for the FET choose a continuous conduction current rating greater than 6A. The same calculation process can be made for the 5V supply for its inductor L2 and current sense resistor, R8. L2 = 13.4 uH at 300KHz, 20uH at 200KHz. For our EVAL board we choose the transformer with a 11uH primary inductance at the expense of slightly higher ripple current. R8 = 0.02 Co = C18 = 330uF/10V Calculating output capacitance and ESR for Stability. Now that the basic output filter has been designed, it is time to check if the output filter will allow stable operation. Since the control loop is internal to the SC1402, the output filter capacitor and its associated equivalent series resistance (ESR), will affect stability. It is important to choose a capacitor with its ESR for stable SMPS operation. A seven step procedure for choosing the output capacitor and ESR ensuring a stable control loop is shown below for the 3.3V supply. The same procedure should also be implemented for the 5V supply. Vinmin = 6V Where Fs is the switching frequency. Vout is the output voltage. Vinmin is the minimum input voltage. Vref is the SC1402 reference voltage. Rs is the sense resistor, (R9 on the EVAL board). Step 1: Determine the Crossover Frequency Fs Fc = Vout 3 * 1+ Vinmin ESRmin = Vout * Rs = 0 .026 Vref ESRmax (1.2 )2 = 0 .018 Step 3: Determine the Minimum Output Capacitance Comin = The results are: System Parameters: Fs = 300kHz Vout = 3.3V Vref = 2.5V Rs = 0.020 ESRmax = Vref 2 * * Fc * Vout * Rs * tan 30 0 ( ) Comin = 162uF Step 4: Determine the Actual Output Capacitance Co = ESRmax * Comin ESRmin Co = 233uF Step 5: Determine the Actual ESR Value ESR = ESRmax + ESRmin 2 ESR = 0.022 U Step 6: From Above Calculations Choose: Co 233uF ESR = 0.022 U Step 7: Check the Ripple Current If Co can handle the ripple current you're done. Otherwise increase the output capacitance to handle the ripple current at maximum Vin and recheck the ESR using the equation for determining the actual output capacitance. If you are using tantalum or electrolytic capacitors you should increase the capacitance to the level approaching the calculated ESR. If you are using poly capacitors a small resistor in series with the capacitor to bring the ESR to the desired level may be necessary for stability due to their low ESR values. Fc = 64.516KHz 12 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 If your ESR value varies significantly from the calculated value and you don't want to add more capacitance or add a series resistor in the capacitor path as described above, we recommend that you bench test the supply over temperature to verify transient response and operation of the SMPS. Conversely: When the 3V output is at maximum ripple 1.5A (D = 50%), the 5V output adds 1.29A of ripple current. The worst-case ripple current is then calculated by: IRMS(MAX) = 1.5 2 + 1.29 2 = 1.98A Input Capacitor Selection Input capacitors are selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows: I RMS = VOUT * (VIN - VOUT ) * I OUT VIN The worst-case input RMS ripple current occurs at 50% duty cycle (D = 0.5 or Vin = 2 Vout) and therefore under this condition the IRMS ripple current can be approximated by: Clearly, the combined input capacitor bank must be chosen to handle 2A of ripple current under worstcase conditions. MOSFET Switches After selecting the voltage and current requirements of each MOSFET device for the upper and lower switches, the next step is to determine their power handling capability. For the EVAL board the IRF7413s meet the voltage and current requirements. These are 30V, 9A FETs. Based on 85C ambient temperature, 150C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper and Lower FETs: I RMS I = LOAD 2 Therefore, for a maximum load current of 3.0A , the input capacitors should be able to safely handle 1.5A of ripple current. For the EVAL board there are two such regulators that operate simultaneously. Each is capable of 1.5A of ripple current, although it is impossible for both regulators to be at 50% duty cycle at the same time since they have different output voltages. For the EVAL board, we choose four 10uF, 30V OSCON capacitors, two for each supply. Each capacitor has a ripple-current capability of 1.38A at 100kHz, 45C. Following the capacitor-derating chart for temperature and frequency operation at 300kHz, two of these capacitors in parallel will suffice, as calculated below: The RMS ripple-current is under a worst-case condition at full load, 3A each when both SMPSs are on. PT = TJ - TA 150 - 85 = = 1.3W e JA 50 Where: TJ = 150C; TA = 85C; JA = 50C/W Each FET must not exceed 1.3W of power dissipation. The conduction losses for the upper & lower FETs can be determined. For the calculations below, we assume a nominal input voltage of 12V, Vout = 3.3V, Iout = 3A and f = 300kHz, the Rdson value for the upper and lower FETs is 11m. We will calculate the conduction losses and switching losses for each FET. From the calculations below we are well within the 1.3W power dissipation limit as calculated above. Conduction Losses Upper FET: PCU = R DS * D * I 2 When the 5V output is at maximum ripple of 1.5A (D = 50%), the 3.3V output adds 1.41A of ripple current. P CU = 0.011 The maximum ripple current is then calculated by: Conduction Losses Lower FET: IRMS(MAX) = 1.5 2 + 1.412 = 2.06A PCL = R DS * (1 - D) * I 2 * 3.3 * 3 2 = 0.027W 12 3.3 2 PCL = 0.011 * 1 - * 3 = 0.072W 12 13 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 2A Switching Losses Upper FET: C RSS * VIN * F * I OUT 2 PSU = IG 240 * 10 -12 * 12 2 * 300000 * 3 = = 0.031W 1 Where Ig is the gate driver current. This is equal to 1A for the SC1402. Crss is the reverse transfer capacitance of the FET; in this case it equals 240pF for the IRF7413. Notice switching losses exist on the upper FET only because the clamp diode across the lower FET will turn on prior to the lower FET turning on. 3A 4A Upper & IR IRF7901D1 Lower FETs Siliconix Si4412 IR IRF7413 Siliconix Si4412 IR IRF7805 Siliconix Si4410 Input Capacitor 10uF, 30V Sanyo OS-CON 2 X 10uF, 30V Sanyo 3 X 10uF, 30V Sanyo OS-CON OS-CON Output Capacitor 330uF, 6.3V/10V* AVX TPS 2X 330uF, 6.3V/10V* 4X 330uF, 6.3V/10V* AVX TPS AVX TPS Sense Resistor 0.033, Dale WSL2010-R033-F 0.02, Dale WSL2010-R020-F 0.012, Dale WSL2512-R012-F Inductor 15uF, Coilcraft DO-3316P-153 10uF, Coilcraft DO3316P-103 4.7uF, Coilcraft DO3316P-472 *10V for 5V SMPS, 6.3V for 3V SMPS Table 2 So the total FET losses equate to: PFETS = 0.027+0.072+0.031 = 0.130W PCB Layout Note that as Vin increases the power dissipation from switching losses will also increase. This is especially important if the input to the supply is from an AC adapter. Therefore, it is necessary to check the calculations with your maximum input voltage specification. In addition, the distribution of power in the upper and lower FETs will change as input voltage increases. Other losses to consider are gate charge losses, inductor ac and copper losses, and losses in the input and output capacitors. All of these items will decrease efficiency and need to be carefully analyzed to obtain the highest efficiency possible, especially if running off battery power. As with any high frequency switching regulator it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible and properly decoupling lines that pull large amounts of current in short periods of time. To keep loop area small always use a ground plane and if possible split the plane into two areas, signal GND and power GND, then tie the two together at one point. Be sure that high current paths have low inductance by making track widths wide where possible. Basic Application Circuit The basic dual-output 3.3V / 5V synchronous buck converter is shown in Figure 1. This circuit shows the minimum requirements for successful operation. For varying current levels, Table 2 provides a useful selection of components for varying supply requirements and is based on the calculations described previously. Input voltage ranges for all designs in the table are 6.5V to 20V. Frequency used in calculations is 300KHz. 14 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 EVALUATION BOARD SCHEMATIC (Fig. 3) VIN C2 + D1 R1 10 10U,30V + 10U,30V C1 1 + CMPSH-3A C4 + 10U,30V C3 GND 10U,30V VIN 1 VDD VDD GND C5 C6 4.7U,6.3V 0.1 301K R9 CSL5 C22 330U,10V 330U,10V C21 10 C23 23 A 3.32K OPEN C 3 R11 140T3 CSH5 CSL3 .02 0.1uF 1 D8 2 7 FB5 SEQ SHDN REF TIME/ON5 1 C27 100pF R17 2M SHDN R16 2M R15 2M R14 2M C24 0.01 RUN/ON3 RESET GND JU9 8 28 R13 9 10 TTI5870 R8 .02 301K 14 +5V 13 12 C18 15 C19 C20 +5V 9 REF 6 11 C30 0.1uF 140T3 GND 1 C29 VL 100pF JU7 R12 10.7K REF REF C25 4.7U,16V 1 D7 R10 10.7K PSAVE SYNC 10.7K C28 0.1uF R23 FB3 1 GND D6 140T3 C +3.3V C26 CSH3 20 A A R20 Q4 IR7413 PGND 1 19 DL3 2 +5V 17 OPEN DL5 0.1uF IR7413 JP4 IR7413 140T3 LX5 LX3 2.2U,25V Q2 A 24 C14 C31 T2/L2 1 Q3 0.1 16 1 D4 1 C 26 D5 10uH DH5 A OPEN SC1402ISS RAW15V MBRS1100 C C17 18 21 0.1 5 2 3 C16 L1 D9 1 BST5 DH3 1 27 C VDD Q1 IR7413 1 1 4 JP3 OPEN JU2 12OUT BST3 2 25 VL CMPD2838 U1 JP5 0.01 VL 0.01 +12V 2 C11 0.1 21 C10 VL C13 4.7U,16V VL D3 C15 22 A V+ C 0.1 C9 OPEN VDD 1 C12 330U,10V 0.22 7 C8 4.7U,35V 453 C7 1 GND 1 GND 1 R18 100K 1 SYNC ON5 1 R19 JP6 1 2 1k 1 GND 1 ON3 RESET 1 4 3 2 1 1 PSAVE S1 1 SW DIP-4 Title SC1402 Eval Board 5 6 7 8 VIN Size B VL Date: Document Number Rev RTP00005 Thursday, April 13, 2000 E Sheet 1 of 1 15 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 5V LINE REGULATION 4.96 3.3V LINE REGULATION 3.29 3.28 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.95 4.94 4.93 3.27 3.26 4.92 4.91 3.25 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 3.24 30 5 7.5 10 12.5 15 17.5 20 Vini INPUT VOLTAGE (V) Vini INPUT VOLTAGE (V) ILOAD = 0.5A ILOAD = 1A ILOAD = 3A 3.29 4.954 3.284 4.948 3.278 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 5V LOAD REGULATION 4.941 4.935 4.929 3.246 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.3V LOAD REGULATION 3.259 4.916 0.6 3.24 3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Iouti , Ioutj LOAD CURRENT (A) Iouti ,Iout2 j LOAD CURRENT (A) VIN = 15V VIN = 6V VIN= 15V VIN = 6V EFFICIENCY vs. 5V LOAD CURRENT EFFICIENCY vs. 3.3V LOAD CURRENT 100 100 95 95 90 90 85 85 80 80 75 75 EFFICIENCY (%) EFFICIENCY (%) 30 j 3.265 3.253 0.3 27.5 3.271 4.923 0 25 ILOAD = 0.5A ILOAD = 1A ILOAD = 3A 4.96 4.91 22.5 70 65 60 70 65 60 55 55 50 50 45 45 40 40 35 35 30 30 0 .1 1 10 30 0 .1 Iou ti , Iou t2j 5 V LOAD CURRENT (A) VIN = 15V VIN = 6V 1 10 Iou ti , Iou t2j 3 V LOAD CURRENT (A) VIN = 15V VIN = 6V 16 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers SC1402 June 20, 2000 OUTLINE DRAWING - SSOP-28 JEDEC: MO-150AH NOTE: DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSIONS. ECN00-1004 17 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320