MOTOROLA Order Number: MC100ES7111/D Rev 0, 12/2002 SEMICONDUCTOR TECHNICAL DATA DATA SHEET Preliminary Information Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Low Voltage 1:10 Differential LVDS Clock Fanout Buffer The Motorola MC100ES7111 is a LVDS differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES7111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. MC100ES7111 MC100ES7111 LOW-VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT DRIVER Features: 1:10 differential clock fanout buffer 50 ps maximum device skew1 * * * * * * * * * SiGe technology Supports DC to 1000 MHz operation1 of clock or data signals FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A LVDS compatible differential clock outputs PECL and HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 32 lead LQFP package Functional Description The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1. AC specifications are design targets and subject to change IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer MC100ES7111 Motorola, Inc. 2002 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1 MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM CLK_SEL Q4 Q4 Q5 Q5 Q6 Q6 17 16 VCC Q2 26 15 Q7 Q2 27 14 Q7 Q1 28 13 Q8 Q5 Q5 Q1 29 12 Q8 Q6 Q6 Q7 Q7 Q8 Q8 Q0 30 11 Q9 Q0 31 10 Q9 VCC 32 9 VCC MC100ES7111 Q9 Q9 OE Figure 1. MC100ES7111 Logic Diagram 1 2 3 4 5 6 7 8 GND CLK1 18 CLK1 CLK1 19 CLK1 OE 20 OE 1 VCC 21 CLK0 0 22 25 CLK0 CLK0 23 VCC CLK_SEL CLK0 24 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 VCC VCC Q3 Q0 Q0 Q3 MC100ES7111 Figure 2. 32-Lead Package Pinout (Top View) Table 1. PIN CONFIGURATION Pin I/O Type Function CLK0, CLK0 Input HSTL/LVDS Differential HSTL or LVDS reference clock signal input CLK1, CLK1 Input PECL Differential PECL reference clock signal input CLK_SEL Input LVCMOS Reference clock input select OE Input LVCMOS Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Q[0-9], Q[0-9] Output LVDS Differential clock outputs GND Supply Negative power supply VCC Supply Positive power supply of the device (3.3V) Table 2. FUNCTION TABLE Control Default 0 CLK_SEL 0 CLK0, CLK0 (HSTL/LVDS) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input 1 OE 0 Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses. Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses. IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MOTOROLA 2 2 MC100ES7111 TIMING SOLUTIONS MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM MC100ES7111 Table 3. Absolute Maximum Ratingsa Symbol VCC VIN Min Max Unit Supply Voltage Characteristics -0.3 3.9 V VCC + 0.3 VCC + 0.3 V 20 mA 50 mA 125 C DC Input Voltage -0.3 VOUT IIN DC Output Voltage -0.3 IOUT TS DC Output Current DC Input Current Storage temperature -65 Condition V TFunc Functional temperature range TA = -40 TJ = +110 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ Max Unit MM ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V CDM ESD Protection (Charged device model) TBD V LU Latch-up immunity 200 mA CIN Input Capacitance JA Thermal resistance junction to ambient JESD 51-3, single layer test board 4.0 JESD 51-6, 2S2P multilayer test board JC TJ Thermal resistance junction to case Operating junction temperaturea (continuous operation) pF Condition Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 C/W MIL-SPEC 883E Method 1012.1 110 C MTBF = 9.1 years a. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES7111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES7111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc TIMING SOLUTIONS 3 3 MC100ES7111 MOTOROLA MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM MC100ES7111 Table 5. DC Characteristics (VCC = 3.3V5%, TJ = 0C to + 110C)a Symbol Characteristics Clock input pair CLK0, CLK0 (HSTL/LVDS differential signals) VDIF Differential input voltageb VX, IN VIH VIL IIN Differential cross point voltagec Input high voltage Min Typ Max 0.68 - 0.9 VCC-1.3 0.2 0.25 Unit Condition V VX+0.1 V V Input low voltage Input Current VX-0.1 150 mA V VIN = VX 0.1V Clock input pair CLK1, CLK1 (PECL differential signals) VPP Differential input voltaged 0.15 1.0 V Differential operation Differential cross point voltagee 1.0 VCC-0.6 VCC-0.880 V Differential operation VCC-1.475 150 V mA 0.8 V 150 mA VIN = VIH or VIN VCMR VIH VIL IIN Input voltage high Input voltage low Input Currenta VCC-1.165 VCC-1.810 V VIN = VIH or VIN LVCMOS control inputs OE, CLK_SEL VIL VIH Input voltage low IIN Input Current Input voltage high 2.0 V LVDS clock outputs (Q[0-9], Q[0-9]) VPP VOS Output Differential Voltage (peak-to-peak) 250 Output Offset Voltage 1125 mV LVDS 1275 mV LVDS TBD mA VCC pin (core) Supply current ICC Maximum Quiescent Supply Current without output termination current TBD a. DC characteristics are design targets and pending characterization. b. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. c. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. d. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. e. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MOTOROLA 4 4 MC100ES7111 TIMING SOLUTIONS MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM MC100ES7111 Table 6. AC Characteristics (VCC = 3.3V5%, TJ = 0C to + 110C) a Symbol Characteristics Clock input pair CLK0, CLK0 (HSTL/LVDS differential signals) VDIF Differential input voltagec (peak-to-peak) VX, IN fCLK Differential cross point voltaged Differential input crosspoint voltagef Typ Max 0.4 1.275 V TBD MHz TBD ps 0.2 1.0 V 1 VCC-0.6 1000 Input Frequency 1000 tPD Propagation Delay CLK1 to Q[0-9] LVDS clock outputs (Q[0-9], Q[0-9]) Differential ps Differential 50 ps Differential ps Differential Output-to-output skew (part-to-part) TBD tJIT(CC) DCO Output cycle-to-cycle jitter TBD e. f. g. h. Output duty cycle TBD TBD % DCfref= 50% Output Rise/Fall Time 0.05 TBD ns 20% to 80% 2.5T + tPD 3.5T + tPD ns T=CLK period Output disable time 50 V TBD Output-to-output skew a. b. c. d. Condition MHz tsk(O) tsk(PP) tr, tf tPDLg Unit V 0.68 Input Frequency tPD Propagation Delay CLK0 to Q[0-9] Clock input pair CLK1, CLK1 (PECL differential signals) VPP Differential input voltagee (peak-to-peak) VCMR fCLK Min tPLDh Output enable time 3T + tPD 4T + tPD ns T=CLK period AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc TIMING SOLUTIONS 5 5 MC100ES7111 MOTOROLA MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM MC100ES7111 CLKx CLKx 50% OE tPDL (OE to Qx[]) tPLD (OE to Qx[]) Qx[] Outputs disabled Qx[] Figure 3. MC100ES7111 AC test reference Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 100 W RT = 50 DUT MC100ES7111 VTT=GND Figure 4. MC100ES7111 AC test reference CLK0 CLK1 VDIF=0.6V VPP=0.8V VX=0.75V CLK0 CLK1 Q[0-9] Q[0-9] Q[0-9] Q[0-9] tPD (CLK0 to Q[0-9]) tPD (CLK1 to Q[0-9]) Figure 5. MC100ES7111 AC reference measurement waveform (HSTL input) CLK0 VCMR=VCC-1.3V Figure 6. MC100ES7111 AC reference measurement waveform (PECL input) VDIF=0.6V VX=1.2V CLK0 Q[0-9] Q[0-9] tPD (CLK0 to Q[0-9]) Figure 7. MC100ES7111 AC reference measurement waveform (LVDS input) IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MOTOROLA 6 6 MC100ES7111 TIMING SOLUTIONS MC100ES7111 Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM MC100ES7111 OUTLINE DIMENSIONS A -T-, -U-, -Z- FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T-U Z 25 1 -U- -T- B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X -Z- 9 0.20 (0.008) AC T-U Z S1 S DETAIL AD G -AB- 0.10 (0.004) AC AC T-U Z -AC- BASE METAL EE EE EE EE F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. SECTION AE-AE W K Q_ X DETAIL AD GAUGE PLANE H 0.250 (0.010) C E IDTTM Low Voltage 1:10 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc TIMING SOLUTIONS 7 7 DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC100ES7111 MOTOROLA MC100ES7111 MPC92459 PART NUMBERS 900 Low MHz Voltage Low1:10 Voltage Differential LVDS Clock LVDS Synthesizer Clock Fanout INSERT PRODUCT NAME AND DOCUMENT TITLEBuffer NETCOM NETCOM Innovate with IDT and accelerate your future networks. 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