ispLSI 5512VE (R) In-System Programmable 3.3V SuperWIDETM High Density PLD Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Generic Logic Block Generic Logic Block Input Bus Global Routing Pool (GRP) Boundary Scan Interface Generic Logic Block Input Bus Input Bus Generic Logic Block Input Bus Generic Logic Block Input Bus Generic Logic Block Generic Logic Block * IN-SYSTEM PROGRAMMABLE -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging Input Bus Generic Logic Block Input Bus * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 155 MHz Maximum Operating Frequency -- tpd = 6.5 ns Propagation Delay -- TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels -- Electrically Erasable and Reprogrammable -- Non-Volatile -- Programmable Speed/Power Logic Path Optimization Input Bus Generic Logic Block Generic Logic Block * Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE -- 3.3V Power Supply -- User Selectable 3.3V/2.5V I/O -- 24000 PLD Gates / 512 Macrocells -- Up to 256 I/O Pins -- 512 Registers -- High-Speed Global Interconnect -- SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance -- SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. -- PCB Efficient Ball Grid Array (BGA) Package Options -- Interfaces with Standard 5V TTL Devices Input Bus Functional Block Diagram Input Bus Features ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE * ARCHITECTURE FEATURES -- Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs -- Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell -- Macrocells Support Concurrent Combinatorial and Registered Functions -- Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable -- Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks -- Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options -- Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright (c) 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 5512ve_05 1 January 2002 Specifications ispLSI 5512VE Functional Block Diagram TMS TCK I/O 195 I/O 194 I/O 193 I/O 192 I/O 207 I/O 206 I/O 205 I/O 204 I/O 211 I/O 210 I/O 209 I/O 208 I/O 223 I/O 222 I/O 221 I/O 220 I/O 227 I/O 226 I/O 225 I/O 224 I/O 239 I/O 238 I/O 237 I/O 236 Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Boundary Scan Interface Generic Logic Block Generic Logic Block Input Bus Input Bus Global Routing Pool (GRP) Generic Logic Block Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus 1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Use the table below to determine which I/O is shared by package type. Package Type 256 fpBGA 272 BGA 388 fpBGA 388 BGA I/O 119 / CLK2 I/O 119 / CLK2 I/O 179 / CLK2 I/O 179 / CLK2 Multiplexed Signals I/O 131 / CLK3 I/O 131 / CLK 3 I/O 197 / CLK 3 I/O 197 / CLK 3 2 I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE CLK 0 CLK 1 1CLK 2 1CLK 3 I/O 124 I/O 125 I/O 126 I/O 127 I/O 112 I/O 113 I/O 114 I/O 115 I/O 108 I/O 109 I/O 110 I/O 111 I/O 96 I/O 97 I/O 98 I/O 99 I/O 92 I/O 93 I/O 94 I/O 95 I/O 80 I/O 81 I/O 82 I/O 83 I/O 76 I/O 77 I/O 78 I/O 79 I/O 64 I/O 65 I/O 66 I/O 67 RESET Input Bus I/O 60 I/O 61 I/O 62 I/O 63 Generic Logic Block Generic Logic Block I/O 48 I/O 49 I/O 50 I/O 51 Generic Logic Block Input Bus I/O 44 I/O 45 I/O 46 I/O 47 Generic Logic Block Generic Logic Block I/O 32 I/O 33 I/O 34 I/O 35 Input Bus Input Bus I/O 28 I/O 29 I/O 30 I/O 31 Input Bus Generic Logic Block I/O 16 I/O 17 I/O 18 I/O 19 Input Bus Input Bus I/O 12 I/O 13 I/O 14 I/O 15 Input Bus Generic Logic Block 1TOE I/O 1 I/O 2 I/O 3 Input Bus VCCIO I/O 243 I/O 242 I/O 241 I/O 240 I/O 255 I/O 254 I/O 253 I/O 252 GOE1 GOE0 Figure 1. ispLSI 5512VE Functional Block Diagram (256-I/O Option) TDI TDO I/O 191 I/O 190 I/O 189 I/O 188 I/O 179 I/O 178 I/O 177 I/O 176 I/O 175/CLK3 I/O 174 I/O 173 I/O 172 I/O 163 I/O 162 I/O 161 I/O 160 I/O 159/CLK2 I/O 158 I/O 157 I/O 156 I/O 147 I/O 146 I/O 145 I/O 144 I/O 143 I/O 142 I/O 141 I/O 140 I/O 131 I/O 130 I/O 129 I/O 128 Specifications ispLSI 5512VE The ispLSI 5000VE Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. ispLSI 5000VE Description (Continued) The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. ispLSI 5000VE Family Members Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is userselectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch. The ispLSI 5000VE Family ranges from 128 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000VE Family device matrix showing the various bondout options is shown in the table below. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin. The ispLSI 5000VE encompasses the innovative features of the ispLSI 5000VA family with several enhancements. The macrocell is optimized and the Ttype flip flop option is removed. To improve the efficiency of design fits, the Product Term Reset Logic is simplified and the polarity option as well as the Global Preset function are removed. The programmable output-delay feature (skew option) is also removed. As a result, the ispLSI 5000VE is not JEDEC compatible with the ispLSI 5000VA. ispLSI 5000VA and 5000VE pinouts may differ in the same package, however all programming and power/ground pins are located in the same locations. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. Table 1. ispLSI 5000VE Family Package Type Device ispLSI 5128VE GLBs Macrocells 100 TQFP 128 TQFP 256 fpBGA 272 BGA 388 fpBGA 388 BGA 4 128 -- 96 I/O -- -- -- -- ispLSI 5256VE 8 256 72 I/O 96 I/O 144 I/O 144 I/O -- -- ispLSI 5384VE 12 384 -- -- 192 I/O 192 I/O -- -- ispLSI 5512VE 16 512 -- -- 192 I/O 192 I/O 256 I/O 256 I/O 3 Specifications ispLSI 5512VE Figure 2. ispLSI 5512VE Block Diagram (256 I/O Version) 16 16 I/O 32 16 32 32 16 32 Q D D 160 3 PT 32 32 Q 32 D 160 3 PT 32 Q GLB10 32 D 160 3 PT 32 3 16 I/O 32 GLB4 32 D D 160 3 PT 3 16 GLB11 32 Q 16 68 16 32 32 3 PT 160 160 68 16 Q 160 160 PT 160 PT 16 I/O 16 I/O 32 GLB5 D 3 3 16 32 32 16 68 16 16 32 3 PT 160 160 16 I/O Q 160 160 PT 160 PT 68 CLK3 16 I/O 32 GLB6 D 3 3 16 GLB9 32 16 16 68 16 16 I/O 32 3 PT 160 160 68 CLK2 Q 160 160 PT 160 PT 3 16 I/O 32 GLB7 GLB8 768 32 16 160 160 PT 160 PT Q 160 160 3 PT 3 68 68 Continued on Next Page 4 CLK0 CLK1 GOE0 GOE1 RESET Specifications ispLSI 5512VE Figure 2. ispLSI 5512VE Block Diagram (256 I/O Version) -- Continued Continued on Previous Page 16 16 I/O 32 16 32 16 32 Q 32 D D 160 3 PT 16 32 Q GLB13 32 D 160 3 PT 160 PT 768 32 GLB14 32 D 160 3 PT 32 GLB15 3 16 I/O 32 GLB0 32 D D 160 3 PT 3 16 32 Q 16 68 16 32 32 3 PT 160 160 68 16 Q 160 160 PT 160 PT 16 I/O 16 I/O 32 GLB1 D 3 3 16 32 Q 16 68 16 32 32 3 PT 160 160 68 16 Q 160 160 PT 16 I/O 16 I/O 32 GLB2 D 3 3 16 32 32 16 68 68 16 32 3 PT 160 160 16 I/O Q 160 160 PT 160 PT 3 16 I/O 32 GLB3 GLB12 Q 160 160 PT 160 PT 160 160 68 68 5 3 PT 3 32 16 IO0/TOE Specifications ispLSI 5512VE Figure 3. ispLSI 5000VE Generic Logic Block (GLB) From GRP 0 1 2 66 67 Global PTOE Bus PTSA Macrocell 0 PT 0 PT 1 From PTSA PT 2 PTSA bypass PT 3 To I/O Pad PT 4 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP Macrocell 1 PT 9 PT 8 From PTSA PT 7 PTSA bypass PT 6 To I/O Pad PT 5 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 PT 79 Macrocell 15 PT 78 From PTSA PT 77 PTSA bypass PT 76 To GRP To I/O Pad PT 75 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 PT 159 Macrocell 31 PT 158 From PTSA PT 157 PTSA bypass PT 156 To GRP To I/O Pad PT 155 PTOE PT Clock PT Reset PT Preset PT 160 PT 161 4 PT 162 6 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP Specifications ispLSI 5512VE Figure 4. ispLSI 5000VE Macrocell VCCIO VCC VCCIO Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 PTOE GOE0 GOE1 TOE PTSA bypass I/O Pad D Q PTSA Slew rate Open drain Clk En PT Clock To GRP 2.5V/3.3V Output R/L Shared PT Clock CLK0 CLK1 CLK2 CLK3 Input threshold 2.5V/3.3V Clk R P PT Reset Shared PT Reset Global Reset PT Preset speed/ power Note: Not all macrocells have I/O pads. 7 To GRP Specifications ispLSI 5512VE speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but are also available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options. Global Clock Distribution The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock Figure 5. ispLSI 5000VE Global Clock Structure CLK 0 (dedicated pin) CLK0 CLK 1 (dedicated pin) CLK1 IO/CLK 2 (shared pin) to/from GRP CLK2 CLK3 IO/CLK 3 (shared pin) to/from GRP RESET (dedicated pin) Global Reset IO0/TOE (shared pin) to/from GRP TOE 8 Specifications ispLSI 5512VE Figure 6. Boundary Scan Register Circuit for I/O Pins HIGHZ EXTEST SCANIN (from previous cell) BSCAN Registers 1 D TOE BSCAN Latches Q D Normal Function OE Q 0 1 0 EXTEST PROG_MODE Normal Function 1 0 D Q D Q D Q 0 I/O Pin 1 1 0 Shift DR Clock DR SCANOUT (to next cell) Update DR Reset Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell) 0 D 1 Shift DR Clock DR 9 Q SCANOUT (to next cell) Specifications ispLSI 5512VE Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch Tbth Tbtcl Tbtcp TCK Tbtvo Tbtco TDO Valid Data Tbtcpsu Data to be captured Valid Data Tbtcph Data Captured Tbtuov Tbtuco Data to be driven out SYMBOL Tbtoz Valid Data Tbtuoz Valid Data PARAMETER MIN MAX UNITS tbtcp TCK [BSCAN test] clock pulse width 125 - ns tbtch tbtcl TCK [BSCAN test] pulse width high 62.5 - ns TCK [BSCAN test] pulse width low 62.5 - ns tbtsu TCK [BSCAN test] setup time 25 - ns tbth TCK [BSCAN test] hold time 25 - ns trf TCK [BSCAN test] rise and fall time 50 - mV/ns tbtco TAP controller falling edge of clock to valid output - 25 ns tbtoz TAP controller falling edge of clock to data output disable - 25 ns tbtvo TAP controller falling edge of clock to data output enable - 25 ns tbtcpsu BSCAN test Capture register setup time 25 - ns tbtcph BSCAN test Capture register hold time 25 - ns tbtuco BSCAN test Update reg, falling edge of clock to valid output - 50 ns tbtuoz BSCAN test Update reg, falling edge of clock to output disable - 50 ns tbtuov BSCAN test Update reg, falling edge of clock to output enable - 50 ns 10 Specifications ispLSI 5512VE Absolute Maximum Ratings 1, 2 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL MIN. MAX. UNITS Commercial TA = 0C to +70C 3.00 3.60 V Industrial TA = -40C to +85C 3.00 3.60 V 2.3 3.60 PARAMETER VCC Supply Voltage VCCIO I/O Reference Voltage V Table 2-0005/5KVE Capacitance (TA=25C,f=1.0 MHz) TYPICAL UNITS I/O Capacitance 10 pf VCC = 3.3V, VI/O = 0.0V Clock Capacitance 10 pf VCC = 3.3V, VCK = 0.0V Global Input Capacitance 10 pf VCC = 3.3V, VG = 0.0V SYMBOL C1 C2 C3 PARAMETER TEST CONDITIONS Table 2-0006/5KVE Erase Reprogram Specification PARAMETER ispLSI Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 10000 - Cycles Table 2-0008/5KVE 11 Specifications ispLSI 5512VE Switching Test Conditions Figure 9. Test Load Input Pulse Levels GND to VCCIOmin Input Rise and Fall Time VCCIO 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load R1 See Figure 9 Device Output Table 2-0003/5KVE 3-state levels are measured 0.5V from steady-state active level. Test Point C L* R2 Output Load Conditions (See Figure 9) 3.3V TEST CONDITION R1 R2 R1 316 348 511 475 35pF Active High 348 475 35pF Active Low 316 511 35pF Active High to Z at VOH -0.5V 348 475 5pF Active Low to Z at VOL+0.5V 316 511 5pF 35pF A B C D *CL includes Test Fixture and Probe Capacitance. 2.5V Slow Slew R2 0213D CL Table 2-0004A/5KVE DC Electrical Characteristics for 3.3V Range1 Over Recommended Operating Conditions SYMBOL VCCIO VIL VIH VOL VOH MIN. TYP. I/O Reference Voltage CONDITION 3.0 - 3.6 V Input Low Voltage -0.3 - 0.8 V Input High Voltage 2.0 - 5.25 V PARAMETER MAX. UNITS Output Low Voltage VCCIO = min, IOL = 8 mA - - 0.4 V Output High Voltage VCCIO = min, IOH = -4 mA 2.4 - - V Table 2-0007/5KVE 1. I/O voltage configuration must be set to VCC. 12 Specifications ispLSI 5512VE DC Electrical Characteristics for 2.5V Range1 Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER MIN. TYP. MAX. UNITS VCCIO VIL VIH I/O Reference Voltage 2.3 - 2.7 V Input Low Voltage -0.3 - 0.7 V Input High Voltage 1.7 - 5.25 V VOL Output Low Voltage - - 0.2 V VOH VCCIO=min, IOL= 100A VCCIO=min, IOL= 2mA Output High Voltage - - 0.6 V VCCIO=min, IOH= -100A 2.1 - - V VCCIO=min, IOH= -2mA 1.8 - - V 2.5V/5512VE 1. I/O voltage configuration must be set to VCCIO. DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL IIL IIH 1 IPU IBHL IBHH IBHLO IBHLH IBHT IVCCIO CONDITION PARAMETER MIN. TYP. MAX. UNITS Input or I/O Low Leakage Current 0V VIN VIL(Max.) - - -10 A Input or I/O High Leakage Current (VCCIO-0.2)V VIN VCCIO - - 10 A VCCIO VIN 5.25V - - 50 A I/O Active Pullup Current 0V VIN VIL - - -200 A Bus Hold Low Sustaining Current VIN = VIL(max) 40 - - A Bus Hold High Sustaining Current -40 - - A Bus Hold Low Overdrive Current VIN = VIH(min) 0V VIN VCCIO - - 550 A Bus Hold High Overdrive Current 0V VIN VCCIO - - -550 A VIL - VIH V - - 30 mA Bus Hold Trip Points Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax) 1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions. 13 DC Char_5KVE Specifications ispLSI 5512VE External Switching Characteristics Over Recommended Operating Conditions -155 3 PARAM. tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 TEST COND. DESCRIPTION A Data Prop. Delay, 5PT Bypass A A 4,5 -125 MIN. MAX. MIN. MAX. -- 6.5 Data Propagation Delay -- Clock Frequency with Internal Feedback1 155 UNITS -- 7.5 ns 8.0 -- 9.5 ns -- 125 -- MHz -- Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 105 -- 87 -- MHz -- Clock Frequency, Max Toggle2 200 -- 167 -- MHz -- GLB Reg. Setup Time before Clk, 5PT bypass 4.5 -- 5.0 -- ns A GLB Reg. Clock to Output Delay -- 3. 5 -- 4.5 ns -- GLB Reg. Hold Time after Clock, 5PT bypass 0.0 -- 0.0 -- ns -- GLB Reg. Setup Time before Clock 6.0 -- 7.0 -- ns -- GLB Reg. Hold Time after Clock 0.0 -- 0.0 -- ns -- GLB Reg. Setup Time before Clock, Input Reg. Path 3.0 -- 3.5 -- ns -- GLB Reg. Hold Time after Clock, Input Reg. Path 0.5 -- 0.5 -- ns A Ext. Reset Pin to Output Delay -- 9.0 -- 10.0 ns -- Ext. Reset Pulse Duration 4.5 -- 5.0 -- ns B/C Local Product Term Output Enable/Disable -- 7.0 -- 8.5 ns B/C Global Product Term Output Enable/Disable -- 13.0 -- 14.0 ns tgen/dis B/C Global OE Input to Output Enable/Disable -- 4.5 -- 5.5 ns tten/dis B/C Test OE Input to Output Enable/Disable -- 9.5 -- 10.5 ns twh -- Ext. Sync. Clock Pulse Duration, High 2.5 -- 3.0 -- ns twl -- Ext. Sync. Clock Pulse Duration, Low 2.5 -- 3.0 -- ns 6 6 Timing Ext.5512ve1.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. 7. Pulse widths less than minimum may cause unknown output behavior. 14 Specifications ispLSI 5512VE External Switching Characteristics Over Recommended Operating Conditions -100 3 PARAM. tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 tgen/dis6 TEST COND. DESCRIPTION 4,5 A Data Prop. Delay, 5PT Bypass -80 MIN. MAX. MIN. MAX. -- 10.0 -- 12.0 UNITS ns A Data Propagation Delay -- 12.0 -- 15.0 ns A Clock Frequency with Internal Feedback1 100 -- 80 -- MHz -- Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 67 -- 56 -- MHz -- Clock Frequency, Max Toggle2 125 -- 100 -- MHz -- GLB Reg. Setup Time before Clk, 5PT bypass 7.0 -- 8.0 -- ns A GLB Reg. Clock to Output Delay -- 6.0 -- 7.0 ns -- GLB Reg. Hold Time after Clock, 5PT bypass 0.0 -- 0.0 -- ns -- GLB Reg. Setup Time before Clock 9.0 -- 11.0 -- ns -- GLB Reg. Hold Time after Clock 0.0 -- 0.0 -- ns -- GLB Reg. Setup Time before Clock, Input Reg. Path 4.5 -- 5.5 -- ns -- GLB Reg. Hold Time after Clock, Input Reg. Path 1.0 -- 1.0 -- ns A Ext. Reset Pin to Output Delay -- 11.5 -- 13.0 ns -- Ext. Reset Pulse Duration 6.5 -- 8.0 -- ns B/C Local Product Term Output Enable/Disable -- 10.0 -- 12.0 ns B/C Global Product Term Output Enable/Disable -- 15.5 -- 17.0 ns B/C Global OE Input to Output Enable/Disable -- 7.5 -- 9.0 ns tten/dis6 B/C Test OE Input to Output Enable/Disable -- 11.5 -- 12.5 ns twh -- Ext. Sync. Clock Pulse Duration, High 4.0 -- 5.0 -- ns twl -- Ext. Sync. Clock Pulse Duration, Low 4.0 -- 5.0 -- ns Timing Ext.5512ve2.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O reference. 7. Pulse widths less than minimum may cause unknown output behavior. 15 Specifications ispLSI 5512VE Internal Timing Parameters Over Recommended Operating Conditions PARAMETER In/Out Delays tin tgclk_in trst tgoe tbuf ten tdis -155 -125 -100 -80 MIN MAX MIN MAX MIN MAX MIN MAX UNIT DESCRIPTION Input Buffer Delay - 1.1 - 1.3 - 2.3 - 2.3 ns Global Clock Buffer Input Delay (clk0) - 0.7 - 1.3 - 1.8 - 1.8 ns Global Reset Pin Delay - 5.8 - 6.6 - 7.1 - 7.1 ns Global OE Pin Delay - 3.2 - 3.9 - 5.9 - 7.4 ns Output Buffer Delay - 2.0 - 2.2 - 2.7 - 3.7 ns Output Enable Delay - 1.3 - 1.6 - 1.6 - 1.6 ns Output Disable Delay - 1.3 - 1.6 - 1.6 - 1.6 ns - 3.1 - 3.6 - 4.0 - 4.5 ns Routing/GLB Delays troute tpdb tpdi tptsa tfbk tinreg GRP and Logic Delay 5-pt Bypass Propagation Delay - 0.3 - 0.4 - 1.0 - 1.5 ns Combinatorial Propagation Delay - 0.0 - 0.0 - 0.0 - 0.0 ns Product Term Sharing Array - 1.8 - 2.4 - 3.0 - 4.5 ns Internal Feedback Delay - 0.0 - 0.0 - 0.0 - 0.5 ns Input Buffer to Macrocell Register Delay - 1.9 - 2.5 - 2.5 - 3.5 ns Register/Latch Delays ts ts_pt th tcoi tsl thl tgoi tpdli tces tceh tsri tsrr Register Setup Time 0.7 - 1.0 - 1.5 - 1.5 - ns Register Setup Time (Product Term Clock) 0.7 - 1.0 - 1.5 - 1.5 - ns Register Hold Time 2.8 - 3.0 - 4.0 - 5.0 - ns - 0.8 - 1.0 - 1.5 - 1.5 ns Latch Setup Time 0.7 - 1.0 - 1.5 - 1.5 - ns Latch Hold Time 2.8 - 3.0 - 4.0 - 5.0 - ns Register Clock to GLB Output Delay Latch Gate to GLB Output Delay - 0.8 - 1.0 - 1.5 - 1.5 ns GLB Latch propagation Delay - 1.0 - 1.5 - 2.0 - 2.5 ns Clock Enable Setup Time 4.1 - 4.3 - 5.3 - 6.3 - ns Clock Enable Hold Time 0.9 - 1.7 - 2.7 - 3.7 - ns Asynchronous Set/Reset to GLB Output Delay - 1.2 - 1.2 - 1.7 - 2.2 ns 0.9 - 1.2 - 1.2 - 2.2 - ns Macrocell PT Clock Delay - 0.4 - 0.4 - 0.5 - 0.5 ns Block PT Clock Delay - 1.4 - 1.9 - 2.5 - 2.5 ns Macrocell PT Set/Reset Delay - 1.1 - 3.7 - 4.8 - 4.8 ns Block PT Set/Reset Delay - 2.1 - 5.7 - 6.8 - 6.8 ns Macrocell PT OE Delay - 1.5 - 2.0 - 2.1 - 3.6 ns Global PT OE Delay - 7.5 - 7.5 - 7.6 - 8.6 Asynchronous Set/Reset Recovery Time Control Delays tptclk tbclk tptsr tbsr tptoe tgptoe Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 16 ns Timing v.2.0 Specifications ispLSI 5512VE ispLSI 5512VE Timing Parameters (continued) ADDER ADDER TYPE BASE PARAMETER -155 -125 -100 -80 UNITS troute 1.0 1.5 1.5 1.5 ns tgclk_in tgclk_in tgclk_in 1.5 1.7 1.7 1.7 ns 1.5 1.7 1.7 1.7 ns 1.5 1.7 1.7 1.7 ns 4.0 4.0 4.0 4.0 ns 0.0 0.0 0.0 0.0 ns 0.5 0.5 0.5 0.5 ns 0.0 0.0 0.0 0.0 ns 0.1 0.1 0.1 0.1 ns 0.2 0.2 0.2 0.2 ns 0.2 0.3 0.3 0.3 ns 0.3 0.4 0.4 0.4 ns 0.4 0.5 0.5 0.5 ns 0.5 0.6 0.6 0.6 ns 0.6 0.7 0.7 0.7 ns 0.6 0.8 0.8 0.8 ns 0.7 0.9 0.9 0.9 ns 0.8 1.0 1.0 1.0 ns 0.9 1.1 1.1 1.1 ns 1.0 1.2 1.2 1.2 ns 1.0 1.3 1.3 1.3 ns 1.1 1.4 1.4 1.4 ns 1.2 1.5 1.5 1.5 Routing Adders tlp Tioi Input Adders clk1 clk2 clk3 Tioo Output Adders1 Slow Slew I/O LVTTL_out LVCMOS25_out LVCMOS33_out tbuf, ten tbuf, ten, tdis tbuf, ten, tdis tbuf, ten, tdis Tbla Additional Block Loading Adders 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 troute troute troute troute troute troute troute troute troute troute troute troute troute troute troute 1Timing for open drain configurations is the same as non-open drain configurations. Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for details. 17 ns Timing Table/5512VE Timing v.2.0 Specifications ispLSI 5512VE ispLSI 5512VE Timing Model Routing/ GLB Delays tPDb From Feedback Feedback tPDi tFBK tROUTE IN tBLA tIN tPTSA DATA Q tLP tINREG CLK OUT In/Out Delays tGCLK_IN tIOI tBUF tEN tDIS tIOO tPTCLK tBCLK CE tPTSR tBSR S/R MC Reg RST tRST Register/ Latch Delays tGPTOE tPTOE OE tGOE Control Delays 5000VE Timing Model In/Out Delays Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array and VCC I/O option). 18 Specifications ispLSI 5512VE Power Consumption Power consumption in the ispLSI 5512VE device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. Each group of five product terms has a single speed/power tradeoff control fuse that acts on the complete group of five. The fast "high-speed" setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower "lowpower" setting will reduce the power dissipation for these product terms. Figure 10 shows the relationship between power and operating frequency. Figure 10. Typical Device Power Consumption vs fmax 600 ispLSI 5512VE High Speed Mode 550 ICC (mA) 500 450 400 ispLSI 5512VE Low Power Mode 350 300 250 0 20 40 60 80 100 120 140 160 fmax (MHz) Notes: Configuration of 32 16-bit Counters Typical Current at 3.3V, 25 C ICC can be estimated for the ispLSI 5512VE using the following equation: High Speed Mode: ICC = 30 + (# of PTs * 0.3030) + (# of nets * Fmax * 0.00273) Low Power Mode: ICC = 30 + (# of PTs * 0.2676) + (# of nets * Fmax * 0.00273) # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Fmax = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/5512VE 19 Specifications ispLSI 5512VE Signal Descriptions Signal Name TMS Description Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. TDI Input - This pin is the JTAG Test Data In pin used to load data. TDO Output - This pin is the JTAG Test Data Out pin used to shift data out. TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. GOE0, GOE1 Input - These two pins are the Global Output Enable input pins. RESET Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active high or low input) for this pin is selectable. I/O Input/Output - These are the general purpose I/O used by the logic array. GND Ground NC1 No connect. VCC Vcc CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. CLK2 / I/O, CLK3 / I/O Input/Output - These pins share functionality. They can be used as dedicated clock inputs for all registers, as well as I/O pins. VCCIO Input - This pin is used for optional 2.5V outputs. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. 1. NC pins are not to be connected to any active signals, VCC or GND. 20 Specifications ispLSI 5512VE Signal Configuration ispLSI 5512VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size) 16 15 14 13 12 A I/O 113 I/O 116 I/O 121 I/O 125 B I/O 108 I/O 115 I/O I/O 119/ 117 CLK2 C I/O 106 I/O 114 NC1 D I/O 105 I/O 109 E I/O 104 F 11 10 9 8 7 6 5 4 3 2 1 I/O I/O 131/ I/O 126 CLK3 133 I/O 139 I/O 140 CLK0 I/O 145 I/O 147 I/O 151 I/O 152 I/O 153 I/O 165 A I/O 124 I/O 129 I/O 132 I/O 136 CLK1 I/O 144 I/O 149 I/O 156 I/O 157 I/O 163 I/O 164 I/O 168 B I/O 120 I/O 123 I/O 128 I/O 135 I/O 138 I/O 141 I/O 143 I/O 148 I/O 155 I/O 159 I/O 160 I/O 161 I/O 172 C I/O 111 GND GND VCC GND VCC GND GND VCC GND VCC I/O 169 I/O 167 I/O 175 D NC1 I/O 101 VCC I/O 112 I/O 122 I/O 127 I/O 134 I/O 142 I/O 150 I/O 158 I/O 166 GND I/O 173 I/O 171 I/O 177 E I/O 100 I/O 102 I/O 97 GND I/O 110 I/O 118 I/O 130 I/O 137 I/O 146 I/O 154 I/O 162 I/O 174 VCC I/O 181 I/O 176 I/O 179 F G I/O 96 I/O 98 TDO VCC I/O 103 I/O 107 VCC GND GND VCC I/O 170 I/O 178 GND I/O 185 I/O 180 I/O 187 G H I/O 94 VCCIO RESET GND I/O 95 I/O 99 GND VCC VCC GND I/O 182 I/O 186 VCC I/O 184 I/O 183 I/O 188 H J I/O 93 I/O 92 I/O 90 GND I/O 91 I/O 87 GND VCC VCC GND I/O 189 I/O 3 GND I/O 191 I/O 190 TMS J K I/O 89 I/O 88 I/O 86 VCC I/O 83 I/O 79 VCC GND GND VCC I/O 10 I/O 7 VCC TDI TCK I/O 0/ TOE K L I/O 85 I/O 84 I/O 82 GND I/O 75 I/O 68 I/O 59 I/O 51 I/O 39 I/O 31 I/O 23 I/O 15 GND I/O 4 I/O 1 I/O 2 L M I/O 81 I/O 80 I/O 77 GND I/O 71 I/O 63 I/O 55 I/O 47 I/O 43 I/O 35 I/O 27 I/O 19 VCC I/O 8 I/O 6 I/O 5 M N I/O 78 I/O 74 I/O 76 VCC GND VCC GND VCC GND GND GND I/O 11 I/O 12 I/O 9 N P I/O 73 I/O 70 I/O 65 I/O 66 I/O 57 I/O 56 R I/O 72 I/O 69 I/O 62 I/O 67 I/O 64 I/O 58 I/O 48 T I/O 61 I/O 60 I/O 54 I/O 53 I/O 52 I/O 50 16 15 14 13 12 11 GND VCC I/O 41 I/O 42 I/O 36 I/O 26 I/O 22 I/O 20 I/O 13 I/O 14 P I/O 46 I/O 40 I/O 34 I/O 29 I/O 25 I/O 24 I/O 18 I/O 17 I/O 16 R I/O 49 I/O 45 I/O 44 I/O 38 I/O 37 I/O 33 I/O 32 I/O 30 I/O 28 I/O 21 T 10 9 8 7 6 5 4 3 2 1 GOE1 GOE0 ispLSI 5512VE Bottom View 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 21 Specifications ispLSI 5512VE Signal Configuration ispLSI 5512VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size) 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 A I/O 114 I/O I/O 119/ NC1 115 CLK2 I/O 122 I/O 126 I/O 129 I/O 132 I/O 136 I/O 139 I/O 140 I/O 142 I/O 146 I/O 149 I/O 151 I/O 154 I/O 158 I/O 160 I/O GND 164 A B NC1 NC1 NC1 I/O 116 I/O 121 I/O 125 I/O I/O 131/ I/O 128 CLK3 135 I/O 137 I/O 141 I/O 143 I/O 147 I/O 150 I/O 153 I/O 157 I/O 159 NC1 I/O 163 I/O 165 B C I/O 111 NC1 NC1 I/O 117 I/O 120 I/O 123 I/O 127 I/O I/O CLK0 138 144 I/O 148 I/O 152 I/O 156 NC1 I/O 162 NC1 I/O 166 I/O 169 C D I/O 109 NC1 I/O I/O GND 113 118 VCC I/O I/O I/O I/O I/O GND VCC CLK1 GND VCC GND NC1 124 133 145 155 161 I/O 167 I/O 170 D E I/O 105 I/O 108 I/O 110 F I/O 102 I/O 104 I/O VCC 107 G I/O 100 I/O 101 I/O 103 I/O 106 H I/O 97 I/O 98 I/O 99 GND J 18 I/O 130 I/O 134 I/O 112 2 1 I/O 168 I/O 171 NC1 I/O 172 E ispLSI 5512VE VCC I/O 173 I/O 175 I/O 176 F Bottom View I/O 174 I/O 177 I/O 178 I/O 179 G GND I/O 180 I/O 181 I/O 182 H GND GND GND GND I/O 183 I/O 184 I/O 185 I/O 186 J I/O TDO VCCIO RESET 96 K I/O 92 I/O 93 I/O 94 I/O 95 GND GND GND GND VCC I/O 188 I/O 187 I/O 189 K L I/O 91 I/O 89 I/O 90 VCC GND GND GND GND TCK TMS I/O 191 I/O 190 L M I/O 88 I/O 87 I/O 86 I/O 85 GND GND GND GND I/O 0/ TDI TOE M N I/O 84 I/O 83 I/O 82 P I/O 81 NC1 R I/O 79 T I/O 2 I/O 1 GND GND I/O 5 I/O 4 I/O 3 N I/O 80 I/O 77 I/O 12 I/O 9 I/O 7 I/O 6 P I/O 78 I/O 76 VCC VCC NC1 I/O 10 I/O 8 R NC1 I/O 75 I/O 74 NC1 NC1 I/O 14 I/O 13 I/O 11 T U I/O 73 I/O 70 I/O 71 GND I/O 64 VCC I/O 58 GND I/O GOE1 VCC 48 I/O 37 GND I/O 28 VCC I/O 21 GND NC1 NC1 NC1 U V I/O 72 I/O 69 I/O 68 I/O 65 I/O 62 I/O 59 I/O 55 I/O 51 I/O I/O GOE0 47 42 I/O 38 I/O 34 I/O 31 I/O 27 I/O 24 I/O 20 I/O 17 I/O 16 W NC1 NC1 I/O 66 NC1 I/O 60 I/O 56 I/O 53 I/O 50 I/O 46 I/O 45 I/O 41 I/O 39 I/O 35 I/O 32 I/O 29 I/O 25 NC1 I/O 19 NC1 NC1 W Y NC1 I/O 67 I/O 63 I/O 61 I/O 57 I/O 54 I/O 52 I/O 49 NC1 I/O 44 I/O 43 I/O 40 I/O 36 I/O 33 I/O 30 I/O 26 I/O 23 I/O 22 NC1 I/O 18 Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package. 22 I/O 15 V Specifications ispLSI 5512VE Signal Configuration ispLSI 5512VE 388-Ball fpBGA (1.0mm Ball Pitch / 23.0mm x 23.0mm Body Size) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O 170 I/O 174 I/O 178 I/O 181 I/O 184 I/O 189 I/O 192 I/O 196 I/O 201 I/O 202 I/O 207 I/O 211 I/O 215 I/O 218 I/O 223 I/O 226 I/O 231 I/O 234 I/O 237 NC1 GND A B I/O 169 GND I/O 171 I/O 175 I/O179/ I/O CLK2 182 I/O 187 I/O 191 I/O 195 I/O 200 I/O 204 I/O 208 CLK0 I/O 216 I/O 219 I/O 224 I/O 228 I/O 233 I/O 236 I/O 241 GND NC1 B C I/O 164 I/O 165 GND I/O 172 I/O 177 I/O 180 I/O 186 I/O 190 I/O 193 I/O 199 I/O 205 I/O 209 I/O 213 I/O 217 I/O 221 I/O 227 I/O 232 I/O 235 I/O 240 GND I/O 242 I/O 245 C D I/O 161 I/O 163 I/O 168 GND I/O 173 VCC I/O 183 I/O 188 VCC I/O 198 VCC I/O 210 I/O 214 VCC I/O 225 I/O 229 VCC I/O 238 GND I/O 243 I/O 246 I/O 249 D E I/O 156 I/O 160 I/O 162 I/O 166 I/O 244 I/O 247 I/O 250 I/O 252 E F I/O 153 I/O 155 I/O 159 VCC VCC I/O 251 I/O 253 I/O 256 F G I/O 147 I/O 151 I/O 154 I/O 157 VCC VCC NC1 H I/O 145 I/O 146 I/O 148 I/O 152 VCC NC1 GND GND GND GND GND GND I/O 144 VCC NC1 GND GND GND GND GND GND GND I/O 142 TDO I/O 150 GND GND GND GND GND GND GND I/O 137 I/O 139 I/O 143 GND GND GND GND GND I/O 133 GND GND GND GND J K VCCIO RESET I/O 140 I/O 141 L I/O 135 I/O 136 M I/O 131 I/O 132 I/O 134 VCC I/O197 CLK3 I/O 206 VCC VCC I/O 254 I/O 255 I/O 258 I/O 259 G NC1 VCC I/O 260 I/O 261 I/O 262 I/O 263 H GND NC1 VCC I/O 264 I/O 265 I/O 268 J GND I/O 267 I/O 269 I/O 270 I/O 271 I/O 272 K GND GND GND I/O 277 VCC I/O 276 I/O 274 I/O 273 L GND GND GND GND I/O 287 I/O 281 I/O 280 I/O 279 I/O 278 M I/O 5 TMS I/O 285 I/O 283 I/O 282 N VCC TCK TDI I/O 286 P CLK1 I/O 220 NC1 N I/O 130 I/O 128 I/O 127 I/O 126 I/O 124 GND GND GND GND GND GND GND GND P I/O 125 I/O 123 I/O 122 VCC NC1 GND GND GND GND GND GND GND GND NC1 R I/O 121 I/O 119 I/O 118 I/O 116 1 VCC NC GND GND GND GND 1 GND GND NC VCC I/O 7 I/O 4 I/O 1 I/O0/ TOE R T I/O 117 I/O 115 I/O 114 I/O 110 VCC NC1 I/O 76 GOE1 I/O 61 I/O 52 VCC I/O 13 I/O 9 I/O 6 I/O 2 T U I/O 113 I/O 112 I/O 108 VCC ispLSI 5512VE VCC I/O 14 I/O 10 I/O 8 U V I/O 109 I/O 107 I/O 105 I/O 101 Bottom View I/O 23 I/O 17 I/O 15 I/O 11 V W I/O 106 I/O 104 I/O 100 GND I/O 94 VCC I/O 85 I/O 80 VCC I/O 69 I/O 65 VCC I/O 53 VCC I/O 44 I/O 38 VCC I/O 28 GND I/O 24 I/O 18 I/O 16 W Y I/O 103 I/O 99 GND I/O 95 I/O 90 I/O 87 I/O 82 I/O 77 I/O 72 GOE0 I/O 64 I/O 60 I/O 54 I/O 49 I/O 45 I/O 41 I/O 35 I/O 32 I/O 27 GND I/O 22 I/O 19 Y AA I/O 98 GND I/O 96 I/O 91 I/O 88 I/O 84 I/O 79 I/O 74 I/O 71 I/O 68 I/O 63 I/O 59 I/O 55 I/O 50 I/O 46 I/O 42 I/O 37 I/O 34 I/O 31 I/O 26 GND I/O 20 AA I/O 97 I/O 92 I/O 89 I/O 86 I/O 81 I/O 78 I/O 73 I/O 70 I/O 67 I/O 62 I/O 58 I/O 56 I/O 51 I/O 47 I/O 43 I/O 40 I/O 36 I/O 33 I/O 29 I/O 25 GND AB 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AB GND 22 VCC 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 23 NC1 VCC Specifications ispLSI 5512VE Signal Configuration ispLSI 5512VE 388-Ball BGA (1.27mm Ball Pitch / 35.0mmx 35.0mm Body Size) 26 25 24 22 21 20 19 18 17 A GND I/O 174 I/O 179/ NC1 23 CLK2 I/O 183 I/O 187 I/O 189 I/O 193 I/O 196 I/O 199 16 15 14 13 12 11 10 9 8 7 6 5 4 3 NC1 I/O 205 I/O 209 CLK0 I/O 215 I/O 218 NC1 I/O 226 I/O 228 I/O 231 I/O 235 I/O 238 I/O 242 I/O 246 B GND GND I/O 175 I/O 177 I/O 180 I/O 184 I/O 188 I/O 191 I/O 182 I/O 186 I/O 190 NC I/O 181 VCC NC1 2 1 GND GND A I/O I/O 197/ I/O 195 CLK3 201 I/O 204 I/O 207 I/O 211 I/O 213 I/O 216 I/O 220 I/O 224 I/O 227 I/O 229 I/O 233 I/O 237 I/O 240 I/O 244 GND I/O 247 B 1 I/O 198 I/O 202 I/O 206 I/O 210 CLK1 I/O 214 I/O 217 I/O 221 I/O 225 NC1 I/O 232 I/O 236 NC 1 I/O 243 I/O 245 GND NC 1 I/O 249 C GND I/O 192 I/O 200 VCC I/O 208 GND NC1 I/O 219 VCC I/O 223 GND NC1 I/O 234 VCC I/O 241 GND I/O 250 NC1 I/O 251 D C I/O 173 I/O 171 GND I/O 178 D I/O 170 I/O 168 I/O 172 GND E I/O 166 I/O 165 NC1 I/O 169 I/O 253 I/O 254 I/O 252 I/O 255 E F I/O 163 I/O 161 NC1 VCC VCC I/O 258 I/O 256 I/O 259 F G I/O 159 I/O 157 I/O 164 I/O 162 NC1 I/O 262 I/O 260 I/O 261 G H I/O 155 I/O 154 I/O 160 NC1 GND NC1 I/O 263 I/O 265 H J I/O 153 I/O 151 I/O 156 GND I/O 264 I/O 270 I/O 267 I/O 268 J I/O 272 I/O 274 I/O 269 I/O 271 K I/O 147 K NC1 I/O 152 I/O 150 L I/O I/O 145 RESET 148 VCC GND GND GND GND GND GND VCC I/O 277 I/O 273 NC1 L I/O 143 I/O 144 I/O 146 GND GND GND GND GND GND I/O 279 I/O 281 NC1 I/O 276 M GND GND GND GND GND GND GND I/O 285 I/O 278 I/O 280 N GND GND GND GND I/O 283 I/O 287 I/O 282 NC1 P M VCCIO N I/O 141 I/O 139 TDO I/O 140 P I/O 137 I/O 135 I/O 142 GND GND GND R I/O 133 I/O 132 NC1 I/O 136 GND GND GND GND GND GND I/O 1 TDI I/O 286 TMS R T I/O 131 NC1 I/O 134 VCC GND GND GND GND GND GND VCC NC1 TCK I/O 0/ TOE T U I/O 127 I/O 125 I/O 130 I/O 128 I/O 5 I/O 7 I/O 2 I/O 4 U V I/O 124 I/O 123 I/O 126 NC1 GND I/O 11 I/O 6 I/O 8 V W I/O 121 I/O 119 I/O 122 GND ispLSI 5512VE I/O 13 I/O 15 I/O 9 I/O 10 W Y I/O 117 I/O 116 I/O 118 I/O 113 Bottom View I/O 17 I/O 19 NC1 I/O 14 Y AA I/O 115 I/O 112 I/O 114 VCC VCC I/O 22 I/O 16 I/O 18 AA AB NC1 I/O 108 I/O 110 I/O 109 I/O 24 I/O 26 I/O 20 NC1 AB AC I/O 107 NC1 I/O 106 GND I/O 97 VCC I/O 90 I/O 86 GND I/O 79 VCC NC1 I/O 68 GND I/O 64 VCC I/O 56 NC1 GND I/O 41 VCC I/O 37 GND I/O 28 I/O 23 I/O 25 AC AD I/O 105 I/O 104 GND I/O 101 I/O 99 I/O 95 I/O 92 I/O 88 I/O 84 I/O 81 I/O 77 I/O 73 I/O 70 GOE1 NC1 I/O 62 I/O 58 I/O 54 I/O 50 I/O 46 I/O 42 I/O 38 I/O 34 GND I/O 27 I/O 29 AD AE I/O 103 GND I/O 100 I/O 96 NC1 I/O 89 I/O 85 NC1 I/O 80 I/O 76 I/O 72 I/O 69 I/O 67 I/O 63 I/O 60 NC1 I/O 53 I/O 51 I/O 47 I/O 44 I/O 40 I/O 36 I/O 33 I/O 31 GND GND AE AF GND GND NC1 I/O 98 I/O 94 I/O 91 I/O 87 NC1 I/O 82 I/O 78 I/O 74 I/O 71 GOE0 I/O 65 I/O 61 I/O 59 I/O 55 I/O 52 I/O 49 I/O 45 I/O 43 NC1 I/O 35 I/O 32 NC1 GND AF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 24 2 1 Specifications ispLSI 5512VE Part Number Description ispLSI 5512VE - XXX X XXXX X Device Family Grade Blank = Commercial I = Industrial Device Number Package F256 = 256-Ball fpBGA (Thermally Enhanced) B272 = 272-Ball BGA (Thermally Enhanced) F388 = 388-Ball fpBGA (Thermally Enhanced) B388 = 388-Ball BGA (Thermally Enhanced) Speed 155 = 155 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 80 MHz fmax Power L = Low 0212/5512ve Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 155 6.5 ispLSI 5512VE-155LF256 256-Ball fpBGA 155 6.5 ispLSI 5512VE-155LB272 272-Ball BGA 388-Ball fpBGA 155 6.5 ispLSI 5512VE-155LF388 155 6.5 ispLSI 5512VE-155LB388 388-Ball BGA 125 7.5 ispLSI 5512VE-125LF256 256-Ball fpBGA 125 7.5 ispLSI 5512VE-125LB272 272-Ball BGA 125 7.5 ispLSI 5512VE-125LF388 388-Ball fpBGA 125 7.5 ispLSI 5512VE-125LB388 388-Ball BGA 100 10 ispLSI 5512VE-100LF256 256-Ball fpBGA 100 10 ispLSI 5512VE-100LB272 272-Ball BGA 100 10 ispLSI 5512VE-100LF388 388-Ball fpBGA 100 10 ispLSI 5512VE-100LB388 388-Ball BGA Table 2-0041A/5512VE INDUSTRIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 125 125 7.5 ispLSI 5512VE-125LF256I 256-Ball fpBGA 7.5 ispLSI 5512VE-125LB272I 272-Ball BGA 125 7.5 ispLSI 5512VE-125LF388I 388-Ball fpBGA 125 7.5 ispLSI 5512VE-125LB388I 388-Ball BGA 100 10 ispLSI 5512VE-100LF256I 256-Ball fpBGA 100 10 ispLSI 5512VE-100LB272I 272-Ball BGA 388-Ball fpBGA 100 10 ispLSI 5512VE-100LF388I 100 10 ispLSI 5512VE-100LB388I 388-Ball BGA 80 12 ispLSI 5512VE-80LF256I 256-Ball fpBGA 80 12 ispLSI 5512VE-80LB272I 272-Ball BGA 80 12 ispLSI 5512VE-80LF388I 388-Ball fpBGA 80 12 ispLSI 5512VE-80LB388I 388-Ball BGA The ispLI 5512VE is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster (i.e. ispLSI 5512VE-155LF256) than the Industrial speed grade (i.e. ispLSI 5512VE-125LF256I). 25 Table 2-0041B/5512VE