ANALOGDEVICES FAX-ON-DEMAND HOTLINE ,.. ~ - Page 2 ANALOG DEVICES CCOSignalProcessor for ElectronicCameras AD9803 FEATURES 3-Wire Serial IIF for Digital Control 18 MHz Correlated Double Sampler Low Noise PGA with 0 dB-30 dB Range Analog Pre-Blanl<ing Function AUX Input with Input Clamp and PGA 10-Bit 18 MSPS AID Converter Direct ADC Input with Input Clamp Internal Voltage Reference Two Auxiliary 8-Bit DACs +3 V Single Supply Operation Low Power: 150 mW at 2.7 V Supply 48-Lead LQFP Package OBS PBLK OLE FUNCTIONAL BLOCK DIAGRAM PGACONT1-2 CLPOB CLAMP CCDIN I PRODUCT DESCRIPTION The AD9803 is a complete CCD and video signal processor developed for electronic cameras. It is well suited for video camera and still-camera applications. The 18 MHz CCD signal processing chain consists of a CDS, low noise PGA, and lO-bit ADc. Required clamping circuitry and a voltage reference are also provided. The AUX input features a wideband PGA and input clamp, and can be used to sample analog video signals. The AD9803 nominally operates from a single 3 V power supply, typically dissipating 170 mW. The AD9803 is packaged in a space-saving 48-lead LQFP and is specified over an operating temperature range of -20C to +70C. AD9803 TE DOUT CLPDM AUXCONT VRT VRB DAC1 DAC2 3-W INTF ADCIN AUXIN ACLP SHP SHD ADCCLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 @ Analog Devices, Inc" 1999 ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page 3 AD9803-SPECIFICATIONS GENERAL SPECIFICATIONS (TMINto TMAX' ACVDD =ADVDD= DVDD= +2.8 V,fADCCLK = 18 MHzunlessotherwisenoted) Parameter Min TEMPERATURE Operating Storage Typ Units 70 150 C C 3.6 3.6 3.6 V V V RANGE -20 -65 POWER SUPPLY VOLTAGE (For Functional Operation) Analog Digital Digital Driver 2.7 2.7 2.7 POWER CONSUMPTION (Power-Down Modes Selected Through Serial UF) Normal Operation (D-Reg 00) High Speed AUX-MODE (D-RegOl) Reference Standby (D-Reg 10 or STBY Pin Hi) Shutdown Mode (D-Reg 11) (Specified Under Each Mode of Operation) (Specified Under AUX-MODE) 10 10 OBS MAXIMUM Max CLOCK RATE 3.0 3.0 3.0 (Specified Under Each Mode of Operation) OLE SIR AMPliFIER Gain Clock Rate AID CONVERTER Resolution Differential Nonlinearity 0-255 Code 256-1023 Code No Missing Codes Full-Scale Input Range Clock Rate 0 10 :to.5 :to.5 GUARANTEED 1.0 0.01 REFERENCE Reference Top Voltage Reference Bottom Voltage mW mW 1.75 1.25 Specifications subjccr to changc without notice. 27 dB MHz Bits TE :to.S :t 1.0 LSBs LSBs IS Vp-p MHz V V DIGITALSPECIFICATIONS (TMIN to TMAX, DRVDD = +2.7 V, CL= 20 pF unlessotherwisenoted) Parameter Symbol Min Vm VlL 1m IlL CIK 2.1 VOH VOL IoH IOL 2.1 Typ Max Units 0.6 V V LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance 10 10 10 pA pA pF LOGIC OUTPUTS High Low High Low Level Level Level Level Output Voltage Output Voltage Output Current Output Current SERIAL INTERFACE TIMING Maximum S CLK Frequency SDATA to SCLK Setup SCLK to SDATAHold SLOAD to SCLK Setup SCLK to SLOAD Hold 0.6 50 50 V V ,uA pA (Figure 35) 10 10 10 10 10 tDS tDH tLS tLH MHz ns ns ns ns Specifications subject to change without notice. -2- REV. 0 ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page ~ AD9803 CCD-MODE SPECIFICATIONS ~T~I~;~TMAX. ACVDD=ADVDD = Min Parameter POWER CONSUMPTION VDD 2.7 VDD 2.8 VDD 3.0 = = CDS Gain Allowable CCD Reset Transient] Max Input Range Before Samration] PGA Max Input Range Max Output Range Digital Gain Control (See Figure 26) Gain Control Resolution Minimum Gain (Code 0) Low Gain (Code 207) Medium Gain (Code 437) High Gain (Code 688) Max Gain (Code 1023) Analog Gain Control (See Figure 25) 0.7 V, PGACONT2 = 1.5 V PGACONTI 1000 dB mV mVp-p 1000 1000 mV p-p mV p-p -3.5 0 SIGNAL-TO-NOISE RATIO3 (@ Minimum TIMING SPECIFICATIONS4 Pipeline Delay Even-Odd OffSet Correction Disabled Even-Odd Offset Correction Enabled Internal Clock DelayS (tID) Inhibited Clock Period (tIKHIBIT) Output Delay (tOD) Output Hold Time (tHOLD) ADCCLK, SHP, SHD, Clock Period ADCCLK Hi-Level, Or Low Level SHP, SHD Minimum Pulsewidd1.6 SHP Rising Edge to SHD Rising Edge 10 (Fixed) -1.5 4 15 26 0 8 OLE 22 32 4.5 26 PGACONTI = 1.8 V, PGACONT2 = 1.5 V BLACK-LEVEL CLAMP Clamp Level (Selected by d1.eSerial IfF) CLP(O) (E-Reg 00) CLP(I) (E-Reg 01) CLP(2) (E-Reg 10) CLP(3) (E-Reg 11) Even-Odd OffSet2 MHz 0 500 OBS 34 50 66 18 :to.5 61 PGA Gain) 30 TE LSB LSB LSB LSB LSB dB Cycles Cycles TIS 15 20 2 47 20 10 20 55.6 28 14 28 NOTES lInput Signal Characteristics dcfmed as shown: 2VMAX INPUT SIGNAL W/PBLK ENABLED 2Even-Odd Offsct is described under the TIleory of Operation section. TIle Even-Odd Offsct is measured with the Even-Off Offsct correction enabled. 3SNR = 20 10glO(FuJI-Scale Voltage/R!\1S Output Noise). "20 pF loading; timing shown in Figure 1. 5Internal aperture delay for actual sampling edge. "Active Low Clock Pulse Mode (C-Rcg 00). REV. 0 -3- Bits dB dB dB dB dB dB dB 5 7 3 Specifications subject to change without notice. Units mW mW mW 18 CLOCK RATE = Max Typ 150 170 185 = MAXIMUM DVDD= +2.8 V, 1SHP = 1m = 1ADCCLK = 18 MHz unless otherwise TIS TIS TIS TIS TIS TIS ns ANALOG DEVICES fAX-ON-DEMAND HOTLINE - Page 5 AD9803-SPECIFICATIONS AUX-MODE SPECIFICATIONS to TMAX' ACVDD=ADVDD = DVDD= +2.8 V, fADCCLK = 18 MHz unless otherwise noted) (TMIN Min Parameter POWER CONSUMPTION Normal (D-Reg 00) High Speed (D-Reg 01) MAXIMUM CLOCK RATE OBS ACTIVE ClAMP (CLAMP ON) Clamp Level (Selectable by the Serial IfF) CLP(O) (E-Reg 00) CLP(1) (E-Reg 01) CLP(2) (E-Reg 10) CLP(3) (E-Reg 11) SPECIFICATIONSl Delay Clock Delay (tID) Delay (tOD) Hold Time (tHOW NOTES '20 pF loading; timing shown in Figure 2. Specifications subject to change without notice. Units mW mW 80 110 PGA Max Input Range Max Output Range Digital Gain Control Gain Control Resolution Gain (Selected by the SerialIlF) Gain(O) Gain(255) TIMING Pipeline Internal Output Output Max Typ 18 MHz 700 1000 mVp-p mVp-p 8 (Fixed) Bits -3.5 10.5 dB dB 34 50 66 18 LSB LSB LSB LSB OLE 4 (Fixed) 2 5 20 Cycles ns ns ns TE ADC-MODE SPECIFICATIONS (TMIN to TMAX' ACVDD =ADVDD= DVDD= +2.8 V,fADCCLK = 18 MHzunlessotherwisenoted) Parameter Min POWER CONSUMPTION MAXIMUM 65 (Normal D-Reg 00) CLOCK RATE ACTIVE ClAMP TIMING SPECIFICATIONS Typ Max Units mW MHz 18 (Same as AUX-MODE) (Same as AUX-MODE) Specifications subject to change without notice. DACSPECIFICATIONS (DAClandDAC2) Parameter Min RESOLUTION Typ 8 (Fixed) Max Units Bits MIN OUTPUT 0.1 V MAX OUTPUT VDD-O.l V 1 mA 500 pF MAX CURRENT LOAD MAX CAPACITIVE Specifications subject LOAD to change witllOut notice. -4- REV. 0 ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page 6 AD9803 TIMING SPECIFICATIONS CCD SHP SHD ADCCLK OBS DO-OO x N-8 N-7 x N-6 x N-5 x N-4 N-3 NOTES: 1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES. 2. ADCCLKRISINGEDGEMUSTOCCURAT LEAST15nsAFTERTHERISINGEDGEOFSHP(tINHIBIT)' 3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP. 4. OUTPUT LATENCY (7 CYCLES) SHOWN WITH EVEN-ODD OFFSET CORRECTION ENABLED. 5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN. VIDEO INPUT ADCCLK D()-D9 x N-4 OLE Figure 1. CCD-MODE Timing N-3 x N-2 x N-1 x NOTE: EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE. Figure 2. AUX-MODE EFFECTIVE PIXELS and ADC-MODE TE N+5 N x Timing OPTICAL BLACK DUMMY BLACK EFFECTIVE PIXELS CCD SIGNAL CLPOB L.c~ CLPDM L,r---l PBLK tr NOTES: 1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED. 2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 p,s WIDE. 3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p'p. 4. CLPDM OVERWRITES PBLK. 5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN. Figure 3. CCD-MODE Clamp Timing REV. 0 -5- - ANALOGDEVICES fAX-ON-DEHAND HOTLINE Page 7 AD9803 TIMING SPECIFICATIONS (CONTINUED) VIDEO SIGNAL H SYNC ACLP 1 I MANUAL CLAMPING n AUTOMATIC CLAMPING ~~ L Figure 4. AUX-MODE Clamp Timing OBS NOTE: ACLP can be used two different ways. To control the exact time of the clamp, an active low pulse is used to specify the clamp interval. Alternatively, ACLP may be tied to ground. In this configuration, the clamp circuitry will sense the most ABSOL UTE MAXIMUM RATINGS* Parameter ADVDD ACVDD DVDD DRVDD CLOCK INPurS PGACONT1, PGACONT2 PIN, DIN DOur VRT, VRB CCDBYP1, CCDBYP2 DACI, DAC2 DRVSS, DVSS, ACVSS, ADVSS Junction Temperature Storage Temperature Lead Temperature (10 sec) negative portion of the voltage. For the video will be clamped to the Active low clamp pulse signal and use this level to set the clamp waveform in Figure 4, the SYNC level black level specified in the E-Register. mode is shown. OLE With Respect To Min Max Units ADVSS, SUBST ACVSS, SUBST DVSS DRVSS DVSS SUBST SUBST DRVSS SUBST SUBST SUBST SUBST -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 6.5 6.5 6.5 6.5 DVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 DRVDD + 0.3 ADVDD + 0.3 ACVDD + 0.3 ACVDD + 0.3 +0.3 +150 +150 +300 V V V V V V V V V V V V C C C TE -65 *Strcsses above those listed under Absolute M~ximum Ratings may cause pennancnt (bmage to the device. 11lis is a stress rating only; functional operation ofthe device attllese or oilier conditions above tllose indicated in tlle operational sections of this specification is not in1plied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING Model AD9803JST Temperature Range OC to +70C GUIDE Package Description Package 48-Lead Plastic Thin Quad Flatpack ST-48 Option CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wid1.out detection. Ald1.ough d1.e AD9803 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. TI1.erefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -6- ~~-~~ REV. 0 -- ANALOGDEVICESfAX-ON-DEHAND HOTLINE - Page 8 AD9803 PIN CONFIGURATION -' >- (/) ..: 0 00(/-0 >-alaI>":>'" ""-alW a.w > > 00",-, ~~~~fiJ~1Lt~~~;::; 481147l146l145l144lJ43l1421141114Olf39lf39l1371 8--- PIN 1 IDENTIFIER AD9803 TOP VIEW (Not to Scale) OBS NC Pin # Pin Name 1,24 2-11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NC DO-D9 DRVDD DRVSS DVSS ACLP ADCCLK DVDD STBY PBLK CLPOB SHP SHD CLPDM CCDBYP2 DIN PIN CCDBYP1 PGACONT1 PGACONT2 ACVSS CLPBYP ACVDD AUXIN AUXCONT ADCIN CMLEVEL VTRBYP DAC1 DAC2 SL SCK ADVDD SDATA ADVSS SUBST. VRB VRT =NO ~~l!!Jl!!Jl.!!Jl!!Jl!!J~~~~~ 00 ooa.",o> CONNECT "'aI ~~dd~~aj~~~~Z D:c":ooOOa.-, 0 ~ a.O:;; 0 OLE 0 -' 0 PIN FUNCTION DESCRIPTIONS Type Description (See Figures 37 and 38 for Circuit DO P P P P DI P DI DI DI DI DI DI AO AI AI AO AI AI P AO P AI AI AI AO AO AO AO Dr Dr P DI P P AO AO No Connect (Should be Left Floating or TIed to Ground) Digital Data Outputs Digital Driver Supply (3 V) Digital Driver Ground Digital Ground AUX-MODE/ADC-MODE Clamp ADC Sample Clock Input Digital Supply (3 V) Power-Down Mode (Active Hi/Internal Pull-Down). Enables Reference Stand-By Mode. Pixel Blanking Black Level Restore Clamp CCD Reference Sample Clock InpUt CCD Data Sample Clock Input Input Clamp CDS Ground Bypass (0.1 flF to Ground) CDS Negative Input (Tie to Pin 27 and AC-Couple to CCD Input Signal) CDS Positive Input (See Above) CDS Ground Bypass (0.1 flF to Ground) PGA Coarse Gain Analog Control PGA Fine Gain Analog Control Analog Ground Bias Bypass (0.1 ,uP to Ground) Analog Supply (3 V) AUX-MODE InpUt AUX-MODE PGA Gain Analog Control ADC-MODE Input Common-Mode Level (0.1 flF to Ground) Bias Bypass (0.1 ,uP to Ground) DAC1 Output DAC2 Output Serial IfF Load Signal Serial IfF Clock Analog Supply (3 V) Serial IfF InpUt Data Analog Ground Analog Ground Bottom Reference (0.1 flF to Ground and 1 flF to VRT) Top Reference (0.1 flF to Ground) TE NOTE Type: AI =Analog Input, Configurations) AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. REV. 0 -7- - - ~- - - ANALOGDEVICESfAX-ON-DEHAND HOTLINE - Page 8 AD9803 EQUIVALENT INPUT CIRCUITS DVDD DAVDD ACVDD OBS DVSS Figure 5. Pins 2-11 ACVSS DAVSS (DO-D9) Figure 8. Pin 26 (DIN) and Pin 27 (PIN) ~ OLET E ACVDD 'i' ".f- DVDD DVSS Figure PGACONT1 PGACONT2 fe~ Sk!l SkU CMLEVEL gUeST DVSS 6. Pin 16, 21, 22 (ADCCLK, 1k!l SHP, SHDJ Figure 9. Pin 29 (PGACONTt) and Pin 30 (PGACONT2) ACVDD + ACVDD 10k!l 200!l I I I 30kfl gUeST Figure ACVSS 7. Pins 25, 28 (CCDBYP) b b gUeST ACVSS Figure -8- 10. Pin 32 (CLPBYP) REV. 0 - Page ANALOGDEVICES fAX-ON-DEMAND HOTLINE 113 AD9803 ACVDD f-- ~ I~~~~~~ DAC1, DAC2 OUTPUT -i f-ACVSS ADVSS Figure 11. Pin 34 (AUXIN) and Pin 36 (ADCIN) Figure 14. Pin 39 (DAC1J and 40 (DAC2) DVDD OBS DRVDD DATA OUT ACVDD ~r - 5.5kJl OPEN ANALOG SDATA RNW OLE CONTROL CLOSED - DIGITAL CONTROL SUBST 0 "CMLEVEL Figure 12. Pin 35 (AUXCONTJ ADVDD DRVSS TE Figure 15. Pin 44 (SDATA) 3kJl 20011 ~::-. ADVSS 1.1k1l ADVDD ff- SUBST Figure 13. Pin 37 (CMLEVELJ REV. 0 DVSS ADVSS Figure 16. Pin 47 (VRB) and Pin 48 (VRTJ -9- - ANALOGDEVICES fAX-ON-DEMAND HOTLINE Page 11 AD9803-Typical PerformanceCharacteristics 800000 240 I I ,,= 0.8LSB 700000 220 > E I Z 200 52 600000 VDD=3.3V (fj 1 ~ 500000 "- = ~ VDD 3.0V is a: VDD=2.8V 0 a: 400000 w aJ I (i) 180 <f) - - ~ 300000 z ~ 160 ~ 200000 140 100000 OBS 120 4 6 Figure 8 10 12 SAMPLE RATE 17. CCD-MODE - 16 14 MHz Power - 0 18 30 29 vs. Clock Rate 31 32 33 34 35 36 DIGITAL OUTPUT CODE Decimal Figure 20. CCD-MODE (PGA Gain = MIN) Grounded-Input OLE 0.6 0.4 0.2 60 30 20 I I 10 0 -10 -20 -0.2 -30 -40 -0.4 -50 -60 -0.60 150 300 450 600 750 900 DC 1023 Figure 18. CCD-MODE DNL at 18 MHz 4 1 2 TE 2ND 3 4 5 6 FREQUENCY MHz - = 3.54 7 8 9 THD at 18 MHz MHz at -3 dB) 60 THD=-54.1dB FUND 50 w\ 40 \ 30 0 20 \ -2 10 . ~ , -4 'Iuu. 0 150 Figure -20 -30 450 19. CCD-MODE 5TH 10' -50 600 750 900 -60 1023 4TH I I J .0. -40 .,)jr,,! 300 2ND 0 -10 ' }/ \ -6 -8 = Figure 21. AUX-MODE (fIN I Noise 40 ID .., 0.0 39 THD -38.7dB FUND 50 I 38 37 - 'rll 3RD- I .1 ., )'r '" . ""'F'll I DC 2 3 4 5 FREQUENCY - MHz 7 9 INL at 18 MHz Figure 22. ADC-MODE at 18 MHz (f,N = 3.54 MHz at -3 dB) -10- REV. 0 - ANALOGDEVICES fAX-ON-DEHAND HOTLINE Page 12 AD9803 THEORY OF OPERATION Introduction The AD9803 is a lO-bit analog-to-digital interface for CCD cameras. The block level diagram of the system is shown in Figure 23. The device includes a correlated double sampler (CDS), 0 dB-30 dB programmable gain amplifier (pGA), black level correction loop, input clamp and voltage reference. The only external analog circuitry required at the system level is an emitter follower buffer between the CCD output and AD9803 inputs. Programmable Gain Amplifier (PGA) The on-chip PGA provides a gain range of 0 dB-30 dB, which is "linear in dB." Typical gain characteristics are shown in Figures 25 and 26. 40 35 30 / 25 CI "I CLPDM / 20 Z ~ 15 OBS 5 DIN 0 CLPOB Figure 23. CCD Mode Signal -5 ~ Figure 24. 30 25 CI "I 20 Z ~ 15 5 / 0 -5 V /' 10 0-~ 3.0 Control 0 V 171 TE / / / ./ 341 511 682 PGA GAIN REGISTER Figure 26. PGA Gain Curve-Digital OUT 852 1023 Control As shown in Figure 27, analog PGA control is provided through the PGACONTI and PGACONT2 inputs. PGACONTI provides coarse and PGACONT2 fme (1/16) gain control. The PGA gain can also be controlled using the internal 1O-bit DAC through the serial digital interface. The gain characteristic shown in Figure 26, with the internal DAC providing the same control range as PGACONT 1. See the Serial Interface Specifications for more details. '~ ~ CDS Block Diagram The AD9803 actually uses two CDS circuits in a "ping pong" fashion to allow the system more acquisition time. In this way, the output from one of the two CDS blocks will be valid for an entire clock cycle. Thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a singlechannel CDS system. This lower bandwidth translates to lower power and noise. PGACONT1 PGACONT2 ~ PGACONT1 PGACONT2 Figure REV. 0 2.5 1.5 2.0 PGACONT1 - Volts 35 SIH d2 1.0 0.5 OLE IH t 0 V 40 Path Figure 24 shows the block diagram of the AD9803's CDS. The S/H blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers. This implementation relies on the off-chip emitter follower buffer to drive the two 10 pF sampling capacitors. Only one capacitor at a time is seen at the input pin. Q1 / ./ Figure 25. PGA Gain Curve-Analog Correlated Double Sampling (CDS) CDS is important in high performance CCD systems as a method for removing several types of noise. Basically, two samples of the CCD output are taken: one with the signal present ("data") and one without ("reference"). Subtracting these two samples removes any noise which is common--or correlated-to both. FROM CCD ;1" /, 10 PIN / -11- 27. =COARSE CONTROL Analog PGA = FINE (1/16) CONTROL Control ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page 13 AD9803 Black Level Clamping For correct signal processing, the CCD signal must be referenced to a well established "black level." The AD9803 uses the CCD's optical black (OB) pixels as a calibration signal, which is used to establish the black level. Two sources of offset are addressed during the calibration-the CCD's own "black level" offset, and the AD9803's internal offsets in the CDS and PGA circuitry. The feedback loop shown in Figure 28 is closed around the PGA during the calibration interval (CLPOB LOW) to set the black level. As the black pixels are being processed, an integrator block measures the difference between the input level and the desired reference level. This difference, or error, signal is amplified and passed to the CDS block where it is added to the incoming pixel data. As a result of this process, the black pixels are digitized at one end of the ADC range, taking maximum advantage of the available linear range of the system. Using the AD9803's serial digital interface, the black level reference may programmed to 16 LSB, 32 LSB, 48 LSB, or 64 LSB. CLPDM ~ = TO ADC Figure 30. Input Clamp Input Blanking In some applications, the AD9803's input may be exposed to large signals from the CCD, either during blanking intervals or "high speed" modes. If the signals are larger than the AD9803's I V p-p input signal range, then the on-chip input circuitry may saturate. Recovery time ITom a saturated state could be substantial. OBS To avoid problems associated with processing these large transients, the AD9803 includes an input blanking function. When active (PBLK =LOW) this function stops the CDS operation and allows the user to disconnect the CDS inputs from the CCD buffer. Additionally, the AD9803's digital outputs will all go to zero while PBLK is low. OLE IN ADC CLPOB NEGREF Figure 28. Black Level Correction Loop (Simplified) The actual implementation of this loop is slightly more complicated as shown in Figure 29. Because there are two separate CDS blocks, two black level feedback loops are required and two offset voltages are developed. Figure 29 also shows an additional PGA block in the feedback loop labeled "RPGA." The RPGA uses the same control inputs as the PGA, but has the inverse gain. The RPGA functions to attenuate by the same factor as the PGA amplifies, keeping the gain and bandwidth of the loop constant. There exists an unavoidable mismatch in the two offset voltages used to correct both CDS blocks. This mismatch causes a slight difference in the offset level for odd and even pixels, often called "pixel-to-pixel offset" or "even-odd offset." To compensate for this mismatch, the AD9803 uses a digital correction circuit after the ADC which removes the even-odd offset between the channels. TE If the input voltage exceeds the supply rail by more than 0.3 volts, then protection diodes will be turned on, increasing current flow into the AD9803 (see Equivalent Input Circuits). Such voltage levels should be externally clamped to prevent possible device damage. lO-Bit Analog-to-Digital Converter (ADC) The ADC employs a multibit pipelined architecture which is well-suited for high throughput rates while being both area and power efficient. The multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. A fully differential implementation was used to overcome headroom constraints of the single +3 V power supply. Differential Reference The AD9803 includes a 0.5 V reference based on a differential, continuous-time bandgap cell. Use of an external bypass capacitor reduces the reference drive requirements, thus lowering the power dissipation. The differential architecture was chosen for its ability to reject supply and substrate noise. Required decoupIing is shown in Figure 31. O.1.,.F IN ADC 1.,.F -1~ CLPOB ~~ Figure 31. Reference NEG REF Figure 29. Black Level Correction Loop Decoupling Internal Timing The AD9803's on-chip timing circuitry generates all clocks necessary for operation of the CDS and ADC blocks. The user needs only to synchronize the SHP and SlID clocks with the CCD wavefo=, as all other timing is handled internally. The ADCCLK signal is used to strobe the output data, and can be adjusted to accommodate desired timing. Figure 1 shows the recommended placement of ADCCLK relative to SHP and SHD. (Detailed) Input Bias Level Clamping The buffered CCD output is connected to the AD9803 through an external coupling capacitor. The dc bias point for this cou- = pling capacitor is established during the clamping (CLPDM LO'W) period using the "dummy clamp" loop shown in Figure 30. 'When closed around the CDS, this loop establishes the desired dc bias point on the coupling capacitor. -12- REV. 0 --- ANALOGDEVICESFAX-ON-DEHAND HOTLINE - Page 1~ AD9803 Even-Odd Pixel Offset Correction The AD9803 includes digital correction circuitry following the 10-bit ADC. The purpose of the digital correction is remove the residual offset between the even and odd pixel channels, which results from the "ping-pong" CDS architecture of the AD9803. The digital offset correction tracks the black level of the even and odd channels, applying the necessary digital correction value to keep them balanced. There is an additional two cycle delay when using the offset correction, resulting in pipeline delay of7 ADCCLK cycles (see Figure 1). OBS 10 The recommended method of controlling the input clamp is to simply ground the ACll' input (Pin 15) to activate the "automatic" clamping capability of the AD9803. The clamp may also be controlled with a separate clock signal. See the clamp timing in Figure 4 for more details. The THD performance for fs = 18 MHz is shown in Figure 21. When operating at fs = 18 MHz, the linearity performance is comparable to the CCD-Mode linearity, shown in Figure 18. The AUX-MODE can be operated at a sampling rate of up to 28.6 MHz. If the sample rate exceeds 18 MHz, then the High Speed AUX-MODE should be programmed through the serial interface (D-Register 01). DOUT OLE Figure 32. Digital Offset Correction Auxiliary DACs The AD9803 includes two 8-bit DACs for controlling any offchip system functions. These are voltage output DACs with near rail-to-rail output capability. Output voltage levels are programmed through the serial interface. DAC specifications are shown on page 4, and the DAC equivalent output circuit is shown in Figure 14. AUX-MODE Operation In addition to the CCD signal-processing path, the AD9803 includes an analog video-processing path. The AUXIN (pin 34) input consists of an input clamp, PGA, and ADc. Figure 33 shows the Input Configuration of this mode. The recommended value of the external ac-coupling capacitor is O.l~. The voltage droop with this capacitor value is 20 /lV/flS. REV. 0 TE Figure 33. AUX-MODE Circuit Configuration -13- ADC-MODE Operation The ADC-MODE of operation is the same as the AUX-MODE, except there is no PGA in the signal path, only the input clamp and ADC. Input specifications and timing for ADC-MODE are the same as those for AUX-MODE. The THD performance is shown in Figure 22. ANALOGDEVICESfAX-ON-DEMAND HOTLINE - Page 15 AD9803 SERIAL INTERFACE SPECIFICATIONS AO A1 A2 MODES 1 0 0 PGA 0 1 0 DAC1 1 1 0 0 0 1 DO D1 eO e1 D2 D3 D4 D5 dO d1 cO c1 D6 D7 POWER DOWN MODES 10 f1 f2 De D9 aO a1 OPERATION MODES 13 15 Ie f6 f9 gO DAC2 I hO OBS mO 1 MODES2' '-- (a) OPERATION MODES 90~ 1 1 T NOTE 'MODES2 REGISTER BIT D1 MUST BE SET TO ZERO. SELECT O L E 9 (c) CLOCK MODES (b) OUTPUT MODES hO~ T T (g) DAC11NPUT ----' (h) DAC2 INPUT. (d) POWER DOWN MODES ~ TE (e) CLAMP LEVEL ~ T (k) EXTERNAL PGA GAIN CONTROL (j) EVEN-ODD OFFSET CORRECTION Figure 34. Internal Register Map (f) PGA GAIN ~ T (m) DAC1 AND DAC2 POWER DOWN SDATA SCK -1 SL f-- tLS tLH-1 f-- l REGISTER LOADED ON RISING EDGE r- J Figure 35. Serial WRITE Operation SDATA SCK SL l 1 Figure 36. 16-Bit Serial WRITE Operation -14- REV. 0 - - Page ANALOGDEVICES fAX-ON-DEMAND HOTLINE 16 AD9803 REGISTER DESCRIPTION (a) A-REGISTER: Modes of Operation al aO Modes 0 0 I 1 0 I 0 I ADC-MODE AUX-MODE CCD-MODE CCD-MODE (b) B-REGISTER: = Gain (0) Gain (255) =00) bI bO D9 D8 D7 D6 D5 D4 D3 D2 Dl DO 0 0 I I 0 I 0 1 Normal I 0 I 0 I 0 I 0 High Impedance 1 0 OBS Clock Modes cl cO SHP-SHD 0 0 I I 0 1 0 I Active Active Active Active 0 1 Clock Pulses 0 I dO Description Normal High Speed Power-Down 1 0 0 I 0 1 0 Power-Down 2 0 0 1 I Minimum Maximum 0 0 0 1 1 1 DACI 0 0 1 1 Input (Default =00 . . .0) g7 g6 g5 g4 g3 g2 gl gO DACI Output 0 I 0 1 Minimum Maximum 0 I (h) H-REGISTER: 0 1 0 1 0 1 0 1 0 1 DAC2 Input (Default Code (0) 0 0 0 0 Code (255) 1 1 1 I =00 . . .0) 0 0 0 0 1 1 1 1 OLE (j) I-REGISTER: Low High Low High (Default Clamp Level Selection (Default eO Clamp Level 0 0 1 I 0 I 0 I 32 LSBs 48 LSBs 64 LSBs 16 LSBs (Default f9 f8 f7 f6 f5 f4 f3 f2 f1 fO Gain (0) 0 0 0 0 0 0 0 0 0 0 Gain (1023) 1 1 I I I I I 1 I I Even-Odd DAC2 Output Minimum Maximum Even-Odd 0 1 Offset Correction In Use Offset Correction Not Used =00 . . .0) CCD-Gain Minimum Maximum -15- REV. 0 ~- =0) Offset Correction External Gain (Default TE PGA Gain Control (Default kO PGA 0 External Voltage Control Through AUXCONT PGACONTI and PGACONT2 Internall0-Bit DAC Control ofPGA Gain (m) M-REGISTER: =00) Offset Correction ;0 =00) Normal Operation High Speed AUX-MODE Reference Stand-By (Same Mode as STBY Pin 18) Total Shut-Down PGA Gain Selection 0 I h7 h6 h5 h4 h3 h2 hi hO el (t) F-REGISTER: AUX-Gain (k) K-REGISTER: dl =00 . . . 0) Clamp Active Pulses Modes Modes (0) (1) (2) (3) I 0 =00) Active Active Active Active Power-Down (e) E-REGISTER: 0 I (Default Low Low High High (d) D-REGISTER: CLF CLF CLF CLF I 0 Code (0) Code (255) PGA Gain Selection (Default f9 f8 f7 f6 f5 f4 f3 f2 (g) G-REGISTER: Output Modes (Default (c) C-REGISTER: (t) F-REGISTER: (Power-On Default Value II) =0) Control DACI & DAC2 pdn (Default mO Power-Down of8-Bit DACs 0 1 8-Bit DACs Powered-Down 8-Bit DACs Operational =0) or ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page 17 AD9803 Application Circuit Utilizing the AD9803's Digital Gain Control Figure 37 shows the recommended circuit configuration for CCD-Mode operation when using the 3-wire serial interface. The analog PGA control pins, PGACONT1 and PGACONT2, should be shorted together and decoupled to ground. If the tWo auxiliary DACs are not used, then Pins 39 and 40 (DAC 1 and DAC2) may be grounded. NOTE: With the exception of a write to the PGA register during AUX-mode, all data writes must be 10 bits. During an AUX-mode write to the PGA register, only 8 bits of data are required. If more than 14 SCK rising edges are applied during a write operation, additional SCK pulses will be ignored (see Figure 35). All reads must be 10 bits to receive valid register contents. All registers default to Os on power-up, except for the A-register \\hich defaults to 11. Thus, on power-up, the AD9803 defaults to CCD mode. During the power-up phase, it is recommended that SL be HIGH and SCK be LOW to prevent accidental register write operations. SDATA may be unknown. The RNW bit ("ReadINot Write") must be LOW for all write operations to the serial interface, and IDGH when reading back from the serial interface registers. Using the AD9803 in AD9801 Sockets The AD9803 may be easily used in existing AD980 I designs without any circuit modifications. Most of the pin assignments are the same for both ICs. Table I outlines the differences. The circuit of Figure 38 shows the necessary connections for the AD9803 when used in an existing AD9801 socket. The poweron reset in the AD9803 assures that the device will power-up in CCD-mode, with analog PGA gain control. OBS APPUCA nONS INFORMA nON Power and Grounding Recommendations The AD9803 should be treated as an analog component when used in a system. The same power supply and ground plane should be used for all of the pins. In a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to analog ground for best noise performance. Separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (the analog ground plane). If the AD9803 digital outputs need to drive a bus or substantial load, then a buffer should be used at the AD9803's outputs, with the buffer referenced to system digital ground. In some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the AD9803 to separate analog and digital ground planes. If this is done, be sure to connect the two ground planes together at the AD9803. To further improve performance, isolating the driver supply DRVDD from DVDD with a ferrite bead can help reduce kickback effects during major code transitions. Alternatively, the use of damping resistors on the digital outputs will reduce the output rise times, also reducing the kickback effect. Table I. AD980l/AD9803 Pin Differences Pin No. AD9801 AD9803 AD9801 Connection 1 14 15 24 32 ADVSS DSUBST DVSS DVSS CLAMP_BIAS NC DVSS ACLP NC CLPBYP 34 35 36 ACVDD ACVDD !NT_BIASI AUXIN AUXCONT ADCIN 38 !NT _BIAS2 VTRBYP 39 40 41 42 44 MODE2 MODEl ADVSS ADVDD ADVSS DAC1 DAC2 SL SCK SDATA Ground Ground Ground Ground Decoupled with 0.1 flF to Ground +3 Volt Supply +3 Volt Supply Decoupled with 0.1 flF to Ground Decoupled with 0.1 flF to Ground Ground Ground Ground +3 Volt Supply Ground OLE -16- TE REV. 0 ANALOG DEVICES FAX-ON-DEHAND HOTLINE - Page 18 AD9803 VDD SDATA SCK SL VOUT2 VOUT1 O.1v.F O.1v.F p1" 4311421141 . CI ~ --' ... CI l.) '" l.) > '" -0: CI 0 -0: OBS DIGITAL OUTPUT DATA VCD O.1v.F VCD NC =NO CONNECT VDD O.1v.F AD9803 OLE O.1v.F O.1v.F CLPDM SHD SHP CLPOB PBLK ADCCLK ~ O.1v.F Figure 37. CCD-Mode Circuit Configuration-Digital REV. 0 - CCD f---o SIGNAL -17- INPUT TE PGA Control ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page19 AD9803 VOD O.11'-F O.11'-F ~,., O.11'-F . ICDle: e: (I) > > CD :::J (I) VDO D.11'-F OBS AD9803 PGACONT2 PGACONT1 DIGITAL OUTPUT DATA >< (I) ...J (1)(/)0.00>-><0 > (/)...J 00 e: > 0 0> 0 Q < < OLE 0 a! CD...J 0. 0. I- CD ...J ~ (I) 0. 0 (I) 1311141115111611171118111911201121 VOD O.11'-F VOO NC =NO ~ O.11'-F CONNECT CLPDM SHD SHP CLPOB PBLK STay ADCCLK Figure 38. Recommended Circuit for AD9801 Sockets -18- ~-~- TE REV. 0 ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page 20 AD9803 OUTLINE DIMENSIONS Dimensions shown in inches and (mm), 48-Lead Plastic OBS Thin Quad Flatpack (ST -48) (LQFP) .i 00 MIN ---. 00-7o...Jt,.0.007(O,18) -11... 0.004 (0.09) OLE REV. 0 TE -19-