M41T0M6T - STMicroelectronics

1/20July 2004

M41T0

SERIAL REAL-TIME CLOCK

FEATURES SUMMARY

■2.0 TO 5.5V CLOCK OPERATING VOLTAGE

■COUNTERS FOR SECONDS, MINUTES,

HOURS, DAY, DATE, MONTH, YEARS, and

CENTURY

■YEAR 2000 COMPLIANT

■I2C BUS COMPATIBLE (400kHz)

■LOW OPERATING CURRENT OF 130µA

■OPERATING TEMPERATURE OF –40 TO

85°C

■AUTOMATIC LEAP YEAR COMPENSATI ON

■SPECIAL SOFTWARE PROGRAMMABLE

OUTPUT

■OSCILLATOR STOP DETECTION

Figure 1. 8-pin SOIC Packages

SO8 (M)

TSSOP8 3x3 (DS)

M41T0

2/20

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 8-pin SOIC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. AC Testing Input/Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3/20

M41T0

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing16

Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 16

Figure 14.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 17

Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data. . . . 17

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

M41T0

4/20

SUMMARY D ESCRIPTION

The M41T0 TIMEKEEPER® RAM is a low power

Serial TIMEKEEPER with a built-in 32.768kHz os-

cillator (external crystal controlled). Eight registers

are used for the clock/calendar function and are

config ured in bi nar y c ode d d ec ima l (B CD) fo rm at.

Addresses and data are transferred serially via a

two-line bi-directional bus. The built-in address

WRITE or READ data byte.

The M41T0 is supplied in 8 lead Plastic Small Out-

line package.

Figure 2. Logic Diagram

Figure 3. SOIC Connections

Note: 1. NF pin must be tied to VSS.

Table 1. Signal Names

Note: 1. NF pin must be tied to VSS.

AI07028

OSCI

VCC

M41T0

VSS

SCL

OSCO

SDA

OUT

SDAVSS SCL

OUTOSCO

OSCI VCC

NF(1)

AI07029

M41T0

OSCI Oscillator Input

OCSO Oscillator Output

OUT Output Driver (Open Drain)

SDA Serial Da ta Addre ss Inpu t / Outpu t

SCL Serial Clo ck

NF(1) No Func tion

VCC Supply Voltage

VSS Ground

5/20

M41T0

Figure 4. Block Diagram

AI07030

SECONDS

OSCILLATOR

32.768 kHz

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

OSCI

OSCO

OUT

VCC

VSS

SCL

SDA

1 Hz

M41T0

6/20

MAXIMUM RATIN G

Stressing the dev ice above the ratin g lis ted in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the devi ce at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicro ele ctr o nic s S URE P ro gram an d other rel -

evant quality documents.

Table 2. Absolute Maximum Ratings

Note: 1. Reflow at peak tempe rature of 255°C to 260°C for < 30 seco nds (tota l thermal budget not to exceed 180 °C for between 90 and 150

seconds).

Symbol Parameter Value Unit

TSTG Storage Temperature (VCC Off, Oscillator Off) –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD(1) Lead Solder Temperature for 10 Seconds 260 °C

VIO Input or Output Voltages –0.3 to VCC + 0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

7/20

M41T0

DC AND AC PARA METERS

This section summ arizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests perfo rmed under the Measure -

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. Operating and AC Measurement Conditions

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 5. AC Testing Input/Output Waveform

Table 4. Capacitance

Note: 1. Effective c apacitance measu red with power supply at 5V; sampled only, not 100% tested.

2. At 25°C , f = 1MHz .

3. Outputs deselected.

Parameter M41T0 Unit

Supply Voltage (VCC)2.0 to 5.5 V

Ambient Operating Temperature (TA)–40 to 85 °C

Load Capacitance (CL)100 pF

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance (SCL) 7 pF

COUT(3) Outp ut Ca pacitanc e (SD A, OUT ) 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

M41T0

8/20

Tab le 5. DC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).

2. At 25° C .

Table 6. Crystal Electrical Characteristics

Note: 1. These values are extern ally supplied. STMicroelectro nics recommends t he KDS DT-38: 1TA/1TC252E12 7, Tuning F ork Type (thr u-

hole) or the DMX -26S: 1TJS125FH2A212, (SMD) quartz crystal for ind ustrial tempera ture oper ations. KDS can be cont acted at kou-

hou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.

2. Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768kHz crystal of minimum trace

lengths and isolation from RF generating signals should be taken into account.

3. RS = 40kΩ when VCC ≤ 2.5V.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Frequency (SCL) = 400kHz 3.0V 35 55 µA

5.5V 130 200 µA

ICC2(2) Supply Current (Standby) All inputs = VCC – 0.2V

Frequency (SCL) = 0Hz 3.0V 0.9 1.2 µA

5.5V 31 µA

VIL Input Low Voltage –0.3 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC +

0.3 V

VOL

Output Low Voltage IOL = 3mA 0.4 V

Output Low Voltage (Open

Drain) IOL = 10mA 0.4 V

Symbol Parameter(1,2) Min Typ Max Unit

fOResona nt Fre qu en cy 32.768 kHz

RSSeries Resistance 60(3) KΩ

CLLoad Capacitance 12.5 pF

9/20

M41T0

OPERATION

The M41T0 clock operates as a slave device on

the serial bus. Access is obtained by implementing

a start con dition fo llowed by the corr ect slave ad -

dress (D0h). The 8 bytes contained in the device

can then be accessed sequentially in the following

order:

1. Seconds Register

2. Minutes Register

3. Century/Hours Register

4. Day Register

5. Date Register

6. Month Register

7. Years Register

8. Control Register

2-Wire Bus Characteristics

This bus is intended for communication between

different ICs. It con sist s of two li nes: o ne bi-di rec-

tional for data signals (SDA) and one for clock sig-

nals (SCL). Bo th t he SDA a nd the SCL lines mu st

be connected to a positive supply voltage via a

pull-up re si st or .

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High. Changes

in the data line while the clock line is High will be

interpr et ed as con t rol si gnals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from High to Low, while the clock is High,

defines the START condition.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition.

Data valid. The state of the data line represents

valid data when after a start condition, the data line

is stabl e for the dur ation of th e High perio d of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte -wi de and eac h rec eiv er ac kn owl -

edges with a ninth bit.

By definition, a device that gives out a message is

called “ transmitter” , the receiv ing device th at gets

the message is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by the master are called

“slaves”.

Acknowledge. Each byte of eight bits is followed

by one A ckn owledge Bit. Thi s Ack nowledg e Bit i s

a low level put on the bus by the receiver, whereas

the master generates an extra acknowledge relat-

ed clock pulse.

A slave receiver which is addressed is obliged to

generate an acknowledge after the reception of

each byte. Al so, a master rec eiver must gener ate

an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA l ine durin g the ackn owledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocke d out of th e slav e. In t his ca se, th e

transmitter must leave the data line High to enable

the master to generate the STOP condition.

M41T0

10/20

Figure 6. Serial Bus Data Transfer Sequence

Figure 7. Acknowledgement Sequence

Figure 8. Bus Timing Requirements Sequence

Note: P = STOP and S = START

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

11/20

M41T0

Tab le 7. AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).

2. Transmitte r must internally provide a hold time to bridge the undefined regi on (300ns max.) of th e falling edge of SCL.

Symbol Parameter(1) Min Typ Max Unit

fSCL SCL Clo ck Frequ en cy 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA STA RT Cond itio n Ho ld Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT Data Setup Time 100 ns

tHD:DAT(2) Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF T i m e th e bu s mu st be f re e be f or e a ne w tr a ns mi ss i on can start 1.3 µs

M41T0

12/20

READ Mode

In this mode, the master reads the M41T0 slave

after setting the slave address (see Figure 9.). Fo l-

lowing the WRITE Mode Control Bit (R/W = 0) and

the Acknowledge Bit, the word addr ess An is writ-

ten to the on-chip address pointer. Next the

START condition and slave address are repeated,

followed by the READ Mode Control Bit (R/W =1).

At this point, the master transmitter becomes the

master receiver. The data byte which was ad-

dressed will be transmitted and the master receiv-

er will send an Acknowledge Bit to the slave

transmitter. The address pointer is only increment-

ed on reception of an Acknowledge Bit. The

M41T0 slave transmitter will now place the data

byte at address An+1 on the bus. The master re-

ceiver r eads a nd a cknow led ges th e ne w by te a nd

the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condit io n to the slave tran sm itte r .

An alternate READ Mode may also be implement-

ed, whereby the master reads the M41T0 slave

without fir st writing to the (vol atile) address po int-

er. The first address that is read is the last one

stored in the pointer (see Figure 11., page 13).

WRITE Mode

In this mode the master transmitter transmits to

the M41T0 slave receiver. Bus protocol is shown

in Figure 12., page 13. Follo win g the ST A RT con -

dition and slave address, a logic '0' (R/W = 0) is

placed on the bus and i ndica tes to the a ddres sed

device that word address An will follow and is to be

written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the interna l add ress poi nter is inc remen ted to

the next memory location within the RAM on the

reception of an acknowledge clock. The M41T0

slave receiver will send an acknowledge clock to

the master transmitter after it has received the

slave address and again af ter it has received the

word address and each data byte (see Fi gur e 9.).

Figure 9. Slave Address Location

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

13/20

M41T0

Figure 10. READ Mode Sequence

Figure 11. Alternate READ Mode Sequence

Figure 12. WRITE Mode Sequence

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

M41T0

14/20

CLOCK OPERATION

The M41T0 is driven by a quartz controlled oscilla-

tor with a nominal frequency of 32.768kHz. The

accuracy of the Real -Time Clock depe nds on the

frequenc y of the q uartz cr ystal th at is us ed as the

time-base for the RTC. The M41T0 is tested to

meet ± 35 ppm with nominal crystal. The eight-

byte Clock Register (see Table 8., page 15) is

used to both set the clock and to read the date and

time from the clock, in a binary coded decimal for-

mat. Se conds, Minutes , and Hours are contain ed

within the first three registers. Bits D6 and D7 of

Clock Register 2 (Hours Register) contain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from '0' to '1' or from '1' to '0' at the turn

of the century (de pending upon its initi al state). If

CEB is set to a '0', CB will not toggle. Bits D0

through D2 of Register 3 contain the Day (day of

week). Registers 4, 5 and 6 contain the Date (day

of month), Month and Years. The final register is

the Control Register. Bit D7 of Register 0 contains

the STOP Bit (ST). Setting this bit to a '1' will cause

the oscillator to stop. If the device is expected to

spend a significant amount of time on the shelf, the

oscillator may be stopped to reduce current drain.

When reset to a '0' the oscillator restarts within

four second s (typi c all y one seco nd) .

The seven clock registers may be read one byte at

a time, or in a seque ntial block. T he Control Reg -

ister (A ddress loca tion 7) ma y be acc essed inde -

pendently. Provision has been made to assure

that a clock update does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of the clock reg-

isters will be delayed by 250ms to allow the READ

to be completed before the update occurs. This

will prevent a transition of data during the READ.

Note: This 250ms delay affects only the clock reg-

ister update and does not alter the actual clock

time.

Output Driver Pin

The OUT pin is an output driver that reflects the

contents of D7 of the Control Register. In other

words, when D7 of location 7 is a '0' then the OUT

pin will be driven low.

Note: The OUT pin is open drain which requires

an external pull-up resistor.

Oscillator Stop Detection

If the Oscillator Fail (OF) Bit is internally set to a '1,'

this indicates that the oscillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of the clock and date da-

ta. This bit will be set to '1' any time the osci llator

stops. T he fo llowi ng co nditio ns can ca use t he OF

Bit to be set:

– The first time power is applied (defaults to a '1'

on power-up).

– The voltage present on VCC is insufficient to

support oscillation.

– The ST Bit is set to '1.'

– External interference or removal of the crystal.

This bit will remain set to '1' until written to logic '0.'

The oscil lator must s tart and have run for at lea st

4 seconds before attempting to reset the OF Bit to

'0.' This function operates both under normal pow-

er and in battery back-up.

Initial Power-on Defaults

Upon initial application of power to the device, the

OUT Bit and OF Bit will be set to a '1,' while the ST

Bit will be set to '0 .' All other Regis ter bits will ini-

tially power- on in a rand om sta te.

15/20

M41T0

Tab le 8. Register Map

Keys: ST = STOP Bit

OUT = Outp u t level

X = Don’t ca r e

0 = Must be set to '0.'

CEB = Century Enable Bit

CB = Century Bit

OF = Oscillator Fail Bit

Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of t he century (dependent upon the initial value set).

When CEB is set to '0', CB will not toggle.

Address Data Function/Range

BCD Form at

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Secon ds Second s 00-59

1 OF 10 Minut es Minute s Minutes 00-59

2CEB (1) CB 10 Hours Hours Century/Hours 0-1/00-23

3 XXXXX Day Day 01-07

4 X X 10 Date Date Date 01-31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7OUT0XXXXXX Control

M41T0

16/20

PACKAGE MECHANICAL INFORMATION

Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing

Note: Drawing is not to scale.

Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A – 1.35 1.75 – 0.053 0.069

A1 – 0.10 0.25 – 0.004 0.010

B – 0.33 0.51 – 0.013 0.020

C – 0.19 0.25 – 0.007 0.010

D – 4.80 5.00 – 0.189 0.197

ddd– –0.10– –0.004

E – 3.80 4.00 – 0.150 0.157

e 1.27 – – 0.050 – –

H – 5.80 6.20 – 0.228 0.244

h – 0.25 0.50 – 0.010 0.020

L – 0.40 0.90 – 0.016 0.035

α–0°8°–0°8°

N8 8

SO-A

ddd

LA1 α

h x 45˚

17/20

M41T0

Figure 14. TSSOP8 – 8-le ad, Thin Shrink Small Outline , 3x3mm bod y size, Outline

Note: Drawing is not to scale.

Table 10. TSSOP8 – 8-lead, Thi n Shrink Sma ll Outli ne, 3x3mm body size, Mechanic al Data

Symb mm inches

Typ Min Max Typ Min Max

A – –1.10– –0.043

A1 – 0.05 0.15 – 0.002 0.006

A2 0.85 0.75 0.95 0.034 0.030 0.037

b – 0.25 0.40 – 0.010 0.016

c – 0.13 0.23 – 0.005 0.009

CP – – 0.10 – – 0.004

D 3.00 2.90 3.10 0.118 0.114 0.122

e 0.65 – – 0.026 – –

E 4.90 4.65 5.15 0.193 0.183 0.203

E1 3.00 2.90 3.10 0.118 0.114 0.122

L 0.55 0.40 0.70 0.022 0.0160.028 0.030

L1 0.95 – – 0.037 – –

α–0°6°–0°6°

N8 8

TSSOP8BM

EE1

A2A

M41T0

18/20

PART NUMBERING

Table 11. Ordering Information Scheme

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Example: M41T 0 M 6 T

Device Type

M41T

Supply Voltage and Write Protect Voltage

0 = VCC = 2.0 to 5.5V

Package

M = SO8 (150mils width)

DS = TSSOP8

Temperature Range

6 = –40 to 85°C

Shipping Method

blank = Tubes (Not for New Design - Use E)

E = Lead-Free Package (ECO PACK®), Tubes

F = Lead-Free Package (ECO PACK®), Tape & Reel

T = Tape & Reel (Not for New Design - Use F)

19/20

M41T0

REVISION HISTORY

Table 12. Document Revision History

Date Rev. # Revision Details

February 2003 1.0 First Issue

18-Feb-03 1.1 Add Pb-Free information (Table 2., Table 11.); update package information (Fi gu re 1.,

Figure 14.; Table 11.)

01-Apr-03 1.2 Fix package outline and data (Figure 1., Figure 14., Table 10., Table 11.)

10-Apr-03 1.3 Revert to previous package (Figure 1., Figure 14., Table 10., Table 11.)

30-Oct-03 1.4 Remove footnote (Table 2.)

30-Jun-2004 2.0 Shipping Method options updated and Note 1 removed from Table 11 ., O rd eri ng

Information Scheme. Datasheet put in new template.

23-Jul-2004 3.0 Content corrected from M41T80 to M41T0.

M41T0

20/20

Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences

of use of such informat ion nor for any inf ringement of pate nts or other rights of third parties whic h may result from it s use. N o license is gr anted

by implication or other wise under any patent or patent rights of STMicroelectronic s. Specificati ons mentioned i n this publication are s ubject

to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e not

authorize d for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.

The ST logo is a regis tered trademark of STMicroelect ronics.

All other names are the property of t heir respective owners .

STMicroelectronics GROUP OF COMPANIES

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -

Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -

Spain - Swede n - Swi tz erland - United Kingdom - United States