ICS9DBL411A
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
Four Output Differential Fanout Buffer for
PCI Express Gen 1 & 2
1
DATASHEET
STOP
LOGIC
DIF_INT
DIF_INC
DIF_LPR(3:0)
4
OE#(3:0)
4
Recommended Application: Features/Benefits:
PCI-Express fanout buffer • Low power differential fanout buffer for PCI-
Express and CPU clocks
• 20-pin MLF or TSSOP packaging
Output Features:
• 4 - low power differential output pairs
• Individual OE# control of each output pair
General Description:
The ICS9DBL411 is a 4 output lower power
differential buffer. Each output has its own OE#
pin. It has a maximum input frequency of 400 MHz.
Funtional Block Diagram
Power Groups
VDD GND
9,18 10,17 VDD_IO for DIF(3:0)
4 5 3.3V Analog VDD & GND
Description
Pin Number (TSSOP)
VDD GND
6,15 7,14 VDD_IO for DIF(3:0)
1 2 3.3V Analog VDD & GND
Pin Number (MLF) Description
Key Specifications:
• Output cycle-cycle jitter < 25ps additive
• Output to output skew: < 50ps
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
2
Pin Configuration
20-pin MLF
DIF_INT
DIF_INC
OE0#
DIF0T_LPR
DIF0C_LPR
20 19 18 17 16
VDDA 1 15 VDD_IO
GNDA 2 14 GND
OE3# 3 13 OE1#
DIF3C_LPR 4 12 DIF1T_LPR
DIF3T_LPR 5 11 DIF1C_LPR
678910
VDD_IO
GND
DIF2C_LPR
DIF2T_LPR
OE2#
9DBL411
OE0# 1 20 DIF0T_LPR
DIF_INC 2 19 DIF0C_LPR
DIF_INT 3 18 VDD_IO
VDDA 4 17 GND
GNDA 5 16 OE1#
OE3# 6 15 DIF1T_LPR
DIF3C_LPR 7 14 DIF1C_LPR
DIF3T_LPR 8 13 OE2#
VDD_IO 9 12 DIF2T_LPR
GND 10 11 DIF2C_LPR
ICS9DBL411
20- pin TSSO P
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
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ICS9DBL411A
Four Output Differential Buffer for PCI Express
3
TSSOP Pin Description
PIN #
(TSSOP) PIN NAME PIN TYPE DESCRIPTION
1OE0# IN
Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
2 DIF_INC IN Complement side of differential input clock
3 DIF_INT IN True side of differential input clock
4 VDDA PWR 3.3V Power for the Analog Core
5 GNDA GND Ground for the Analog Core
6OE3# IN
Output Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
7 DIF3C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
8 DIF3T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
9 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
10 GND GND Ground pin
11 DIF2C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
12 DIF2T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
13 OE2# IN Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
14 DIF1C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
15 DIF1T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
16 OE1# IN Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
17 GND GND Ground pin
18 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
19 DIF0C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
20 DIF0T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
4
MLF Pin Description
PIN #
(MLF) PIN NAME PIN TYPE DESCRIPTION
1 VDDA PWR 3.3V Power for the Analog Core
2 GNDA GND Ground for the Analog Core
3OE3# INOutput Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
4DIF3C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
5 DIF3T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
6 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
7 GND GND Ground pin
8DIF2C_LPR OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
9 DIF2T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
10 OE2# IN Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
11 DIF1C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
12 DIF1T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
13 OE1# IN Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
14 GND GND Ground pin
15 VDD_IO PWR Power supply for low power differential outputs, nominal 1.05V to 3.3V
16 DIF0C_LPR OUT Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
17 DIF0T_LPR OUT True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
18 OE0# IN Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
19 DIF_INC IN Complement side of differential input clock
20 DIF_INT IN True side of differential input clock
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
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ICS9DBL411A
Four Output Differential Buffer for PCI Express
5
Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Maximum Supply Voltage VDDA Core Supply Voltage 4.6 V 1,7
Maximum Supply Voltage VDD_IO Low-Voltage Differential I/O Supply 0.99 3.8 V 1,7
Maximum Input Voltage VIH 3.3V LVCMOS Inputs 4.6 V 1,7,8
Minimum Input Voltage VIL Any Input Vss - 0.5 V 1,7
Storage Temperature Ts - -65 150 °C1,7
Input ESD protection ESD prot Human Body Model 2000 V 1,7
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Ambient Operating Temp Tambient - 0 70 °C 1
Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1
Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.99 3.465 V 1
Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1
Input Low Voltage VILSE Single-ended inputs VSS - 0.3 0.8 V 1
Differential Input High Voltage VIHDIF
Differential inputs
(single-ended measurement) 600 1.15 V 1
Differential Input Low Voltage VILDIF
Differential inputs
(single-ended measurement) VSS - 0.3 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 2
Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1
IDD_3.3V 3.3V supply 25 mA 1
IDD_IO+100M VDD_IO supply @ fOP = 100MHz 15 mA 1
IDD_IO_400M VDD_IO supply @ fOP = 400MHz 54 mA 1
IDD_SB33
3.3V supply, Input stopped, OE#
pins all high 1mA 1
IDD_SBI
O
VDD_IO supply, Input stopped 0.1 mA 1
Input Frequency FiVDD = 3.3 V 33 400 MHz 2
Pin Inductance L
pin
7nH 1
CIN Logic Inputs 1.5 5 pF 1
COUT Output pin capacitance 6 pF 1
OE# latency TOE#LAT
Number of clocks to enable or
disable output from
assertion/deassertion of OE#
13periods1
Tdrive_OE# TDROE#
Output enable after
OE# de-assertion 10 ns 1
Tfall_OE# TFALL 5ns 1
Trise_OE# TRISE 5ns 1
Operating Supply Current
Standby Current
Fall/rise time of OE# inputs
Input Capacitance
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
6
AC Electrical Characteristics - DIF Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate tSLR Differential Measurement 1 2.5 V/ns 1,2
Falling Edge Slew Rate tFLR Differential Measurement 1 2.5 V/ns 1,2
Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1
Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1
Minimum Output Voltage VLOW Includes undershoot -300 mV 1
Differential Voltage Swing VSWING Differential Measurement 1200 mV 1
Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4
Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5
DCYCDIS0
Differential Measurement,
fIN<=100MHz 0.5 % 1,6
DCYCDIS1
Differential Measurement
100MHz < fIN<=267MHz +5 % 1,6
DCYCDIS2
Differential Measurement,
fIN>267MHz +7 % 1,6
DIF Jitter - Cycle to Cycle DIFJC2C
Differential Measurement,
Additive 25 ps 1
DIF[3:0] Skew DIFSKEW Differential Measurement 50 ps 1
Propagation Delay tPD Input to output Delay 2.5 3.5 ns 1
PCIe Gen2 Phase Jitter -
Addtive tphase_addHI 1.5MHz < fIN < Nyquist (50MHz) 0.8 ps rms 1
PCIe Gen2 Phase Jitter -
Addtive tphase_addLO 10KHz < fIN < 1.5MHz 0.1 ps rms 1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
8 Maximum input voltage is not to exceed maximum VDD
6 Tthis is the figure refers to the maximum distortion of the input wave form.
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
7 Operation under these conditions is neither implied, nor guaranteed.
Duty Cycle Distortion
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
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ICS9DBL411A
Four Output Differential Buffer for PCI Express
7
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
a 0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
20 6.40 6.60 .252 .260
10-0035
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP
6.40 BASIC 0.252 BASIC
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
(173 mil) (25.6 mil)
SYMBOL
INDEX
AREA
INDEX
AREA
12
1
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
-C-
b
c
L
aaa
C
α
20-pin TSSOP Package Drawing and Dimensions
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
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ICS9DBL411A
Four Output Differential Buffer for PCI Express
8
Top V iew
Index Area
D
Sawn
Singulation
Anvil
Singulation
A
0. 08 C C
A3
A1
Seating Plane
E2
E2
2
L
(N
-1)x e
(Ref.)
(Ref.)
& N
N
Even
N
e
D2
2
D2
(Re f.)
&
Odd
1
2
e2
(Typ.)
If N & N
are Even
(N -1)x
(Ref.)
b
Thermal
Base
N
OR
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
D
N
N
D
D
D
DIMENSIONS
SYMBOL MIN. MAX.
A0.81.0
A1 0 0.05 N 20
A3 ND5
b 0.18 0.3 NE5
eD x E BASIC 4.00 x 4.00
D2 MIN. / MAX. 2.00 / 2.25
E2 MIN. / MAX. 2.00 / 2.25
L MIN. / MAX. 0.45 / 0.65
ICS 20L
TOLERANCESYMBO
L
0.50 BASIC
DIMENSIONS
0.20 Reference
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
Orderi ng Inf orm ati on
P a rt / Orde r Num ber Shi ppi ng P a cka gi ng P acka ge Te m perature
9DBL411A K LF Tubes 20-pin MLF 0 to + 70°C
9DBL411A K LF T Tape and Reel 20-pin M LF 0 to + 70°C
9DBL411A GLF Tubes 20-pi n TSSOP 0 t o + 70°C
9DBL411A GLF T Tape and Reel 20-pin TS S OP 0 t o + 70°C
"LF" suffi x to the pa rt num be r are the P b-Fre e configuration and a re RoHS com pli ant.
"A" is the device revision de signator (w ill not correla te to the da ta shee t re vision).
20-pin MLF Package Drawing and Dimensions
IDT® Four Output Differential Buffer for PCI Express 1250C—06/28/12
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
9
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology , Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United S t ates
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Jap an
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
This product is protected by United States Patent NO. 7, 342, 420 and other patents.
Revision History
Rev. Issue Date Description Page #
0.1 8/1/2006 Initial Release. -
0.2 9/22/2006 Updated MLF Package Dimensions. 8
A 7/31/2007
1. Updated electrical characteristics - additive jitter, cycle-to-cycle, tpd, skews,
slew rates, Idd, etc.
2. Corrected power grouping table for TSSOP pkg
3. Final Release 1,5,6
B 2/21/2008
1. Highlighted that VIHDIF and VILDIF are single ended measurments.
2. Corrected VSWING paramater from 300mV to 1200mV.
3. Updated dut
y
c
y
cle distortion table with a 3rd fi
g
ure for speeds <=100MHz. 5
C 6/28/2012 Typo for "Differential Input Low Voltage" units; changed "V" to "mV"
