NJM2211
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FSK DEMODULATOR / TONE DECODER
■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE
The NJM2211 is a monolithic phase-locked loop (PLL) system especially
designed for data communications. It is particularly well suited for FSK modem
applications, and operates over a wide frequency range of 0.01Hz to 300kHz. It
can accommodate analog signals between 2mV and 3V, and can interface with
conventional DTL, TTL and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal frequency within the passband, a quadrature
phase detector which provides carrier detection, and an FSK voltage
comparator which provides FSK demodulation. External components are used
to independently set carrier frequency, bandwidth, and output delay.
■ FEATURES
● Wide Operating Voltage (4.5V to 20V)
● Wide frequency range (0.01Hz to 300kHz)
● DTL / TTL / ECL logic compatibility
● FSK demodulation with carrier-detector
● Wide dynamic range (2mV to 3Vrms)
● Adjustable tracking range (±1% to ±80%)
● Excellent temperature stability (20ppm / °C typical)
● Package Outline DIP14, DMP14
● Bipolar Technology
■ APPLICATIONS
● FSK demodulation
● Data synchronization
● Tone decoding
● FM detection
● Carrier detection
■ PIN CONFIGURATION
NJM2211D
NJM2211M
NJM2211D
NJM2211M
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■ BLOCK DIAGRAM
■ ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage V+ 20 V
Input Signal Level VIN 3 Vrms
Power Dissipation PD (DIP14) 700 mW
(DMP14) 300 mW
Operating Temperature Range Topr -40 to +85 °C
Storage Temperature Range Tstg -40 to +125 °C
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■ ELECTRICAL CHARACTERISTICS (V+=+12V, Ta=25°C)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Operating Voltage V+ 4.5 - 20 V
Operating Current ICC R
0 ≥ 10kΩ - 5 11 mA
Oscillator
Frequency Accuracy ∆f0 - ±1.0 - %
Frequency Stability Temp. Coefficient ∆f0 / ∆TR
1=∞ - ±20 - ppm / °C
Power Supply Rejection PSRR V+=12±1V
V+=5±0.5V
- ±0.05
±0.2
±1.5 % / V
% / V
Upper Frequency Limit f0 MAX R
0=8.2kΩ, C0=400pF - 300 - kHz
Lowest Operating Frequency f0 MIN R
0=2MΩ, C0=50µF - 0.01 - Hz
Timing Resistor
Operating Range 5 - 2000 kΩ
Timing Resistor R0
Recommended Range 15 - 100 kΩ
Loop Phase Detector
Peak Output Current I0 Meas. at pin 11 ±100 ±200 ±300 µA
Output Offset Current IOS - ±2.0 - µA
Output Impedance Z0 - 1.0 - MΩ
Maximum Voltage Swing VOM Ref. to pin 10 ±4.0 ±5.0 - V
Quadrature Phase Detector
Peak Output Current IO Meas. at Pin 3 - 150 - µA
Output Impedance - 1.0 - MΩ
Maximum Voltage Swing - 11 - VP-P
Input Preamp
Input Impedance RIN Meas. at Pin 2 - 20 - kΩ
Input Signal Voltage Required to Cause Limiting VIN - 2 - mVrms
Voltage Comparator
Input Impedance RIN Measure at Pin 3 & 8 - 2 - MΩ
Input Bias Current IB - 100 - nA
Voltage Gain GV R
L=5.1kΩ - 70 - dB
Output Voltage Low VSAT 5, 6, 7PIN IC=3mA - 0.3 1.0 V
Output Leakage Current ILEAK V
0=12V - 0.01 11 µA
Internal Reference
Output Voltage VREF Measure at Pin 10 4.75 5.30 5.85 V
Output Impedance Z0 - 100 - Ω
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■ EQUIVALENT CIRCUIT
■ CIRCUIT FUNCTION
● Signal Input (Pin 2)
The input signal is AC coupled to this terminal. The internal impedance at pin 2 is 20kΩ, Recommended input signal
leveles in the range of 10mVrms to 3Vrms.
● Quadrature Phase Detector Output (Pin 3)
This is the high-impedance output of the quadrature phase detector, and is internally connected to the input of lock-detect
voltage comparator. In tone detection applications, pin 3 is connected to ground through a parallel combination of RD and
CD (see Figure 1) to eliminate chatter at the lock-detect outputs. If this tone-detect section is not used, pin 3 can be left
open circuited.
● Lock-Detect Output, Q (Pin 5)
The output at pin 5 is at a "high" state when the PLL is out of lock and goes to a "low" or conducting state when the PLL is
locked. It is an open collector type output and required a pull-up resistor, RL, to V+ for proper operation. In the "low" state it
can sink up to 5mA of load current.
● Lock-Detect Complement, Q (Pin 6)
The output at pin 6 is the logic complement of the lock-detect output at pin 5. This output is also an open collector type
stage which can sink 5mA of load current in the low or "on" state.
● FSK Data Output (Pin 7)
This output is an open collector logic stage which requres a pull-up resistor, RL, to V+ for proper operation. It can sink 5mA
of load current. When decoding FSK signals the FSK data output will switch to a "high"or off state for low input frequency,
and will switch to a "low" or on state for high input frequency. If no input signal is present, the logic state at pin 7 is
indeterminate.
● FSK Comparator Input (Pin 8)
This is the high-impedance input to the FSK voltage comparator. Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase-detector output (pin 11). This data filter is formed by RF and CF of
Figure 1. The threshold voltage of the comparator is set by the internal reference voltage, VR, available at pin 10.
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● Reference Voltage VR (Pin 10)
This pin is internally biased at the reference voltage level, VR ; VR=V+ / 2-650mV. The DC voltage level at this pin forms
an internal reference for the voltage levels at pin 3, 8, 11, and 12. Pin 10 must be bypassed to ground with a 0.1µF
capacitor.
● Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop phase-detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VREF. The peak voltage swing available at the phase detector output is equal to ±VREF.
Figure 1. FSK & Tone Detection
● VCO Control Input (Pin 12)
VCO free-running frequency is determined by external timing resistor, R0, connected from this terminal to ground. The
VCO free-running frequency, f0, is given by :
()
0C0R
1
Hzf0=
where C0 is the timing capacitor across pins 13 and 14. For optimum temperature stability R0 must be in the range of
10kΩ to 100kΩ (see Typical Electrical Characteristics).
This terminal is a low impedance point, and is internally biased at a DC level equal to VR. The maximum timing current
drawn from pin 12 must be limited to ≤ 3mA for proper operation of the circuit.
● VCO Timing Capacitor (Pins 13 and 14)
VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals. C0 must
be non-polarized, and in the range of 200pF to 10µF.
● VCO Frequency Adjustment
VCO can be fine tuned by connecting a potentiometer, RX, in series with R0 at pin 12 (see Figure 2)
● VCO Free-Running Frequency, F0
The NJM2211 does not have a separate VCO output terminal. Instead, the VCO outputs are internally connected to the
phase-detector sections of the circuit. However, for setup or adjustment purposes, the VCO free-running frequency can
be measured at pin 3 (with CD disconnected) with no input and also pin 2 shorted to pin 10.
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■ DESIGN EQUATIONS
See Figure 1 for Definitions of Components.
1. VCO Center Frequency, f0 :
()
0C0R
1
Hzf0=
2. Internal Reference Voltage, VR (measured at pin 10) :
mV650
2
V
VS
R−
+
=
3. Loop Lowpass Filter Time Constant, τ :
τ=R1C1
4. Loop Damping, ξ :
=4
1
C
C
ξ
1
0
5. Loop Tracking Bandwidth, ±∆f/f0 :
∆f/f0 =R0 / R1
6. FSK Date Filter Time Constant, τF :
τF=RFCF
7. Loop Phase Detector Conversion Gain, Kφ :
(Kφ is the differential DC voltage across pins 10 and 11, per unit of phase error at phase-detector input) :
(
)
(
)
π
V2
radian) per volts (in K REF
φ
−
=
8. VCO conversion Gain, K0, is the amount of change in VCO frequency per unit of DC voltage change at pin 11 :
REF
0V1R0C
1
volt) per Hertz (in K −
=
9. Total Loop Gain Kτ :
K
T (in radians per second per volt =2πKφK0
=4 / C0R1
10. Peak Phase-Detector Current, IA :
25
V
)mA(I REF
A=
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■ APPLICATIONS
FSK Decoding
Figure 2 shows the basic circuit connection for FSK decoding. With reference to Figures 1 and 2, the functions of
external components are defined as follows : R0 and C0 set the PLL center frequency. R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF from a one pole post-detection filter for
the FSK data output. The resistor RB (=510kΩ) from pin 7 to pin 8 introduces positive feedback across FSK comparator
to facilitate rapid transition between output logic states.
Recommended component values for some of the most commonly used FSK bauds are given in Table 1.
Design Instructions
The circuit of Figure 2 can be tailored for any FSK decoding application by the choice of five key circuit components ;
R0, R1, C0, C1 and CF. For a given set of FSK mark and space frequencies. f1 and f2, these parameters can be
calculated as follows :
1. Calculate PLL center frequency, f0
2
ff
f21
0
+
=
2. Chose a value of timing resistor R0 to be in the range of 10kΩ to 100kΩ. This choice is arbitary. The recommended
value is R0 ≅20kΩ. The final value of R0 is normally fine-tuned with the series potentiometer, Rx.
3. Calculate value of C0 from Design Equation No.1 or from Typical Performance Characteristics :
C0=1 / R0f0
4. Calculate R1 to give a ∆f equal to the mark-space deviation :
R1=R0 [f0 / (f1 - f2)]
5. Calculate C1 to set loop damping. (See Design Equation No.4.)
Normally, ξ ≈ 1 / 2 is recommended
Then :C1=C0 / 4 for ξ =1 / 2
6. Calculate Data Filter Capacitance, CF :
For RF=100kΩ. RB=510kΩ, the recommended value of CF is :
RateBand
3
)Fµin(CF=
Note : All calculated component values except R0 can be rounded off to the nearest standard value, and R0 can be varied to fine-tune center
frequency through a series potentiometer, Rx (see Figure 2).
Table 1. Recommended Value for FSK
(Ref. Fig. 2)
FSK Band Component Values
300 Band C0=0.039µF CF=0.005µF
F1 =1070Hz C1=0.01µF R0=18kΩ
f2 =1270Hz R1=100kΩ
300 Band C0=0.022µF CF=0.005µF
f1=2025Hz C1=0.0047µF R0=18kΩ
f2=2225Hz R1=200kΩ
1200 Band C0=0.027µF CF=0.0022µF
f1=1200Hz C1=0.01µF R0=18kΩ
f2=2200Hz R1=30kΩ
Figure 2. FSK Decoding
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Figure 3. FSK Demodulation with Carrier Detect Capability Figure 4. Tone Detection
Design Example
75 Band FSK demodulator with mark / space frequencies of 1110 / 1170Hz :
Step 1 : Calculate f0 :
f
0=(1110+1170) (1 / 2)=1140Hz
Step 2 : Choose R0=20kΩ (18kΩ fixed resistor in series with 5kΩ potentiometer)
Step 3 : Calculate C0 from VCO Frequency vs. Timing Capacitor : C0 =0.044µF
Step 4 : Calculate R1 : R1=R0 (1140 / 60) =380kΩ
Step 5 : Calculate C1 : C1=C0 / 4=0.011µF
Note : All values except R0 can be rounded off to nearest standard value.
FSK Decoding With Carrier Detect
The lock-detect section of the NJM2211 can be used as a carrier detect option for FSK decoding. The recommended
circuit connection for this application is shown in Figure 3. The open-collector lock-detect output, pin 6, is shorted to the
data output (pin 7). Thus, the data output will be disabled at "low" state, until there is a carrier within the detection band of
the PLL, and the pin 6 output goes "high" to enable the data output.
The Minimum value of the lock-detect filter capacitance CD is inversely proportional to the capture range, ±∆fc. This is
the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is
further limited by C1. For most applications, ∆fc<∆f / 2, For RD=470kΩ, the approximate minimum value of CD can be
determined by :
CD (µF) ≥ 16 / capture range in Hz
With values of CD that are too small, chatter can be observed on the lock-detect output as an incoming signal
frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of the
lock-detect output.
Tone Detection
Figure 4 shows the generalized circuit connection for tone detection. The logic outputs, Q and Qat pins 5 and 6 are
normally at "high" and "low" logic states, respectively. When a tone is present within the detection band of the PLL, the
logic state at these outputs becomes reversed for the duration of the input tone. Each logic output can sink 5mA of load
current.
Both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors RL1 and RL2 as
shown in Figure 4.
With reference to Figure 1 and 4, the function of the external circuit components can be explained as follows : R0 and
C0 set VCO center frequency, R1 sets the detection bandwidth, C1 sets the lowpass-loop filter time constant and the
loop damping factor, and RL1 and RL2 are the respective pull-up resistors for the Q and Qlogic outputs.
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Design Instructions
The circuit of Figure 4 can be optimized for any tone-detection application by the choice of five key circuit
components : R0, R1, C0, C1, and CD. For a given input tone frequency, fS, these parameters are calculated as follows :
1. Chose R0 to be in the range of 15kΩ to 100kΩ. This choice is arbitrary.
2. Calculate C0 to set center frequency, f0 equal to fS : C0=1 / R0fs.
3. Calculate R1 to set bandwidth ±∆f (see Design Equation No.5) : R1=R0 (f0 / ∆f)
Note : The total detection bandwidth covers the frequency range of f0=∆f
4. Calculate value of C1 for a given loop damping factor :
C1=C0 / 16ξ2
Normally ξ ≈ 1 / 2 is optimum for most tone-detector applications, giving C1=0.25 C0.
Increasing C1 improves the out-of band signal rejection, but increases the PLL capture time.
5. Calculate value of filter capacitor CD. To avoid chatter at the logic output, with RD=470kΩ, CD must be :
C
D (µF) ≥ (16 / capture range in Hz)
Increasing CD slows the logic output response time.
Design Examples
Tone detector with a detection band of 1kHz±20Hz :
Step 1 : Choose R0=20kΩ (18kΩ in series with 5kΩ potentiometer).
Step 2 : Choose C0 for f0=1kHz : C0 =0.05µF.
Step 3 : Calculate R1 : R1=(R0)(1000 / 20)=1MΩ.
Step 4 : Calculate C1 : for ξ=1 / 2, C1=0.25µF, C2=0.013µF.
Step 5 : Calculate CD : CD=16 / 38=0.42µF.
Step 6 : Fine tune the center frequency with the 5kΩ potentiometer, RX.
Linear FM Detection
The NJM2211 can be used as a linear FM detector for a wide range of analog communications and telemetry
applications. The recommended circuit connection for the application is shown in Figure 5. The demodulated output is
taken from the loop phase detector output (pin 11), through a post detection filter made up of RF and CF, and an external
buffer amplifier. This buffer amplifier is necessary because of the high impedance output at pin 11. Normally, a
non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Figure 5.
Figure 5. Linear FM Detector
The FM detector gain, i.e., the output voltage change per unit of FM deviation, can be given as :
VOUT=R1 VR/100 R0 Volts/% deviation
where VR is the internal reference voltage. For the choice of extrernal components R1, R0, CD, C1 and CF, see the
section on Design Equations.
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■ TYPICAL CHARACTERISTICS
Operating Current VCO Frequency
Center Frequency Drift VCO Frequency
Center Frequency
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
