ANALOG DEVICES FEATURES AD363 16-Channel Data Acquisition Input Stage with: Digitally Controlled Channel Selection/Mode Control 16 Single-Ended or 8 Differential Channels 25 kHz Throughput Rate Guaranteed No Missing Codes Over Temperature AD364 16-Channel Data Acquisition Input Stage with: Digitally Controlled Channel Selection/Mode Control 16 Single-Ended or 8 Differential Channels 20 kHz Throughput Rate Guaranteed No Missing Codes Over Temperature Three-State Buffered Digital Output PRODUCT DESCRIPTIONS The AD363 and AD364 are complete 16-channel data acquisi- tion systems which condition and subsequently convert an ana- log voltage into digital form. Each system consists of two devices, an analog input stage (AIS) and an analog-to-digital converter (ADC). The AIS includes a two 8-channel multiplex- ers, a channel address register, a unity gain instrumentation am- plifier, and a sample-hold amplifier. The multiplexers may be connected to the instrumentation amplifier in either an 8- channel differential or 16-channel single ended configuration. A unique feature of these products is an internal user controlled switch which connects the multiplexers in either single-ended or differential mode. This allows a single device to perform in ei- ther mode with hard-wire programming and permits interfacing a mixture of single-ended and differential signals by dynamically switching the input mode control. The AD363 and AD364 differ in ADC performance. Each ADC is a complete 12-bit successive approximation converter includ- ing an internal clock and a precision reference. Active laser trimming results in maximum linearity errors of +0.012% with conversion times of 25 ws (AD363) or 32 ps (AD364). The hy- brid AD363-ADC has five user selectable input ranges (+2.5, +5.0, +10.0, 0 to +5, and 0 to +10 volts) and includes a high impedance buffer amplifier. The AD364-ADC is a monolithic converter with 3-state output buffer circuitry for direct interface to an 8-, 12-, or 16-bit processor bus and three user selected input ranges (+5, +10, and 0 to +10 volts). Both products are specified for operation over both the commer- cial (0C to +70C) and military (55C to +125C) temperature ranges. The AD363 and AD364 are available with environmen- tal screening. Please contact the factory or nearest sales office for details. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ANALOG INPUTS. Complete 16-Channel, 12-Bit Data Acquisition Systems AD363 FUNCTIONAL BLOCK DIAGRAM DC POWER (415, +5) [ eo AD363 AD363 SUCCESSIVE : J ANALOG INPUT ANALOG-TO-pIciTaAL PPROXIMATION] | | HI SECTION REGISTER g FoI ix wou N/) converter / 4 use (81) 1 oH DIFF ANALOG a a2 L;4 AMP ouT ma fee a4 MODE rf si Cp 4 3 P = eubhrie a ANALOG [ees 2 = 4 Lo \ SH 1 KH 86 o Spey Mux asad BUFFER C287 5 L | p88 a 1564 Ns 5 Le B10 LATCHES a is Conmmot: - LSB (B12) Loaic [| = STS ww! AB AZATAQ) CHANNEL SINGLE-ENDY [ INPUT | SELECT DIFFERENTIAL CONVERT START CHANNEL LATCH MODE SELECT SELECT AD364 FUNCTIONAL BLOCK DIAGRAM DC POWER (e1S, +5) sts r4 AD364 | | AD364 . 4 ahs. ANALOG INPUT ANALOG-TO-DIGITAL so HI SECTION Hou Vico 5) a. CAP B6-OB' z Lo DIFF ANALOG ol 1 zi 74 AMP OUT MODE 8 [ La SWITCH Tv be z & Tq -to- SIM ANALOG pp? ole Mux AMP IN Lag DB0-DB3 LATCHES [ag + CONTROL AND | | LOGIC 128 S ao Re CE AE A2 AT AO [ INPUT | CHANNEL SELECT CHANNEL SELECT LATCH SINGLE-END DIFFERENTIAL MODE SELECT One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Telex: 924491 Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASSAD363/AD364 a SPECIFICATIONS (typical @ +25C, +15 V and +5 V unless otherwise noted) Parameter AD363RK AD363RS ANALOG INPUTS Number of Inputs 16 Single-Ended or 8 Differential (Electronically Selectable) * Input Voltage Ranges Bipolar +2.5 V, +5.0 V, 10.0 V * Unipolar Oto +5 V,0to +10 V = Input (Bias) Current, per Channel +50 nA max = Input Impedance ON Channel 10' Q, 100 pF OFF Channel 10 Q, 10 pF Input Fault Current (Power OFF or ON) 20 mA, max, Internally Limited Common-Mode Rejection Differential Mode 70 dB min (80 dB) typ) @ 1 kHz, 20 V p-p * Mux Crosstalk (Interchannel, Any OFF Channel to Any ON Channel) 80 dB max (90 dB typ) @ 1 kHz, 20 V p-p * RESOLUTION 12 Bits * ACCURACY Gain Error! +0.05% FSR (Adjustable to Zero) = Unipolar Offset Error +10 mV (Adjustable to Zero) * Bipolar Offset Error +20 mV (Adjustable to Zero) * Linearity Error +1/2 LSB max * Differential Linearity Error +1 LSB max (+1/2 LSB typ) = Relative Accuracy +0.025% FSR * * Noise Error 1 mV p-p, 0.1 Hz to 1 MHz TEMPERATURE COEFFICIENTS Gain Offset, +10 V Range Differential Linearity +30 ppm/C max (+10 ppm/*C typ) +15 ppm/*C max (+5 ppm/C typ) No Missing Codes Over Temperature Range +25 ppm/C max (+15 ppm/C typ) +8 ppm/C max (+5 ppm/*C typ) * SIGNAL DYNAMICS Conversion Time* 25 ws max (22 ws typ) * Throughput Rate, Full Rated Accuracy 25 kHz min (30 kHz typ) * Sample-and-Hold Aperture Delay 200 ns max (150 ns typ) z Aperture Uncertainty 500 ps max (100 ps typ) * Acquisition Time To +0.01% of Final Value 18 ws max (10 ps typ) bs For Full-Scale Step Feedthrough 70 dB max (80 dB typ) @ 1 kHz * Droop Rate 2 mV/ms max (1 mV/ms typ) * DIGITAL INPUT SIGNALS? Convert Command (to ADC Section, Pin 21) Positive Pulse, 200 ns min Width. Leading Edge (0 to 1") Resets Register, Trailing Edge (1" to 0") Starts Conversion * 1 TTL Load = Input Channel Select (to Analog Input Section, Pins 28-31) 4-Bit Binary Channel Address * 1 LS TTL Load 5 Channel Select Latch (to Analog (Input Section, Pin 32) 1 Latch Transparent * 0 Latched * 4 LS TTL Loads * Sample-Hold Command (to Analog Input Section Pin 13 Normally 0 Sample Mode * Connected to ADC Status, 1 Hold Mode * Pin 20) 2 LS TTL Loads * * Short Cycle (to ADC Section Pin 14) Single-Ended/Differential Mode Select (to Analog Input Section, Pin 1) Connect to +5 V for 12-Bits Resolution Connect to Output Bit n + 1 for n Bits Resolution 1 TTL Load 0 Single Ended Mode 1 Differential Mode (+4.0 V min) 3 TTL Loads *AD363/AD364 Parameter AD363RK AD363RS DIGITAL OUTPUT SIGNALS? (All Codes Positive True) Parallel Date Unipolar Code Binary 7 Bipolar Code Offset Binary/Twos Complement * Output Drive 2 TTL Loads * Serial Data (NRZ Format) Unipolar Code Binary x Bipolar Code Offset Binary * Output Drive 2 TTL Loads * Status (Status) Logic 1 (0) During Conversion = Output Drive 2 TTL Loads * Internal Clock Output Drive 2 TTL Loads * Frequency 500 kHz * INTERNAL REFERENCE VOLTAGE +10.00 V, +10 mV = Max External Current +lmA * Voltage Temperature Coefficient +20 ppm/C max * POWER REQUIREMENTS Supply Voltages/Currents +15 V, 5% @ +45 mA max (+38 mA typ) * -15 V, =5% @ 45 mA max (38 mA typ) = +5 V, 5% @ +136 mA max (+113 mA typ) bd Total Power Dissipation 2 Watts max (1.7 Watts typ) * TEMPERATURE RANGE Specification OC to +70C 55C to +125C Storage 55C to +150C 55C to +150C PACKAGE OPTIONS Analog Input Section (DH-32E) AD Section (DH-32C) AD363RKD AD363RKD AD363RSD AD363RSD NOTES With 50 0, 1% fixed resistor in place of Gain Adjust pot. *Conversion time of ADC Section. 7One TTL Load is defined as I,, = 1.6 mA max @ V,,, = 0.4 V, I, = 40 pA max @ Vy, = 2.4 V. One LS TTL Load is defined as I,, = 0.36 mA max @ Vy = 0.4 V, Ipy = 20 pA max @ Vy = 2.7 V. *Specifications same as AD363RK. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (ALL MODELS) EV. Digital SUpply acicessitisiarPiess ecageumeartvess a asa +5.5V +V, Analog Supply ... 0... eee ee ee ee eee +16V V, Analog Supply .......2. eee eee eee eee -16V Vas Signal 2h 6osGk co hs HEWES ER Be +V, Analog Supply Vang Digital asso sews o6 PS 0 to +V, Digital Supply AGND: to: DGND) csccescs ox escemtitn Le Gente ee ae +1VAD363/AD364 AD363 PIN FUNCTION DESCRIPTION ANALOG INPUT SECTION ANALOG-TO-DIGITAL CONVERTER SECTION Pin Pin Number | Function Number Function 1 Single-End/Differential Mode Select 1 Data Bit 12 (Least Significant Bit) Out 0: Single-Ended Mode 2 Data Bit 11 Out 1: Differential Mode (+4.0 V min) 3 Data Bit 10 Out 2 Digital Ground 4 Data Bit 9 Out 3 Positive Digital Power Supply, +5 V 5 Data Bit 8 Out 4 High Analog Input, Channel 7 6 Data Bit 7 Out 5 High Analog Input, Channel 6 f Data Bit 6 Out 6 High Analog Input, Channel 5 8 Data Bit 5 Out 7 High Analog Input, Channel 4 9 Data Bit 4 Out 8 High Analog Input, Channel 3 10 Data Bit 3 Out 9 High Analog Input, Channel 2 11 Data Bit 2 Out 10 High Analog Input, Channel 1 12 Data Bit 1 (Most Significant Bit) Out 11 High Analog Input, Channel 0 13 Data Bit 1 (MSB) Out 12 No Connect 14 Short Cycle Control 13 Sample-Hold Command Connect to +5 V for 12 Bits 0: Sample Mode Connect to Bit (n + 1) Out for n Bits 1: Hold Mode 15 Digital Ground Normally Connected to ADC Pin 20 16 Positive Digital Power Supply, +5 V 14 Offset Adjust 17 Status Out 15 Offset Adjust 0: Conversion in Progress 16 Analog Output (Parallel Data Not Valid) Normally Connected to ADC 1: Conversion Complete Analog In (Parallel Data Valid) 17 Analog Ground 18 +10 V Reference Out 18 High (Low) Analog Input, Channel 15 (7) 19 Clock Out (Runs During Conversion) 19 High (Low) Analog Input, Channel 14 (6) 20 Status Out 20 Negative Analog Power Supply, 15 V 0: Conversion Complete 21 Positive Analog Power Supply, +15 V (Parallel Data Valid) 22 High (Low) Analog Input, Channel 13 (5) 1: Conversion in Progress 23 High (Low) Analog Input, Channel 12 (4) (Parallel Data Not Valid) 24 High (Low) Analog Input, Channel 11 (3) 21 Convert Start In 25 High (Low) Analog Input, Channel 10 (2) Reset Logic _ 26 High (Low) Analog Input, Channel 9 (1) Start Convert _ 27 High (Low) Analog Input, Channel 8 (0) 22 Comparator In 28 Input Channel Select, Address Bit AE 23 Bipolar Offset 29 Input Channel Select, Address Bit AO Open for Unipolar Inputs 30 Input Channel Select, Address Bit Al Connect to ADC Pin 22 for 31 Input Channel Select, Address Bit A2 Bipolar Inputs 32 Input Channel Select Latch 24 10 V Span R In 0: Latched 25 20 V Span R In 1: Latch Transparent 26 Analog Ground 27 Gain Adjust 28 Positive Analog Power Supply, +15 V 29 Buffer Out (for External Use) 30 Buffer In (for External Use) 31 Negative Analog Power Supply, 15 V 32 Serial Data Out Each Bit Valid on Trailing (~ V_) Edge Clock Out, ADC Pin 19SPECIFICATIONS (typical @ +25C, +15 V and +5 V unless otherwise noted) AD363/AD364 Parameter AD364RJ AD364RK AD364RS AD364RT Units ANALOG INPUTS Number of Inputs 16 Single-Ended or 8 Differential (Electronically Selectable) Input Voltage Range Togs to Tiss +10 * * - Vv Input (Bias) Current per Channel +50 * * * nA Input Impedance ON Channel 101100 * = QO||pF OFF Channel 10/10 * * * OllpF Input Fault Current 20 * * * mA max (Power ON or OFF) (Internally Common-Mode Rejection Limited) Differential Mode 1 kHz 20 V p-p 70 min (80 typ) * r * dB Mux Crosstalk (Any OFF CHANNEL to Any ON Channel) 1 kHz 20 V p-p 80 max (90 typ) = * * dB Offset, Channel to Channel Bap) ie z * mV max ACCURACY Gain Error! 0.3 * * * % of FSR Unipolar Offset Error* +10 +8 * xe mV Bipolar Offset Error +50 +20 * xk mV Linearity Error 0.024 0.012 =e % of FSR max T.. 10. Te 0.024 0.012 * * % of FSR max Differential Linearity Error 0.024 0.012 * ae % of FSR max Teg to Tes 0.024 0.012 * * % of FSR max Noise Error 1 mV p-p 0.1 Hz to 1 MHz * * = TEMPERATURE COEFFICIENTS Gain 54 31 = ied ppm/C Offset (+10 V Range) 12 7 * ** ppm/C Operating Temperature Range 0C to +70C * 55C to +125C | *** ppm/C SIGNAL DYNAMICS Conversion Time 32 max (25 typ) m * ps Throughput Rate, Full Accuracy 20 min (25 typ) * * kHz Sample-Hold Aperture Delay 200 max (150 typ) = * ns Aperture Uncertainty 500 max (100 typ) 7 7 ps Acquisition Time To 0.01% of Final Value For Full-Scale Step 18 max (10 typ) * * ps Feedthrough at 1 kHz 70 max (80 typ) * * dB Droop Rate 2 max (1 typ) * 7 mV/ms DIGITAL INPUT SIGNALS Analog Input Section Input Channel Select 4 Bit Binary Address * * * 1 LS TTL Load x * * Channel Select Latch 1 Latch Transparent * - i 0 Latched *~ * * 4 LS TTL Loads * 7 * Single-Ended/Differential 0 Single Ended x = Mode Select 1 Differential (+4 V min) is * * 3 TTL Loads * * ri Sample-and-Hold Command 0 Sample Mode x * * 1 Hold Mode * * * 1 TTL Load * * x ADC Section? 4.5=V,=5.5 Logic Input Threshold Tse to Tinax Logic 1 2.0 * V min Logic 0 0.8 = V max Logic Input Current Twin 10 Tinax Logic 1 20 pA max Logic 0 20 pA maxAD363/AD364 Parameter AD364RJ AD364RK AD364RS AD364RT Units DIGITAL OUTPUT SIGNALS Logic Outputs T,yi, tO Trax Sink Current Voyr = 0.4 V 1.6 = * * mA min Source Current Vour = 2-4 V 0.5 = " * mA min Output Leakage When in Three State +40 * * = uA max Output Coding Unipolar Positive True Binary * * * Bipolar Positive True Offset Binary * * * POWER REQUIREMENTS Supply Voltages/Currents +15 V, 5% @ 36 mA max * * 15 V, +5% @ 65 mA max 7 * +5 V, +5% @ 75 mA max * PACKAGE OPTIONS Analog Input Section (DH-32E) AD364RJD AD364RKD AD364RSD AD364RTD ADC Section (D-28) AD364RJD AD364RKD AD364RSD AD364RTD NOTES 1With 50 Q resistor from REF IN to REF OUT. Adjustable to zero. Adjustable to zero. 312/8 line must be hard wired to Vy ocic or digital common. *Specifications same as AD364RJ. **Specifications same as AD364RK *** Specifications same as AD364RS. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (ALL MODELS) +V, Digital-Supply: canner ea was age pennnan +5.5V #+V, Analog SUDDIV y.hicrneis cumin ameters een ae +16 V =V, Analog Supply i.e cc ses sects ack esiedeledane eo8 ane -16V Viriscoietial, 3155) 0.24 be comet se eerie tele +V, Analog Supply Vins Dipital--.5) 3s sacs Hs Fa Se 0 to +V, Digital Supply AGND to. PGND we i caraway ae eee: +1VAD364 PIN FUNCTION DESCRIPTION ANALOG INPUT SECTION ANALOG-TO-DIGITAL CONVERTER SECTION Pin Pin Number | Function Number | Function 1 Single-End/Differential Mode Select 1 Logic Power Supply, +5 V 0 Single-Ended Mode 2 Data Mode Select (12/8) 1 Differential Mode 0: 8 Upper Bits or 2 Digital Common 4 Lower Bits as Selected by Byte 3 Positive Digital Power Supply, +5 V Select (Ao)) 4 High Analog Input, Channel 7 3 Chip Select (CS) 5 High Analog Input, Channel 6 0: Device Selected 6 High Analog Input, Channel 5 1: Device Inhibited 7 High Analog Input, Channel 4 4 Byte Address/Short Cycle (Ag) 8 High Analog Input, Channel 3 0: Upper 8 Bits Enabled (12/8 0)/ 9 High Analog Input, Channel 2 12-Bit Cycle 10 High Analog Input, Channel 1 1: Lower 4 Bits Enabled (12/8 1)/ ll High Analog Input, Channel 0 8-Bit Cycle 12 No Connect 5 Read Convert (R/C) 13 Sample-Hold Command 0: Convert Start 0: Sample Mode 1: Read Enable 1: Hold Mode 6 Chip Enable (CE) _ Normally Connected to ADC Pin 28 _ : RC 0, CS 0 Initiates Conversion 14 Offset Adjust SF -RC 1. CS 0 Initiates Read 15 Offset Adjust 0: Device Disabled 16 Analog Output 1: Device Enabled Normally Connected to ADC id Analog Power Supply, +15 V (Vec) Analog In 8 Reference Out, +10 V 17 Analog Common 9 Analog Common (AC) 18 High (Low) Analog Input, Channel 15 (7) 10 Reference In 19 High (Low) Analog Input, Channel 14 (6) 1l Analog Power Supply, 15 V (Veg) 20 Negative Analog Power Supply, 15 V 12 Bipolar Offset 21 Positive Analog Power Supply, +15 V 13 10 V Span Input 22 High (Low) Analog Input, Channel 13 (5) 14 20 V Span Input 23 High (Low) Analog Input, Channel 12 (4) 15 Digital Common (DC) 24 High (Low) Analog Input, Channel 11 (3) 16 Data Bit 0 25 High (Low) Analog Input, Channel 10 (2) 17 Data Bit 1 26 High (Low) Analog Input, Channel 9 (1) 18 Data Bit 2 27 High (Low) Analog Input, Channel 8 (0) 19 Data Bit 3 28 Input Channel Select, Address Bit AE 20 Data Bit 4 29 Input Channel Select, Address Bit AO 21 Data Bit 5 30 Input Channel Select, Address Bit Al 22 Data Bit 6 3] Input Channel Select, Address Bit A2 23 Data Bit 7 32 Input Channel Select Latch 24 Data Bit 8 0: Latched 25 Data Bit 9. 1: Latch Transparent 26 Data Bit 10 27 Data Bit 11 28 Status OutAD363/AD364 SINGLE-ENDY DIFFERENTIAL MODE SELECT OFFSET SAMPLE. HIGH ANALOG INPUTS 6 INPUT amatoc ADJUST = HOLO OOOO DIGITAL OUTPUT =*~. COMMAND CHO CHT) 6CH? 6CHO OCHS) 6 CHS OCH CHT GROUND wh) ws] a] ashe] of tof oft sf orf sft sh 3 a4 CASE BUFFER: S.CHANNEL MULTIPLEXER DIFF AMP SINGLE: SAMPLE. + END! AND. AL HOLD wal MOOE SWITCH [1 capaciri B-CHANNEL CHANNEL SELECT on MULTIPLEXER NTROL LOGIC SS] LATCH | | } ap we 9 af at mj oz oz af 26h at zal za} xf nt 2 *15 CHIZ: CHIZ CHIT CHIO CHa | CME AE Ae Ay Aa r . INPUT CHANNEL CHANNEL SELECT SELECT LATCH ANALOG CHIS CHI -15V GROUND ] LOW" ANALOG INPUTS AIS Functional Block Diagram DESIGN Concept Figures 1 and 2 show a general DAS application using the AD363 and AD364, respectively. By dividing the data acquisition task into two sections, several important advantages are realized. Performance of each design is optimized for its specific function. Production yields are in- creased thus decreasing costs. Furthermore, the standard config- uration packages plug into standard sockets and are easier to handle than larger packages with higher pin counts. DC POWER (#15V, #5V) ro [4] AD363 AD363 SUCCESSIVE _ , Te] betaine ANALOG-To-niarraL APPROXIMATION] | 6 er SECTION hw) converTeR REGISTER =e M58 = TS] mux ing 4 MSB (B1) Ef fe ore =A Zuae Zz er+e AMP: Le 83 9 MODE + L 8 ete SWITCH Lf Bs z [ Te [ta 5 z ee] LO SiH |} pe ng | MUX AMP [87 Le TE L td SE a Neeo Le B10 LATCHES at awn jm LSB (B12) CONTROL LoGic sts t T AE AZATAQ) CHANNEL SINGLE-ENDY INPUT | SELECT OIFFERENTIAL CONVERT START CHANNEL LATCH MODE SELECT SELECT Figure 1. AD363 DAS Dc POWER (415, +5) of sts P4 AD364 AD364 r J ANALOG INET ANALOG-TO-DIGITAL : 4 SECTION Hota [WV] converter 5 q ore SAP | aNaLos 088-0811 2-74 AMP ouT are Ah 2 a q a DB4-DB7 zg: J ANALOG Bd i 154 DBO-DB3 LATCHES CONTROL AND | Losic 5 128 TS ap RE cE AE AZ A1 AO) CHANNEL SINGLE-END | pur | SELECT DIFFERENTIAL L CHANNEL LATCH MODE SELECT SELECT Figure 2. AD364 DAS 100 VLiO TWLIDIG System Timing Figure 3 is a general timing diagram for the circuits shown in Figures 1 and 2 operating at the maximum conversion rate. ADDRESS MAY BE CHANGED ADDRESS OM | T ee ins MIN _ 20ns MIN = MIN CONY COMMAND (ADC) m= 5/H ACQUISITION ADDRESS LATCH KX) x STATE DOESN'T MATTER CONVERT COMMAND STATUS (SAMPLE-HOLD) s H $ [H MAX CONV SAMPLE-HOLD - TIME (ADC) + ACQUISITION GATED CLOCK - Lf UY fu | j fl iz Figure 3. AD363 Timing Diagram The normal sequence of events is as follows: 1. The appropriate Channel Select Address is latched into the address register. Time is allowed for the multiplexers to settle. 2. A Convert Start command is issued to the ADC which, in response, indicates that it is busy by placing a Logic 1 on its Status line. 3. The ADC Status controls the sample-and-hold. When the ADC is busy, the sample-and-hold is the Hold mode. 4. The ADC goes into its conversion routine. Since the sample- and-hold is holding the proper analog value, the address may be updated during conversion. Thus multiplexer settling time can coincide with conversion and need not affect throughput rate. 5. The ADC indicates completion of its conversion by returning Status to Logic 0. The sample-and-hold returns to the Sample mode. 6. If the input signal has changed full scale (different channels may be widely varying data) the sample-and-hold will typi- cally require 10 microseconds toacquire the next input to sufficient accuracy for 12-bit conversion. After allowing a suitable interval for sample-and-hold to stabilize at its new value, another Convert Start command may be issued to the ADC. AD363-ADC OPERATION Figure 4 shows a detailed timing diagram for the AD363-ADC. Serial data changes on rising edges of the internal clock and is guaranteed to be stable on falling edges. AD364-ADC OPERATION There are two sets of control pins on the AD364-ADC: the gen- eral control inputs (CE, CS, and R/C) and the internal register controls inputs (12/8 and Ag). The general control pins function similarly to those on most A/D converters, performing device timing, addressing, cycle initiation, and read enable functions. The internal register control inputs, which are not found on most A/D converters, select output data format and conversion cycle length.=| 200n8, min START 25, mex i fl. 10013 4 re GATED CLOCK %& 4 & t t te te ty te to tio try tie t STATUS __ | conversion IN el INDETERMINATE PARALLEL DATA VALID BIT1 (MSB) BIT 2 SLI BIT 3 SS] i as [ SY BIT 4 BITS WN | ; BIT 6 SS LJ BIT s WS |_| BIT9 DS BIT 10 WS BIT 11 SS | | | BIT 12 + (LSB) SS LJ sentat 21 jo | 0 Jo] 25 [os | or [oe Toe Lovo} orf a2 AL Figure 4. AD363-ADC Timing Diagram (Binary Code 110101011001) The two major control functions, convert start and read enable, are controlled by CE, CS, and R/C. Although all three inputs must be in the correct state to perform the function (for convert start, CE = 1, CS = 0, R/C = 0; for read enable, CE = 1, CS = 0, R/C = 1), the sequence does not matter. For large sys- tems, typically microprocessor controlled, standard operation for convert start would be to first set R/C = 0 (from R/W line); ad- dress the chip with CS = 0, then apply a positive start pulse to CE. A read would be done similarly but with R/C = 1. Ag (byte select) and 12/8 (data format) inputs work together to control the output data and conversion cycle. In almost all situa- tions 12/8 is hard-wired high (to Vy ogic) or low (to Digital Common). If it is wired high, all 12 data lines will be enabled when the read function is called by the general control inputs. For an 8-bit bus interface, 12/8 will be wired low. In this mode, only the 8 upper bits or the 4 lower bits can be enabled at once, as addressed by Ag. For these applications, the 4 LSBs (Pins 16-19) should be hard-wired to the 4 MSB (Pins 24-27). Thus, during a read, when Ag is low, the upper 8 bits are enabled and present data on Pins 20 through 27. When Ag goes high, the upper 8 data bits are disabled, the 4 LSBs then present data to Pins 24 to 27, and the 4 middle bits are overridden so that zeros are presented to Pins 20 through 23. The Ag input performs an additional function of controlling conversion length. If Aj is held low prior to cycle initiation, a full 12-bit, 25 zs cycle will result; if Ag is held high prior to cycle initiation, a shortened 8-bit, 16 ws cycle will result. The Ao line must be set prior to cycle initiation and held in the de- sired position at least until STS goes high. Thus, for micro- processor interface applications, the Ag line must be properly controlled during both the convert start and read functions. STANDARD FULL CONTROL INTERFACE The timing for the standard full control interface is shown in Figure 5. In this operating mode, CS is used as the address in- put which selects the particular device, R/C selects between the read data and start conversion functions, and CE is used to time the actual functions. TIMING FOR FULL CONTROL APPLICATIONS CONVERT START TUMING READ TIMING Fe _ ie fF eee ee Ty ne Se eee ES fF Fea a fas % ~ = = | HIGH Sata} a 81.617 + et 2 aPEDANCE ee) - - op o Figure 5. AD364-ADC Timing Diagram The left side of the figure shows the conversion start control. CS and R/C are brought low (their sequence does not matter), then the start pulse is applied to CE. The timing diagram shows a time delay for CS and R/C prior to the start pulse at CE. If less time than this is allowed, the conversion will still be started, but an appropriately longer pulse will be needed at CE. However, if the hold times for CS and R/C after the rising edge of the start pulse at CE are not followed, the conversion may not be initiated. The Ag line determines the conversion cycle length and must be selected prior to conversion initiation. If Ag is low, a 12-bit cy- cle results; if Ap is high, an 8-bit short cycle results. Minimum setup and hold times are shown. The status line goes high to indicate conversion in progress. The analog input signal is al- lowed to vary until the STS goes high. It must then be held steady until STS again goes low at the end of conversion. The data read function operates in a similar fashion except that R/C is now held high. The data is stored in the output register and can be recalled at will until a new conversion cycle is com- manded. In addition, if the converter is arranged in the 8-bit data mode, the Aj line now functions as the byte select address, with setup and hold times as shown. With Aj low, Pins 20 to 27 (DB4-11) come out of three-state and present data. With Ag high, Pins 16-19 (DB0-3) come out of three-state with data and Pins 20-23 present active trailing zeros. In the 8-bit mode, Pins 16-19 will be hard-wired directly to Pin 2427 for direct two byte loading onto an 8-bit bus. There are two delay times for the data lines after CE is brought low: tp is the delay until the outputs are fully into the high impedance state. STANDALONE OPERATION For simpler control functions, the AD364-ADC can be con- trolled with just R/C. In this case, CE is wired high, CS low, 12/8 high, and Ag low. There are two ways of cycling the deviceAD363/AD364 TIMING SPECIFICATIONSFULL CONTROL MODE tpsc | 400 ns max tpp | 200 ns max ture | 300 ns min typ | 25 ns min tssc | 300 ns min tssp | 150 ns min tysc | 200 ns min tsrrn | 0 min tsrc | 250 ns min tear | 150 ns min turc | 200 ns min tusr | 50 ns min tsac | 0 min turer | 0 min trac | 300 ns min tyar | 50 ns min tc 15-35 ys (12-Bit) | tyyy, 150 ns max 10-24 ws (8-Bit) | tea; | 20 ns min tsua | 10-18 ps tsa 0 min with this simple hookup. If a negative pulse is used to initiate conversion as in Figure 6, the converter will automatically bring the 12 data lines out of three-state at the end of conversion. The data will remain valid on the output lines until another pulse is applied. If the conversion is initiated by a high pulse as shown in Figure 7, the data lines are held in three-state at the end of conversion until R/C is brought high. The next conversion cycle is initiated when R/C goes low; the data from the previous cycle will remain valid for the time ty;pp- An alternative to the above is to toggle R/C as needed to initiate a new cycle on read data. Data will appear when R/C is brought high, a new cycle is initiated when RIC goes low. TIMING FOR STAND -ALONE OPERATIONS SHORT LOW PULSE: OUTPUTS COME ON AFTER CONVERSION tur BS STS B1-12 Figure 6. SHORT HIGH PULSE: OUTPUTS SYNCHRONIZED TO RISING EDGE RIC sTs B1-12 IMPEDANCE Figure 7. TIMING SPECIFICATIONSFULL CONTROL MODE tir 250 ns min tps 600 ns max tpr 25 ns max tis 300 ns min 1000 ns max tires 300 ns min topper 250 ns max APPLICATIONS Single-Ended/Differential Mode Control The AIS features an internal analog switch that configures the Analog Input Section in either a 16-channel single-ended or 8-channel differential mode. This switch is controlled by a non- TTL logic input applied to Pin 1 of the Analog Input Section: 0: Single-Ended (16 Channels) 1: Differential (8 Channels) (+4.0 V min) When in the differential mode, a differential source may be ap- plied between corresponding High and Low analog input channels. It is possible to mix SE and DIFF inputs by using the mode control to command the appropriate mode. In this case, four microseconds must be allowed for the output of the Analog In- put Section to settle to within +0.01% of its final value, but if the mode is switched concurrent with changing the channel ad- dress, no significant additional delay is introduced. The effect of this delay may be eliminated by changing modes while a conver- sion is in progress (with the sample-and-hold in the Hold mode). When SE and DIFF signals are being processed concur- rently, the DIFF signals must be applied between corresponding High and Low analog input channels. Another application of this feature is the capability of measuring 16 sources individu- ally and/or measuring differences between pairs of those sources. Input Channel Addressing Table I is the truth table for input channel addressing in both the single-ended and differential modes. The 16-single-ended channels may be addressed by applying the corresponding digi- tal number to the four Input Channel Select address bits, AE, AO, Al, A2 (Pins 28-31). In the differential mode, the eight channels are addressed by applying the appropriate digital code to AO, Al, and A2; AE must be enabled with a Logic 1. In- ternal logic monitors the status of the SE/DIFF Mode input and addresses the multiplexers singularly or in pairs as required. ADDRESS ON CHANNEL (Pin Number) Differential AE A2 Al_ AO0/| Single-Ended Hi Lo 0 0 0 0 0 (1) None 0 0 0 1 1 (10) None 0 0 1 0 2 (9 None 0 0 ] 1 3 (8) None 0 1 0 0 4 (7) None 0 1 0 1 5 (6) None 0 1 1 0 6 (5) None 0 1 1 1 7 (4 None 1 0 0 0 8 (27) 01) 0(27) 1 0 0 1 9 (26) 1(10) 1(26) 1 0 l 0 10 (25) 2 (9) 2 (25) 1 0 1 1 ll (24 3 (8 3(24) 1 1 0 0 12 (23) 4 (7) 5 (23) l l 0 1 13 (22) 5 (6) 522) l 1 1 0 14 (19) 6 (5) 6(19) lc-1 1 41 15 (18) 7 (4) 7(18) Table |. Input Channel Addressing Truth Table qjWhen the channel address is changed, six microseconds must be allowed for the Analog Input Section to settle to within +0.01% of its final output (including settling times of all elements in the signal path). The effect of this delay may be eliminated by per- forming the address change while a conversion is in progress (with the sample-and-hold in the hold mode). All unused in- puts must be grounded. Input Channel Address Latch The AIS is equipped with a latch for the Input Channel Select address bits. If the Latch Control pin (Pin 32) is at Logic 1, input channel select address information is passed through to the multiplexers. A Logic 0 freezes the input channel address present at the inputs at the 1-to-0 transition level-triggered. This feature is useful when input channel address information is provided from an address, data or control bus that may be re- quired to service many devices. The ability to latch an address is helpful whenever the user has no control of when address infor- mation may change. Sample-and-Hold Mode Control The Sample-and-Hold Mode Control input (Pin 13) is normally connected to the Status output (Pin 20) from an analog-to-digital converter. When a conversion is initiated by applying a Convert Start command to the ADC, Status goes to Logic 1, putting the sample-and-hold in to the Hold mode. This freezes the information to be digitized for the period of conversion. When the conversion is complete, Status returns to Logic 0 and the sample-and-hold returns to the Sample mode. Eighteen microseconds must be allowed for the sample-and-hold to ac- auire (catch up to) the analog input to within +0.01% of the final value before a new Convert Start command is issued. The purpose of a sample-and-hold is to stop fast changing input signals long enough to be converted. In this application, it also allows the user to change channels and/or SE/DIFF mode while a conversion is in progress thus eliminating the effects of multiplexer, analog switch and differential amplifier settling times. If maximum throughput rate is required for slowly changing signals, the Sample-and-Hold Mode Control may be wired to ground (Logic 0) rather than to ADC Status thus leaving the sample-and-hold in a continuous sample mode. Analog Input Section Offset Adjust Circuit Although the offset voltage of the AIS may be adjusted, that adjustment is normally performed at the ADC. In some special applications, however, it may be helpful to adjust the offset of the Analog Input Section. An example of such a case would be if the input signals were small (<10 mV) relative to the AIS voltage offset and if a gain stage was to be inserted between the AIS and the ADC. To adjust the offset of the AIS, the circuit shown in Figure 8 is recommended. ANALOG INPUT SECTION output SAMPLE < Laan [14/]21 7 100k2 OFFSET VOLTAGE ADJUST TO V+ ANALOG (+15V) Figure 8. AIS Offset Voltage Adjustment Under normal conditions, all calibration is performed at the ADC Section. Gain Adjust, AD363-ADC: Gain may be adjusted by connect- ing a 100 potentiometer between +10 V Reference Output and Gain Adjust Input (ADC Pins 18 and 27). A multi-turn, low temperature coefficient potentiometer, such as a 20-turn cermet device, is recommended. This potentiometer may be re- placed with a 50 , 0.1% resistor to obtain an absolute gain cali- bration of 0.05% without trimming. Offset Adjust, AD363-ADC: The simplest offset adjust circuit requires a 20-turn, 20 kO cermet potentiometer and a 3.9 MQ. resistor as shown in Figure 9a. This arrangement has an adjust- ment range of +8 LSBs, and will contribute a maximum of 2.3 ppm/C offset drift with a carbon composition fixed resistor (TC = 1200 ppm/*C). Drift contributions from the offset ad- just circuit can be reduced well below this level using metal-film resistors and the circuit of Figure 9b. Gain Adjust, AD364-ADC: Gain may be adjusted by connect- ing a 100 2 potentiometer between the Reference Output and Reference Input (ADC Pins 8 and 10). A multi-turn, low tem- perature coefficient potentiometer, such as a 20T cermet device, is recommended. A fixed 50 , 1% resistor should be connected between Pins 8 and 10 if no gain trim is required. +15V 3.9M 20k AD363-ADC 20T -15V Figure 9a. +15V 2 . Fe PF 20k OOkM.F. 200k M. F. AD363-AD 20T READE -15V Figure 9b. Offset Adjust, AD364-ADC: Offset adjust circuits for unipolar and bipolar operation are shown in Figures 10a and 10b. In each case the potentiometer should be a multi-turn, low temperature coefficient device, such as 20-turn cermet. Lowest offset drift in unipolar operation will be realized when the fixed resistors are low-TC (100 ppm/C) metal-film types. =11=AD363/AD364 If no offset adjustment is desired, Pin 12 should be connected to Pin 9 (unipolar mode) or to Pin 8 through a 50 2 1% resistor (bipolar mode). OFFSET R1 100k -15V 0 MIDDLE AD364-ADC i (10) REF IN R2 100k MIDDLE BITS 10022 ann ved OFFSETS 10042 Figure 10b. Bipolar Gain & Offset Input Scaling: Connections for the various ADC input ranges are given in Tables II and III. Buffer: An uncommitted unity-gain buffer is available in the AD363-ADC. This buffer has a 2 1s settling time to 0.01% for a 20 V step. Its input should be grounded if the buffer is not used. Connect Connect Analog Connect Bipolar Range Input To Pin: | Span Pin: | Pin 23 To: Oto +5 V 24 25 to 22 0to+10V 24 2.5 V to +2.5 V | 24 25 to 22 -5Vt+5V 24 22 -10V to +10 V 25 Table Il. AD364-ADC Pin Connections Connect Analog Connect Range Input To Pin: | Pin 12 To: 0to +10 V 13 GND* -5Vtwo+5V 13 Pin 8** -10Vto +10 V 14 Pin 8** *Refer to Figure 10a for gain and offset adjustments. **Refer to Figure 10b for gain and offset adjustments. Table [ll. AD364-ADC Pin Connections Other Considerations Grounding: Analog and digital signal grounds should be kept separate where possible to prevent digital signals from flowing in the analog ground circuit and inducing spurious analog signal noise. Analog Ground (Pin 17) and Digital Ground (Pin 2) are not connected internally; these pins must be connected exter- nally for the system to operate properly. Preferably, this connec- tion is made at only one point, as close to the AIS, as possible. The case is connected internally to Digital Ground to provide good electrostatic shielding. If the grounds are not tied common on the same card with the AIS they should be connected with back-to-back general purpose diodes as shown in Figure 11. This will protect the AIS from possible damage caused by volt- ages in excess of +1 volt between the ground systems which could occur if the key grounding card should be removed from the overall system. The device will operate properly with as much as +200 mV between grounds, however this difference will be reflected directly as an input offset voltage. AIS ADC DGND AGND DGND AGND TO CARD IN914 OR CONNECTOR EQUIVALENT Figure 11. Ground-Fault Protection Diodes Power Supply Bypassing: The +15 V and +5 V power leads should be capacitively bypassed to Analog Ground and Digital Ground respectively for optimum device performance. 1 jF tan- talum types are recommended; these capacitors should be lo- cated close to the system. It is not necessary to shunt these capacitors with disc capacitors to provide additional high fre- quency power supply decoupling since each power lead is by- passed internally with a 0.039 wF ceramic capacitor. ={9AD363/AD364 ORDERING GUIDE Temperature Model Range Package Option AD363RKD | 0C to +70C DH-32E (Analog Input Section) DH-32C (ADC Section) AD363RSD | 55C to +125C | DH-32E (Analog Input Section) DH-32C (ADC Section) AD364RJD | 0C to +70C DH-32E (Analog Input Section) D-28 (ADC Section) AD364RKD | 0C to +70C DH-32E (Analog Input Section) D-28 (ADC Section) AD364RSD | 55C to +125C | DH-32E (Analog Input Section) D-28 (ADC Section) AD364RTD | 55C to +125C | DH-32E (Analog Input Section) D-28 (ADC Section) D-28 Package 4 |+- 0.005 (0.13) MIN nee >| [ 0 Oo 28 15 1 14 a 0.610 (15.49) 0.580 (14.73) }+_ 1.490 (37.85) MAX oe 0.060 (1.52) /} 0.015 (0.38) 0.232MAX J r es MAN) 0.150 (3.81) | 0.075 (0.38) Lg 0.200(5.08) | MIN 0.008 (0.20) 0.125 (3.18) __ vy lhe A k 0.065 (1.65) peso eee 0.023 (0.58) a 100 a 54) 0.036 (0.96) ; : 0.074 (0.36) DH-32C Package >| [+ 9.008 0.19) man Soo ooo oo 0.098 (2.49) MAX +| r 32 17 1 16 ee ee pe_ 1.620 (41.14) MAX _ 0.280 (7.11) MAX y 0.180 (4.57) 0.150 (3.81) _ 1 lh | 0.020 (0.51) 0.100 (2.54) 0.055 (1.40) 0.016 (0.41) 0.035 (0.89) 0.910 (23.11) 0.870 (22.10) > eS 0.012 (0.31) 0.009 (0.23)* | 0.930 (23.62) 0.890 (22.61) (22.61) DH-32E Package 32 17 0.060 (1.52) 0.225 (5.72) M a 1.750 (44.31) MAX 0.025 (0.63) 0.075 (7.02) 0.075 (0.38) F 0.230 (5.84) y e 0-190 (4.83) 0.160 (4.06) A tt 0.185 (4.89) f 0.120 (3.05) | ne ee | ll >| >| 10.120 (3.05) MAX 0.005 (0.13) MIN 0.023 (0.58) 0.100 (2.54) 0.070 (1.78) 0.014 (0.36) 0.030 (0.76) 1,105 1.105 (28.07) 07) [*___ tors e7an "| 0,015 (0.38) 0.008 (0.20) 0.910 (23.10) *~ 0.890 (22.61)aaaAD363/AD364 ~15-L6/Z-E-68P LD W'Ss'N NI G3LNIYd ~16=