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LTC1923

1923f

High Efficiency Thermoelectric

Cooler Controller

■

High Efficiency, Low Noise Topology

■

Adjustable Output Slew Rate Reduces EMI

■

Full-Bridge Controller for Bidirectional

Current Control

■

Adjustable Pulse-by-Pulse Bidirectional TEC

Current Limit

■

Open/Shorted Thermistor Indication

■

Solution Footprint in Less Than 0.6" × 0.8"

(Double-Sided PCB)

■

Available in 5mm x 5mm QFN and

28-Pin SSOP Packages

■

TEC Voltage Clamping

■

TEC Current, Voltage and Heat/Cool Status Outputs

■

Adjustable/Synchronizable Oscillator Frequency

Reduces Filter Component Size and System Noise

■

2.5V Reference Voltage Output

■

2.7V Minimum Operating Voltage

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Laser-Based Fiber Optic Links

■

Medical Instruments

■

CPU Temperature Regulators

Laser Temperature Control Loop Achieving Setpoint Stability of 0.01°C

The LTC

1923 is a pulse width modulator intended for

thermoelectric cooler (TEC) or heater applications requir-

ing either unidirectional or bidirectional drive circuits. All

of the necessary control circuitry and two sets of comple-

mentary output drivers are integrated into the LTC1923 to

drive a full bridge, providing an efficient means of bidirec-

tional current flow to the TEC. An accurate temperature

control loop to stabilize the temperature of a laser diode

system is easily achieved with the addition of just a few

external components. Typical temperature setpoint accu-

racy of 0.1°C is achievable with the LTC1923. Adding an

instrumentation amplifier front end allows setpoint stabil-

ity of 0.01°C.

The part features independent adjustable heating and

cooling pulse-by-pulse current limit, current soft-start for

controlled start-up, output slew rate control to reduce

system noise, differential current sense and voltage am-

plifiers and a host of auxiliary circuits to protect the laser

and provide redundant system monitoring.

PLLLPF

SLEW

SDSYNC

CNTRL

EAOUT

AGND

LIM

SET

FAULT

THRM

H/C

TEC

REF

PDRVB

NDRVB

PGND

NDRVA

PDRVA

–

TEC

–

LTC1923

–

LTC2053

A = 10

REF

LTC1658

REF

10k

0.1%

10k

NTC V

OUT

TMP

CMD

330pF

1µF

10µF

10µH

C1, C2: TAIYO YUDEN JMK325BJ226MM-T (X7R)

L1, L2: SUMIDA CDRH6D2B-220NC

*MNA, MPA: SILICONIX Si9801

**MNB, MPB: SILICONIX Si9801

1923 TA01

4.7µF

1µF

10M

100k

10k

1µF

10µH

22µFC2

22µF

MPA*

REF

MPB**

MNA*

MNB**

TEC

COOLER

82k

APPLICATIO S

FEATURES

TYPICAL APPLICATIO

DESCRIPTIO

LTC1923

1923f

to GND................................................. –0.3V to 6V

SDSYNC, R

SLEW

......................................... –0.3V to 6V

FB, CNTRL, V

THRM

, I

LIM

, V

SET

..................... –0.3V to 6V

, CS

–

, TEC

–

.................................–0.3V to 6V

ORDER PART

NUMBER

LTC1923EGN

JMAX

= 125°C, θ

= 120°C/W

ABSOLUTE AXI U RATI GS

WWWU

PACKAGE/ORDER I FOR ATIO

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.

VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.

ELECTRICAL CHARACTERISTICS

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

PLLLPF

SLEW

SDSYNC

CNTRL

EAOUT

AGND

LIM

SET

FAULT

THRM

H/C

TEC

REF

PDRVB

NDRVB

PGND

NDRVA

PDRVA

–

TEC

–

Consult LTC Marketing for parts specified with wider operating temperature ranges.

(Note 1)

FAULT, H/C ................................................. –0.3V to 6V

Operating Temperature Range (Note 2) .. –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)..................300°C

ORDER PART

NUMBER

LTC1923EUH

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

1CNTRL

EAOUT

AGND

ILIM

VSET

PDRVB

NDRVB

VDD

PGND

NDRVA

PDRVA

CS+

SDSYNC

RSLEW

PLLLPF

VREF

FAULT

VTHRM

H/C

VTEC

TEC–

TEC+

ITEC

CS–

UH PACKAGE

32-LEAD PLASTIC QFN

PIN 1

TOP VIEW

JMAX

= 125°C, θ

= 34°C/W

EXPOSED PAD IS PGND

(MUST BE SOLDERED TO PCB)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Supply

VDD Operating Supply Voltage ●2.7 5.5 V

UVLO Undervoltage Lockout Low to High Threshold ●2.6 2.7 V

UVHYST Hysteresis High to Low ●50 130 mV

Operating Supply Current No Output Load, Outputs Not Switching 2 4 mA

DDSHDN

Shutdown I

SDSYNC = 0V 10 25 µA

SHDNTH Shutdown Threshold Measured at PDRVA, PDRVB 0.3 0.8 1.4 V

LTC1923

1923f

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.

VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference

REF

Reference Output Voltage No Load 2.462 2.5 2.538 V

●2.450 2.550 V

REFGD

REF

Good Threshold V

REF

Rising Threshold ●2.25 2.45 V

LDREG Load Regulation I

LOAD

= –1mA to –10mA 10 25 mV

LINEREG Line Regulation V

= 2.7V to 5.5V 5 20 mV

REFISC

Short-Circuit Current V

REF

= 0V 10 20 mA

Oscillator and Phase-Locked Loop

OSCI

Initial Oscillator Frequency R

= 10k, C

= 330pF 190 225 260 kHz

OSC

Frequency Variation V

= 2.7V to 5V, C

= 330pF, R

= 10k ●165 225 270 kHz

OSCPK C

Ramp Peak 1.4 1.5 1.6 V

OSCVLY C

Ramp Valley 0.4 0.5 0.6 V

TICH

Charge Current C

= 0.3V, R

= 10k –150 µA

TIDIS

Discharge Current C

= 1.8V, R

= 10k 150 µA

PLLGAIN Gain from PLLLPF to R

–1.1 –0.9 –0.7 V/V

PLLLPF

Phase Detector Output Current

Sinking f

SYNC

< f

OSC

12 µA

Sourcing f

SYNC

> f

OSC

–12 µA

MSTTH Master Threshold On PLLLPF Pin Measured at SDSYNC Pin V

– 0.7 V

– 0.4 V

SDDLY Shutdown Delay to Output 20 45 µs

Error Amplifier

Input Offset Voltage EAOUT = 1V, V

= 2.5V –18 18 mV

AOL Open-Loop Gain EAOUT = 0.45V to 1.55V, CNTRL = 2.5V 80 dB

Common Mode Input Range EAOUT = 1V 0.2 V

+ 0.2 V

FB and CNTRL Input Bias Currents FB = CNTRL = 1.25 –100 100 nA

Output High I

LOAD

= –100µA 1.65 V

Output Low I

LOAD

= 100µA 0.3 0.45 V

SOURCE

Sourcing Current EAOUT = 1V, FB = 2.4V, CNTRL = 2.5V –1.5 –0.5 mA

SINK

Sinking Current EAOUT = 1V, FB = 5V, CNTRL = 2.5V 1 2 mA

GBW Gain-Bandwidth Product f = 100kHz (Note 3) 2 MHz

Current Sense Amplifier

ACS Amplifier Gain 10 V/V

CSOFF Amplifier Offset Measured at I

TEC

–15 –2 10 mV

TECH

Output Sourcing Load Regulation CS

- CS

–

= 100mV, I

LOAD

= 0 to –50µA 0.1 0.2 V

TECL

Output Sinking Load Regulation CS

- CS

–

= 100mV, I

LOAD

= 0 to 50µA 0.1 0.2 V

f3dB –3dB Frequency (Note 3) 500 kHz

LIMTH

Current Limit Threshold Measured at CS

, CS

–

●125 145 165 mV

LIMDLY

Current Limit Delay to Output 300 450 ns

SSI

CHG

Soft-Start Charge Current SS = 0.75V –2.5 –1.5 –0.5 µA

SSI

LIM

Soft-Start Current Limit Threshold SS = 0.5V, Measured at CS

, CS

–

50 70 90 mV

LIM

Current Limit Threshold I

LIM

= 0.5V, Measured at CS

, CS

–

50 70 90 mV

LTC1923

1923f

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LTC1923E is guaranteed to meet specifications from 0°C to

70°C. Specifications over the –40°C to 85°C operating temperature range

are assured by design, characterization and correlation with statistical

process controls.

ELECTRICAL CHARACTERISTICS

Note 3: Guaranteed by design, not tested in production.

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.

VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TEC Voltage Amplifier

ATEC Amplifier Gain 0.98 1 1.02 V/V

TECOFF Amplifier Offset Measured at V

TEC

, V

= 2.5V –7 mV

TECCMR Common Mode Rejection 0.1V < V

< 4.9V 60 dB

TECH

Output High Voltage I

LOAD

= –50µA 4.7 4.9 V

TECL

Output Low Voltage I

LOAD

= 50µA 0.1 0.3 V

f3dB –3dB Frequency (Note 3) 1 MHz

Output Drivers

OUTH Output High Voltage I

OUT

= –100mA 4 4.5 V

OUTL Output Low Voltage I

OUT

= 100mA 0.7 1.2 V

RISE

Output Rise Time C

LOAD

= 1nF 20 ns

FALL

Output Fall Time C

LOAD

= 1nF 20 ns

rSLEW

Output Rise Time C

LOAD

= 1nF, R

SLEW

= 10k 20 ns

fSLEW

Output Fall Time C

LOAD

= 1nF, R

SLEW

= 10k 20 ns

rSLEW

Output Rise Time C

LOAD

= 1nF, R

SLEW

= 100k 90 ns

fSLEW

Output Slew Fall Time C

LOAD

= 1nF, R

SLEW

= 100k 90 ns

SLEWVT R

SLEW

Disable Threshold 2.75 V

DLY Output Dead Time R

= 10k 90 ns

Fault

OPENTH Open Thermistor Threshold V

SET

= 5V, Measured with Respect to V

SET

–410 mV

SHRTTH Shorted Thermistor Threshold V

SET

= 5V, Measured with Respect to GND 0.975 V

FLTV Fault Output Low Voltage 1mA Into FAULT, During Fault 150 300 mV

Direction Comparator

DIRH Low-to-High Threshold TEC

–

= 2.5V, Measured with Respect to TEC

–

50 mV

Sensed When H/C Toggles Low

DIRL High-to-Low Threshold TEC

–

= 2.5V, Measured with Respect to TEC

–

–50 mV

Sensed When H/C Toggles High

HCV H/C Output Low Voltage 1mA Into Pin 150 300 mV

LTC1923

1923f

TEMPERATURE (°C)

–50

165

OSCILLATOR FREQUENCY (kHz)

185

205

225

265

–20 10 40 70

1923 G01

100 130

245

CT = 330pF

RT = 10k

RT (kΩ)

OSCILLATOR FREQUENCY (kHz)

200

600

800

1000

1800

1923 G02

400

10 20

1200

1400

1600

CT = 68pF

CT = 150pF

CT = 330pF

VDD = 2.7V, 5V

TA = 25°C

TEMPERATURE (°C)

REF

(V)

2.495

2.500

1923 G03

2.490

2.485

2.510

2.505

–50 –20 10 40 70 100 130

TYPICAL PERFOR A CE CHARACTERISTICS

VREF vs IREF for Different

Temperatures Output Dead Time vs RT

Error Amplifier Offset Voltage

vs Temperature Open Thermistor Threshold

vs Temperature

Output Rise/Fall Time vs RSLEW

Shorted Thermistor Threshold

vs Temperature

REF

(mA)

REF

(V)

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

2.475

2.470

1923 G04

515

= 125°C

= 25°C

= –50°C

(kΩ)

DEAD TIME (ns)

125

1923 G05

100

25 7.5 10 12.5

150

= 2.7V

= 5V

= 25°C

RISE TIME (ns)

100

150

1923 G06

0100 200 300

250

200

SLEW

(kΩ)

= 25°C

TEMPERATURE (°C)

–50

–1.0

ERROR AMPLIFIER VIO (mV)

–0.5

0.5

1.0

1.5

–20 10 40 70

1923 G07

100 130

TEMPERATURE (°C)

–50

4.55

OPEN THERMISTOR THRESHOLD (V)

4.56

4.57

4.58

4.59

4.60

–20 10 40 70

1923 G08

100 130

VSET = 5V

TEMPERATURE (°C)

–50

0.95

SHORTED THERMISTOR THRESHOLD (V)

0.96

0.97

0.98

0.99

1.00

–20 10 40 70

1923 G09

100 130

VSET = 5V

Oscillator Frequency

vs Temperature Oscillator Frequency vs RTVREF vs Temperature

LTC1923

1923f

TYPICAL PERFOR A CE CHARACTERISTICS

Representative Waveforms for NDRVA,

NDRVB, TEC Current and CS+ – CS–

Representative Waveforms for

TEC Current, CS+ – CS– and ITEC

= 5V 1923 G15.tif

TEC

= 2.5Ω

= 0.1Ω

CH1: TEC CURRENT (500mA/DIV)

CH2: VOLTAGE ACROSS

0.1Ω SENSE RESISTOR

(CS

– CS

–

) 100mV/DIV

CH3: NDRVA (5V/DIV)

CH4: NDRVB (5V/DIV)

CH2: VOLTAGE ACROSS 0.1Ω SENSE

RESISTOR R

(CS

– CS

–

) 100mV/DIV

CH3: VOLTAGE ON I

TEC

PIN EQUAL TO

TEN TIMES THE ABSOLUTE VALUE OF

CH2 (200mV/DIV)

CH1: TEC CURRENT (500mA/DIV)

CH1, CH3

CH2

= 5V 1923 G16.tif

TEC

= 2.5Ω

= 0.1Ω

System Power Loss

vs TEC Current TEC Clamp Voltage

vs Temperature

Current Limit Threshold

vs Temperature

TEMPERATURE (°C)

–50

CURRENT LIMIT THRESHOLD (mV)

130

1923 G10

–20 40

10 70 100

165

160

155

150

145

140

135

130

125

TEC CURRENT (A)

0.4

0.5

0.7

1923 G11

0.3

0.2

0.5 1

0.1

0.6

POWER LOSS (W)

= 5V

= 3.3V

= 25°C

TEMPERATURE (°C)

–50

TEC CLAMP VOLTAGE (V)

130

1923 G12

–20 40

10 70 100

2.550

2.530

2.510

2.490

2.470

2.450

LTC1923

1923f

Identical Test Conditions as Above, Except in Heating Mode. TEC’s Higher Heating Mode Efficiency

Results in Higher Thermal Gain. 0.002°C Peak-to-Peak Variation Is 4x Stability Improvement.

Baseline Tilt, Just Detectable, Shows Similar 4x Improvement vs Above

Long-Term Cooling Mode Stability Measured in Environment that Steps 20 Degrees Above Ambient

Every Hour. Data Shows Resulting 0.008°C Peak-to-Peak Variation, Indicating Thermal Gain of

2500. 0.0025°C Baseline Tilt Over Plot Length Derives From Varying Ambient Temperature

1923 G13.tif

1923 G14.tif

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1923

1923f

PI FU CTIO S

PLLLPF (Pin 1/Pin 30): This pin serves as the lowpass

filter for the phase-locked loop when the part is being

synchronized. The average voltage on this pin equally

alters both the oscillator charge and discharge currents,

thereby changing the frequency of operation. Bringing the

voltage on this pin above V

– 0.4V signifies that the part

will be used as the synchronization master. This allows

multiple devices on the same board to be operated at the

same frequency. The SDSYNC pin will be pulled low during

each C

charging cycle to facilitate synchronization.

SLEW

(Pin 2/Pin 31): Placing a resistor from this pin to

AGND sets the voltage slew rate of the output driver pins.

The minimum resistor value is 10k and the maximum

value is 300k. Slew rate limiting can be disabled by tying

this pin to V

, allowing the outputs to transition at their

maximum rate.

SDSYNC (Pin 3/Pin 32): This pin can be used to disable the

IC, synchronize the internal oscillator or be the master to

synchronize other devices. Grounding this pin will disable

all internal circuitry and cause NDRVA and NDRVB to be

forced low and PDRVA and PDRVB to be forced to V

EAOUT will be forced low. FAULT will also be asserted low

indicating a fault condition. The pin can be pulled low for

up to 20µs without triggering the shutdown circuitry. The

part can either be slaved to an external clock or can be used

as the master (see Applications Information for a more

detailed explanantion).

CNTRL (Pin 4/Pin 1): Noninverting Input to the Error

Amplifier.

EAOUT (Pin 5/Pin 2): Output of the Error Amplifier. The

loop compensation network is connected between this pin

and FB. The voltage on this pin is the input to the PWM

comparator and commands anywhere between 0% and

100% duty cycle to control the temperature of the tem-

perature sense element.

FB (Pin 6/Pin 3): The Inverting Input to the Error Amplifier.

This input is connected to EAOUT through a compensating

feedback network.

AGND (Pin 7/Pin 4): Signal Ground. All voltages are

measured with respect to AGND. Bypass V

and V

REF

with low ESR capacitors to the ground plane near this pin.

SS (Pin 8/Pin 6): The TEC current can be soft-started by

adding a capacitor from this pin to ground. This capacitor

will be charged by a 1.5µA current source. This pin connects

to one of the inverting inputs of the current limit compara-

tor and allows the TEC current to be linearly ramped up from

zero. The voltage on this pin must be greater than 1.5V to

allow the open/shorted thermistor window comparitor to

signal a fault.

LIM

(Pin 9/Pin 7): A voltage divider from V

REF

to this pin

sets the current limit threshold for the TEC. If the voltage

on this pin is set higher than 1V, then I

LIMIT

= 150mV/R

as that is the internal current limit comparator level. If the

voltage on this pin is set less than 1V, the current limit

value where the comparator trips is:

LIMIT

= [0.15 • R

ILIM1

• V

REF

]/[(R

ILIM1

+ R

ILIM2

) • R

]

SET

(Pin 10/Pin 8): This is the input for the setpoint

reference of the temperature sense element divider net-

work or bridge. This pin must be connected to the bias

source for the thermistor divider network.

FAULT (Pin 11/Pin 9): Open-drain output that indicates by

pulling low when the voltage on V

THRM

is outside the

specified window, the part is in shutdown, undervoltage

lockout (UVLO), or the reference is not good. When the

voltage on V

THRM

is outside the specified window, it

signifies that the thermistor impedance is out of its accept-

able range. This signal can be used to flag a microcontroller

to shut the system down or used to disconnect power from

the bridge. See Applications Information for using this

signal for redundant protection.

THRM

(Pin 12/Pin 10): Voltage Across the Thermistor. If

the voltage on this pin is outside the range between 410mV

below V

SET

and 0.2 • V

SET

, the FAULT pin will be asserted

(and latched) low indicating that the thermistor tempera-

ture has moved outside the acceptable range.

H/C (Pin 13/Pin 11): This open-drain output provides the

direction information of the TEC current flow. If TEC

greater than TEC

–

, which typically corresponds to the

system cooling, this output will be a logic low. If the

opposite is the case, this pin will pull to a logic high.

(GN Package/UH Package)

LTC1923

1923f

PI FU CTIO S

NDRVA, NDRVB (Pins 21, 24/Pins 19, 23): These push-

pull outputs are configured to drive the opposite low side

switches in a full-bridge arrangement.

PGND (Pin 22/Pin 20): This is the high current ground for

the IC. The external current sense resistor should be

referenced to this point.

(Pin 23/Pins 21, 22): Positive Supply Rail for the IC.

Bypass this pin to PGND and AGND with >10µF low ESL,

ESR ceramic capacitors. The turn on voltage level for V

is 2.6V with 130mV of hysteresis.

REF

(Pin 26/Pin 27): This is the output of the Reference.

This pin should be bypassed to GND with a 1µF ceramic

capacitor. The reference is able to supply a minimum of

10mA of current and is internally short-circuit current

limited.

(Pin 27/Pin 28): The triangular wave oscillator timing

capacitor pin is used in conjunction with R

to set the

oscillator frequency. The equation for calculating fre-

quency is:

fRC

OSC TT

=075.

•

(Pin 28/Pin 29): A single resistor from R

to AGND sets

the charging and discharging currents for the triangle

oscillator. This pin also sets the dead time between turning

one set of outputs off and turning the other set on to ensure

the outputs do not cross conduct. The voltage on this pin

is regulated to 0.5V. For best performance, the current

sourced from the R

pin should be limited to a maximum

150µA. Selecting R

to be 10k is recommended and

provides 90ns of dead time.

TEC

(Pin 14/Pin 12): Output of the differential TEC voltage

amplifier equal to the magnitude of the voltage across

the␣ TEC.

TEC

–

(Pin 15/Pin 13): Inverting Input to the Differential TEC

Voltage Amplifier. This amplifier has a fixed gain of 1 with its

output being the voltage across the TEC with respect to

AGND. This input, along with TEC

, signifies whether the

TEC is heating or cooling the laser as indicated by the

H/C␣ pin.

TEC

(Pin 16/Pin 14): Noninverting Input to the Differen-

tial TEC Voltage Amplifier.

TEC

(Pin 17/Pin 15): Output of the Differential Current

Sense Amplifier. The voltage on this pin is equal to 10 •

TEC

+ I

RIPPLE

) • R

, where I

TEC

is the thermoelectric

cooler current, I

RIPPLE

is the inductor ripple current and R

is the sense resistor used to sense this current. This

voltage represents only the magnitude of the current and

provides no direction information. Current limit occurs

when the voltage on this pin exceeds the lesser of 1.5

times the voltage on SS, 1.5 times the voltage on I

LIM

1.5V. When this condition is present, the pair of outputs,

which are presently conducting, are immediately turned

off. The current limit condition is cleared when the C

reaches the next corresponding peak or valley (see Cur-

rent Limit section).

–

(Pin 18/Pin 16): Inverting Input to the Differential

Current Sense Amplifier.

(Pin 19/Pin 17): Noninverting Input of the Differential

Current Sense Amplifier. The amplifier has a fixed gain

of␣ 10.

PDRVA, PDRVB (Pins 20, 25/Pins 18, 24): These push-

pull outputs are configured to drive the opposite high side

PMOS switches in a full-bridge arrangement.

(GN Package/UH Package)

LTC1923

1923f

FU CTIO AL DIAGRA

–

TSD

1.5V

ENABLE

1/2 VDD 1 = NO SLEW LIMITING

SWITCHES OPEN

350mV

OPEN/SHORTED THERMISTOR

0.2VSET

VSET

CNTRL

–

SDSYNC

PLLLPF

RSLEW

SLEW LIMITING

VDD

ISLEW

0.7V

1 = SHDN

VDD + VBE

EAOUT

RAMP = 0.5V – 1.5V

0.5V

IRT

VTHRM

DIGITAL

PHASE

DETECTOR

SHUTDOWN

COMPARATOR

MASTER

COMPARATOR

OSCILLATOR

ERROR

AMPLIFIER

FAULT ITEC VTEC H/C

1923 BD

TEC+

CS–

CS+

ILIM

1.5µA

PGND

NDRVB

VDD

TEC–

2.5V LDO

REF

VREF

AGND

REFGOOD

UVLO

SHDN

TSD

VBG

VREF GOOD

COMPARATOR

1 = REFGOOD

ENABLE

UVLO

1 = UVLO

VDD

20µs

DELAY

ENABLE

OSC VALLEY

CURRENT LIMIT

–

INPUT

SELECT

X10

CS AMP

TEC AMP

–

INPUT

SELECT

DIRECTIONAL

COMPARATOR

–

0.3V

VDD – 0.4V

–

2.5V

TEC

CLAMP

VTEC

–

ENABLE

OSC PEAK

NDRVA

PDRVB

PDRVA

VDD

90ns

DELAY

PDRVA

PDRVB

NDRVA

90ns

DELAY

∝

IRT

NDRVA

LTC1923

1923f

OPERATIO

MAIN CONTROL LOOP

The LTC1923 uses a constant frequency, voltage mode

architecture to control temperature. The relative duty

cycles of two pairs of N-/P-channel external MOSFETs, set

up in a full-bridge (also referred to as an H-bridge)

configuration are adjusted to control the system tempera-

ture. The full-bridge architecture facilitates bidirectional

current flow through a thermoelectric cooler (TEC) or

other heating element. The direction of the current flow

determines whether the system is being heated or cooled.

Typically a thermistor, platinum RTD or other appropriate

element is used to sense the system temperature. The

control loop is closed around this sense element and TEC.

The voltage on the output of the error amplifier, EAOUT,

relative to the triangle wave on C

, controls whether the

TEC will be heating or cooling. A schematic of the external

full bridge is shown in Figure 1. The “A” side of the bridge

is comprised of the top left PMOS, MPA, and lower right

NMOS, MNA. The gates of these devices are attached to

the PDRVA and NDRVA outputs of the LTC1923, respec-

tively. The “B” side of the bridge is comprised of PMOS,

MPB and NMOS, MNB. The gates of these MOSFETs are

controlled by the PDRVB and NDRVB outputs of the

LTC1923.

The “A” side of the bridge is turned on (NDRVA is high and

PDRVA is low) when the output of the error amplifier is

less than the voltage on the C

pin as shown in Figure 2.

For this condition, the state of each output driver is as

follows: PDRVA is low, NDRVA is high, PDRVB is high and

NDRVB is low. When the voltage on EAOUT is greater than

the voltage on the C

pin, the “B” side of the bridge is

turned on. The average voltage across the TEC, V

TECOOLER

is approximately:

TECOOLER

= V

TEC+

– V

TEC–

= V

•␣ (D

– D

)

where

= the full-bridge supply voltage

TECOOLER

= V

TEC+

– V

TEC–

= the duty cycle of the “A” side of the bridge or the

amount of time the “A” side is on divided by the

oscillator period

= the duty cycle of the “B” side of the bridge

Duty cycle terms D

and D

are related by the following

equation:

= 1 – D

In steady-state, the polarity of V

TECOOLER

indicates whether

the system is being heated or cooled. Typically, when

current flows into the TEC

side of the cooler, the system

is being cooled and heated when current flows out of this

terminal.

Note: Do not confuse the TEC

side of the TEC

with the TEC

input of the LTC1923, although these two

points should be connected together

MNA

1923 F01

MPB

MPA

–+

MNBNDRVB

NDRVA

–

TEC

–

PDRVA

PDRVB

TEC

TECOOLER

NDRVA A

SIDE

EAOUT

PDRVA

NDRVB

PDRVB

1923 F02

Figure 1. Full-Bridge Schematic Figure 2. Error Amplifier Output, CT and Output Driver Waveforms

LTC1923

1923f

PROTECTION FEATURES

Many protection features have been integrated into the

LTC1923 to ensure that the TEC is not overstressed or the

system does not thermally run away. These features

include pulse-by-pulse current limiting, TEC voltage clamp-

ing and open/shorted thermistor detection.

Current Limit

The peak current in the full bridge during each switching

cycle can be limited by placing a sense resistor, R

, from

the common NMOS source connections of MNA and MNB

to ground. The CS

and CS

–

connections should be made

as shown in Figure 1. Current limit is comprised of a fixed

gain of ten differential amplifier, an attenuator (resistor

divider) and a current limit comparator. A detailed diagram

of the circuitry is shown in Figure 3. The differential

amplifier output, I

TEC

, is provided to allow the user the

ability to monitor the instantaneous current flowing in the

bridge. If an average current is desired, an external RC

filter can be used to filter the I

TEC

output. Approximately

50ns of leading edge blanking is also internally integrated

to prevent nuisance tripping of the current sense circuitry.

It relieves the filtering requirements for the CS input pins.

During a switching cycle, current limit occurs when the

voltage on ITEC exceeds the lowest of the following three

conditions: 1) 1.5 times the voltage on the SS pin, 2) 1.5

times the voltage on the ILIM pin or 3) 1.5V. When a

current limit condition is sensed, all four external FETs are

immediately shut off. These devices are turned back on

only after CT reaches the same state (either charging or

OPERATIO

discharging) as when the current limit condition oc-

curred. For instance, if CT is charging when current limit

occurs, the outputs are forced off for the remainder of this

charging time, the entire CT discharge time, and are only

re-enabled when CT reaches its valley voltage and begins

charging again. An analogous sequence of events occurs

if current limit is tripped while CT is being discharged.

The full-bridge current can be soft-started (gradually

increased) by placing a capacitor from the SS pin to

ground. A 1.5µA current is sourced from the chip and will

charge the capacitor. This limits the inrush current at start-

up and allows the current delivered to the TEC to be linearly

increased from zero.

The LTC1923 features a dedicated pin, I

LIM

, to adjust

current limit. If the voltage placed on I

LIM

is greater than

1V, the default current limit, I

LIMIT

, is:

LIMIT

= 150mV/R

where R

= the current sense resistor.

Utilizing the I

LIM

pin allows the current limit threshold to

be easily set and adjusted (the current limit threshold can

also be adjusted by changing R

). More importantly, it

facilitates independent setting of the heating and cooling

current limits with the addition of one transistor. Figure 4

shows how to implement this using three resistors and an

external NMOS, M1. In many applications, a higher cool-

ing capability is desired. When TEC

is greater than

TEC

–

, the H/C output is in a low state signifying that the

system is being cooled (this is typical for most lasers).

–

A = 10

2R 1V

NDRVB

CURRENT SENSE

AMPLIFIER

PULSE-BY-PULSE

CURRENT LIMIT

TEC

–

NDRVATEC

NDRVB

OSCILLATOR

PEAK/VALLEY

NDRVA

TEC

LIM

SS 1.5µA

INPUT SELECT

LEB

1923 F03

SHUT

OUTPUTS

OFF

–

Figure 3. Current Sense Circuitry

LTC1923

1923f

Transistor M1 is off and the current limit threshold is given

by:

IRV

RR R

LIMIT ILIM REF

ILIM ILIM S

()

015

.• •

•

When TEC

–

is greater than TEC

, the open-drain output,

H/C, pulls high through R

PULLUP

, causing M1 to turn on.

The current limit value is given by:

IRR V

RRRR

LIMIT ILIM ILIM REF

ILIM ILIM ILIM S

()

015

213

.• •

•

reducing the current limit threshold for heating. If the

heating current limit needs to be greater than the cooling

limit, an extra inversion can be added.

Open/Shorted Thermistor Detection

The temperature sense element (NTC thermistor, plati-

num RTD or other appropriate component) must be prop-

erly connected in order for the system to regulate

temperature. If the sense element is incorrectly con-

nected, the system will be unable to control the tempera-

ture and the potential exists for the system to thermally run

away.

A TEC by nature produces a temperature differential be-

tween opposite sides of the device depending upon how

much current is flowing through it. There is a maximum

limit to the amount of temperature differential that can be

produced, which depends upon a number of physical

OPERATIO

parameters including the size of the TEC and how well

heatsinked the device is. The TEC itself dissipates power

to produce the temperature differential, generating heat,

which must also be removed. At a certain level of power

dissipation in the TEC, both sides will begin to heat. This

is because the TEC will not be able to pump the self-

generated heat to the outside world, which can lead to

thermal runaway. If the device thermally runs away, dam-

age to the TEC and possibly the components whose

temperature is being regulated will occur.

The LTC1923 contains two dedicated comparators that

directly monitor the voltage on the thermistor. If this

voltage is outside the valid window, a latch is set and the

FAULT pin is asserted low. The output drivers are not shut

off and the control circuitry is not disabled, meaning the

part will continue to try to regulate temperature. It is up to

the user to use the FAULT signal to disable the appropriate

circuitry. There are a couple of ways to do this. The first

way is to have the FAULT signal a system microprocessor

to shut the system down through the SDSYNC pin. Fig-

ure␣ 5 shows another means of protecting the system.

External NMOS M1 and PMOS M2 have been added along

with two pull-up resistors (RP1 and RP2). M1 and RP2

invert the FAULT signal while M2 acts as a switch in series

with bridge. When no fault is present, the gate of M1 is

–

H/C

2N7002

LTC1923

LIM

TEC

–

1923 F04

LIM3

ILIM1

ILIM2

REF

PULLUP

Figure 4. Independently Heating/Cooling Current Limit

1923 F05

NDRVB

NDRVA

–

PDRVA

PDRVB

FAULT M1

TEC

Figure 5. Redundant Fault Protection

LTC1923

1923f

pulled to V

forcing the gate of M2 low, which allows the

bridge to operate as described earlier. When a fault occurs

and FAULT is asserted low, M1 is shut off, forcing the gate

of M2 high, shutting that device off. The power path is thus

opened, ensuring no current is delivered to the TEC. M2

wants to have low R

DS(ON)

(less than the value of R

minimize the power losses associated with it). R

and

can be selected on the order of 100k.

The lower comparator threshold level is 20% (twenty

percent) of V

SET

and the upper comparator threshold level

is 350mV below V

SET

, where V

SET

is the voltage applied on

the V

SET

pin. V

SET

is typically tied to the bias source for the

thermistor divider so that any variations will track out.

The V

SET

pin has a high input impedance so that a divided-

down voltage can be supplied to this pin to modify the

acceptable thermistor impedance range. This is shown in

Figure 6. The voltage applied to the V

SET

pin must be a

minimum of 2V. The lower thermistor impedance thresh-

old is:

RRR

TH LOWER()

.• •

.•

02 1 3

208 3

The upper impedance threshold is:

RRR R R

RRR

TH UPPER()

–( )

()

13 2 3

223

where α = 0.35/V

SET

Changing R1 also changes the valid thermistor impedance

range.

Example: V

REF

= V

SET

= 2.5V

R1 = 10k, R2 = 0Ω, R3 = open

= 10k NTC thermistor with a temperature coeffi-

cient of –4.4%/C at 25°C.

The acceptable thermistor impedance range before caus-

ing a fault is 2.5kΩ to 61kΩ. This corresponds to a valid

temperature range of between about –10°C and 60°C.

To ensure the part does not power up with a latched fault

at start-up, a fault will not be latched until soft-start has

completed. This corresponds to the voltage on SS reach-

ing 1.5V. For a 1µF soft-start capacitor, this delay is

approximately 1 second. This provides enough time for all

supplies (V

, setpoint reference and V

REF

) to settle at

their final values.

TEC Voltage Clamping

An internal clamp circuit is included to protect the TEC

from an overvoltage condition. When the differential volt-

age across the TEC exceeds 2.5V, the error amplifier

output voltage at the input of the PWM comparator is

limited. This clamps the duty cycle of the output drivers,

and therefore, the voltage across the TEC. The voltage

where clamping occurs can be increased by placing a

resistor divider in parallel with the TEC and by making the

appropriate connections to TEC

and TEC

–

as shown in

Figure 7. The divider increases the voltage across the TEC,

TECOOLER

, where the clamp activates, to:

kVR

TECOOLER

TE CM TE

=++



















1100 25 200

1200

•.–

REF

SET

THRM

1923 F06

10k

NTC

Figure 6. Modifying the Acceptable Thermistor Range

TEC

TE2

TE1

1923 F07

TECOOLER

+–

TEC

–

Figure 7. Increasing Voltage Clamp Threshold

OPERATIO

LTC1923

1923f

The terms containing the fixed resistance values are the

loading errors introduced by the input impedance of the

differential amplifier. A common mode voltage error is

also introduced since the addition of R

TE1

and R

TE2

change

the fully differential nature of the amplifier. In order to

minimize these errors select R

TE1

and R

TE2

to be 10k or

less. The above equation reduces to:

TECOOLER TE

≅+











125

The Higher Voltage Applications section shows a fully

differential means to increase the clamp voltage.

This will similarly alter the heating and cooling direction

thresholds by the same factor, increasing the thresholds

TE1

and R

TE2

are assumed to be ≤10k)

DIRH mV R

DIRL mV R





















50 1

–

The output voltage on the VTEC pin, V

VTEC

, will be reduced

by the same ratio:

VTEC TECOOLER

=+11

Oscillator Frequency

The oscillator determines the switching frequency and the

fundamental positioning of all harmonics. The switching

frequency also affects the size of the inductor that needs

to be selected for a given inductor ripple current (as

opposed to TEC ripple current which is a function of both

the filter inductor and capacitor). A higher switching

frequency allows a smaller valued inductor for a given

ripple current. The oscillator is a triangle wave design. A

current defined by external resistor R

is used to charge

and discharge the capacitor C

. The charge and discharge

rates are equal. The selection of high quality external

components (5% or better multilayer NPO or X7R ceramic

capacitor) is important to ensure oscillator frequency

stability.

The frequency of oscillation is determined by:

OSC(kHz)

= 750 • 10

/[R

(kΩ) • C

(pF)]

The LTC1923 can run at frequencies up to 1MHz. The value

selected for R

will also affect the delay time between one

side of the full bridge turning off and the opposite side

turning on. This time is also known as the “break-before-

make” time. The typical value of 10kΩ will produce a 90ns

“break-before-make” time. For higher frequency applica-

tions, a smaller value of R

may be required to reduce this

delay time. For applications where significant slew rate

limiting or external gate driver chips are used, a higher

value for R

may necessary, increasing the dead time. The

“break-before-make” time can be approximately calcu-

lated by:

DELAY

= R

(kΩ) • 5.75 • 10

–9

+ 35ns

Phase-Locked Loop

The LTC1923 has an internal voltage-controlled oscillator

(VCO) and phase detector comprising a phase-locked

loop. This allows the oscillator to be synchronized with

another oscillator by slaving it to a master through the

SDSYNC pin. The part can also be designated as the

master by pulling the PLLLPF pin high to V

. This will

result in the part toggling the SDSYNC pin at its set

oscillator frequency. This signal can then be used to

synchronize additional oscillators.

When being slaved to another oscillator, the frequency

should be set 20% to 30% lower than the target frequency.

The frequency lock range is approximately ±50%.

The phase detector is an edge sensitive digital type, which

provides zero degrees phase shift between the external

and internal oscillators. This detector will not lock up on

input frequencies close to the harmonics of the VCO center

frequency. The VCO hold-in range is equal to the capture

range dfH = dfC = ±0.5f

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLLPF pin. A simplified block

diagram is shown in Figure 8.

OPERATIO

LTC1923

1923f

If the external frequency (f

PLLIN

) is greater than the oscil-

lator frequency, current is sourced continuously out of the

PLLLPF pin. When the external frequency is less than the

oscillator frequency, current is sunk by the PLLLPF pin.

The loop filter components R

, C

and C

LP2

, smooth out

current pulses from the phase detector and provide a

stable input to the VCO. These components also determine

how fast the loop acquires lock. In most instances C

LP2

can be omitted, R

can be set to 1k and C

can be

selected to be 0.01µF to 0.1µF to stabilize the loop. Make

sure that the low side of filter components is tied to AGND

to keep unwanted switching noise from altering the perfor-

mance of the PLL.

Figure 9 illustrates three different ways to set the oscilla-

tor frequency. In Figure 9a, the oscillator is free running

with the frequency determined by RT and CT. In Figure 9b,

DIGITAL

PHASE

FREQUENCY

DETECTOR

PLLLPF

SDSYNCB

LP2

OSC C

PLL

1923 F08

EXTERNAL

FREQUENCY

Figure 8. Phase-Locked Loop Block Diagram

the oscillator is slaved to an external clock. Figure 9c

illustrates how one LTC1923 can be used as a master to

synchronize other LTC1923s or additional devices requir-

ing synchronization. To implement this, determine the

values of RT and CT to obtain the desired free-running

oscillator frequency of the master by using the equation

given in the oscillator frequency section. Tie the master’s

PLLLPF pin to VDD and the SDSYNC pin to VDD through a

resistor RPLL as shown in Figure 9c. RPLL typically can be

set to 10k, but may need to be a lower value if higher

frequency operation is desired (above 250kHz). Set the

slave free-running frequencies to be 20% to 30% less

than this. The SDSYNC pin of the master will switch at its

free-running frequency (with approximately 50% duty

cycle), and this can be used to synchronize the other

devices.

OPERATIO

PLLLPF

LTC1923

SDSYNC

1923 F09a

PLLLPF

LTC1923

SDSYNC

CLP2 RLP

CLP

CLKIN C

1923 F09b

PLLLPF

LTC1923

SDSYNC

VDD

PLLLPF

LTC1923

MASTER SLAVE

1923 F09c

SDSYNC

CLP2 RLP

CLP

1.2 • RT

RPLL

(9a) Free Running (9b) Slave Operation with External Clock—

Set Oscillator Frequency at 70% to 80% of External Clock

Figure 9. Oscillator Frequency Setup: a) Free Running b) Slaved Operation c) Master/Slave Operation

(9c) Master/Slave Operation—Set Oscillator Frequency of Slave at 70% to 80% of Master

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

The thermistor may be isolated from the control circuitry.

It has a relatively high input impedance and is therefore

susceptible to noise pick up. Extreme care should be taken

to ensure this signal is noise free by shielding the line

(coaxially). A lowpass filter can be added between the

thermistor and the input to the LTC2053, but since it is in

the signal path, there are limitations on how much filtering

can be added.

Inductor Ripple Current

The current that flows in the bridge can be separated into

two components, the DC current that flows through the

TEC and the inductor ripple current that is present due to

the switchmode nature of the controller. Although the TEC

current has its own ripple component, proper filtering will

minimize this ripple relative to the inductor ripple current,

validating this assumption that the TEC current is constant

(see TEC Ripple Current section). A simplified half-circuit

of the bridge in steady-state is shown in Figure 10. The

current, I

, through the inductor (L) consists of the ripple

current (∆I

) and static TEC current (I

TEC

). The ripple

current magnitude, ∆I

, can be calculated using the fol-

lowing equation:

∆I

= (V

BRIDGE2

– V

TEC2

)/(4 • f

OSC

• L • V

BRIDGE

)

where

BRIDGE

is the full-bridge supply voltage (typically V

)

OSC

is the oscillator frequency

L is the filter inductor value

TEC

is the DC voltage drop across the TEC

The peak inductor current is equal to ITEC + ∆I1/2 and is

the current level that trips the current limit comparator.

Keeping the ripple current component small relative to

ITEC keeps the current limit trip level equal to the current

flowing through the TEC.

Example: V

BRIDGE

= 5V, R

TEC

= 2.5Ω, V

TEC

= 2.5V,

TEC

= 1A, L = 22µH, f

OSC

= 250kHz. The peak-to-peak

ripple current using the above equation is:

∆I

= 170mA

The peak inductor current is therefore 1.085A in order to

get 1A of DC TEC current.

TEC Ripple Current

Every TEC has a fundamental limitation (based mainly on

the TEC’s physical characteristics) on the maximum

temperature differential that it can create between sides.

The ability to create this maximum temperature differen-

tial is affected by the amount of ripple current that flows

through the device, relative to the DC component. An

approxima

tion of this degradation due to TEC ripple cur-

rent is given by the following equation:

dT/dT

MAX

= 1/(1 + N

)

where:

dT is the adjusted achievable temperature differential

MAX

is the maximum possible temperature differen-

tial when the TEC is fed strictly by DC current and is

typically specified by the manufacturer

N is the ratio of TEC ripple current to DC current

TEC manufacturers typically state that N should be no

greater than 10%.

MPA

MNB

PDRVA

NDRVB ESR V

TEC

1923 F10

TEC

1/2 V

BRIDGE

Figure 10. Full-Bridge Half Circuit

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

In this application, the bridge supply voltage, oscillator

frequency and external filter components determine the

amount of ripple current that flows through the TEC.

Higher valued filter components reduce the amount of

ripple current through the TEC at the expense of increased

board area. Filter capacitor ESR along with inductor ripple

current will determine the peak-to-peak voltage ripple

across the TEC and therefore the ripple current since the

TEC appears resistive.

The ripple current through the TEC, I

TEC(RIPPLE)

, is

approximately equal to:

IVV

fLCRV

V V ESR

fLV R

TEC RIPPLE BRIDGE TEC

OSC TEC BRIDGE

BRIDGE TEC

OSC BRIDGE TEC

()

–

•••••

–•

••• •

≅

()

where:

OSC

= the oscillator frequency

L = the filter inductor value

C = the filter capacitor value

TEC

= the resistance of the TEC

TEC

= the DC voltage drop across the TEC

ESR = the equivalent series resistance of the filter

capacitor

BRIDGE

= the full-bridge supply voltage typically equal

to V

The equation above shows that there are two components,

which comprise TEC ripple current. The first term is the

increase in voltage from the charging of the filter capaci-

tor. The second term is due to the filter capacitor ESR and

is typically the dominant contributor. Therefore the filter

capacitor selected wants to have a low ESR. This capacitor

can be made of multilevel ceramic, OS-CON electrolytic or

other suitable capacitor. Increasing the oscillator fre-

quency will also reduce the TEC ripple current since both

terms have an inverse relationship to operating frequency.

Example: V

BRIDGE

= 5V, R

TEC

= 2.5Ω, V

TEC

= 2.5V,

L = 22µH, C = 22µF, f

OSC

= 250kHz, ESR = 100mΩ

TEC(RIPPLE)

= 3.1mA + 13.6mA = 16.7mA

For this example the DC current flowing through the TEC

is 1A, making the ripple current equal to approximately 1.7%

(this illustrates why I

TEC

can be approximated to be DC).

Closing the Feedback Loop

Closing the feedback loop around the TEC and thermistor

(or other temperature sensitive element) involves identify-

ing where the thermal system’s poles are located and

placing electrical pole(s) (and zeroes) to stabilize the

control loop. High DC loop gain is desirable to keep

extremely tight control on the system temperature. Unfor-

tunately the higher the desired loop gain, the larger the

compensation values required to stabilize the system.

Given the inherently slow time constants associated with

thermal systems (on the order of many seconds), this can

lead to unreasonably large component values. Therefore,

the amount of loop gain necessary to maintain the desired

temperature accuracy should be calculated, and after

adding some margin, this should be the target DC loop

gain for the system. A block diagram of the system is

shown in Figure 11. The gain blocks are as follows:

= instrumentation amplifier gain (V/V)

= error amplifier gain (V/V)

MOD

= modulator gain (d/V)

PWR

= power stage gain (V/d)

TEC

= TEC gain (°C/V)

THRM

= Thermistor Gain (V/°C)

and K

are the electrical gains associated with the

instrumentation and LTC1923 error amplifier. Switching

regulators are sampled systems that convert voltage to

duty cycle (d), which explains why the K

MOD

and K

PWR

gain terms are expressed as a function of duty cycle and

voltage. The TEC converts voltage to temperature change,

while the thermistor’s impedance and therefore voltage

across it changes with temperature.

The loop gain can be expressed by the following equation:

T (loop gain) = K

• K

MOD

• K

PWR

• K

TEC

• K

THRM

And the error introduced by the finite gain of the system,

, can be expressed by:

= V

/(1 + T)

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

–

LTC1923LTC2053

REF

THRM

MOD

PWR

TEC

10k

NTC

–

POWER

STAGE

TEC

1923 F11

TECOOLER

ERROR

AMP

Figure 11. Simplified Loop Block Diagram

This voltage error translates back into a temperature

setpoint error.

Example:

THRM

= 10k

NTC with 4.4%/°C at 25°C

R1 = 10k

REF

= 2.5V

T = 25°C

For this thermistor with a 25°C temperature setpoint, the

change in thermistor voltage with temperature is given by

–25mV/°C. In order to maintain a 0.01°C temperature

accuracy, this translates into a 250µV error signal, V

. The

minimum loop gain can now be calculated from the above

equation:

= V

/(1 + T)

A 25°C setpoint temperature requires VIN = 1.25V for

VREF = 2.5V. The required loop gain is 5000 or 74dB.

There are two handles to adjust the loop gain, K

and K

while the other handles are fixed and depend upon the TEC

and thermistor characteristics (K

TEC

and K

THRM

), V

SET

and

R1 (K

THRM

) and V

MOD

and K

PWR

). The modulator and

power gain product is given by:

MOD

• K

PWR

= 2 • V

where V

= the C

voltage which has a fixed 1V amplitude.

The TEC gain depends upon the TEC selected and corre-

sponds to the relationship between the voltage across the

device and what temperature differential is created. This

gain term changes with operating temperature, and whether

the TEC is heating or cooling. TECs are inherently more

efficient at heating (and therefore have a higher gain) as

compared to cooling. A worst-case rough estimation of

the gain can be obtained by taking the maximum TEC

voltage required to force a given change in temperature

from the TEC specifications:

TEC

= dT/V

TEC(MAX)

The thermistor gain should be linearized around tempera-

ture setpoint.

Example:

Setpoint T = 25°C

= 5V

THRM

= 10k NTC with 4.4%/°C at 25°C

R1 = 10k

REF

= 2.5V

dT/V

TEC(MAX)

= 45°C/1.5V = 30°C/V

LTC1923

1923f

TMP

CMD

–

REF

OUT

LTC1658

10k

NTC

REF R

CNTRL

EAOU

LTC1923

ERROR

AMPLIFIER

1923 F1

A = 10

LTC2053

Figure 12. Alternative Compensation Method to Improve Transient Response

APPLICATIO S I FOR ATIO

WUUU

The linearized thermistor gain around 25°C is –25mV/°C.

For a minimum loop gain of 5000 as calculated above, the

combined gain of the instrumentation and error amplifiers

can be calculated:

• K

= T/(K

MOD

• K

PWR

• K

TEC

• K

THRM

)

• K

= 5000/(10 • 30 • 0.025) = 667

A combined gain of 1000 can be selected to provide

adequate margin. The instrumentation amplifier gain should

be set at typically 10, as this attenuates any errors by its

gain factor. The error amplifier gain would then be limited

to the remainder through the gain setting resistors, R

and

shown in Figure 11.

= KEA – 1

The multiple poles associated with the TEC/thermistor

system makes it difficult to compensate. Compounding

this problem is that there will be significant variations in

thermal time constants for the same system, making

elaborate compensation schemes difficult to reliably imple-

ment. The most robust method (i.e., least prone to

oscillation) is to place a dominant pole well below the

thermal system time constant (τ) (anywhere from many

seconds to minutes). This time constant will set the

capacitor value by the following equation:

Please refer to Application Note 89 for more detailed

information on compensating the loop. Ceramic capaci-

tors are not recommended for use as the integrating

capacitor or anywhere in the signal path as they exhibit a

piezoelectric effect which can introduce noise into the

system. The component values shown on the front page of

this data sheet provide a good starting point, but some

adjustment may be required to optimize the response.

Dominant pole compensation does have its limitations. It

provides good loop response over a wide range of laser

module types. It does not provide the fastest transient

response to step changes in temperature. If this is a

necessity, a more complex compensation approach as

shown in Figure 12 may be required. This approach adds

an additional zero into the feedback loop to speed up the

transient response. First note that the LTC2053 inputs

have been swapped as the LTC1923 error amplifier is now

running in an inverting configuration. Capacitor C

needed to provide the lead term. Resistor R

is used to

buffer the LTC2053 from capacitive loading and limit the

error amplifier high frequency gain.

Since the system thermal pole locations are not known, a

qualitative compensation approach must be employed.

This entails looking at the transient response when the

TEC is heating (due to the inherent higher gain) for a small-

signal step change in temperature and modifying compen-

sation components to improve the response. A reasonable

starting point is to select components that mimic the

response that will be obtained from the front page of this

data sheet. Therefore R

, R

and C

would be selected to

be 1MΩ, 1MΩ and 0.47µF, respectively. R

should be

selected to be a factor of 100 smaller than R

, or on the

order of 10k. Make sure that the loop is stable prior to the

introduction of capacitor C

. The addition of C

will

provide some phase boost in the loop (in effect, offsetting

one of the poles associated with the thermal system). Start

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

–

REF

OUT

TMP

CMD

LTC1658

10k

NTC

LTC1923

ERROR

AMPLIFIER

1923 F13

4.7µF10M

10k

100k 6

CNTRL

EAOUT

Figure 13. Simplifed Temperature Control Loop Omitting

the LTC2053 Instrumentation Amplifier Front End

with C

on the order of C

and note its affect on system

response. Adjust the values based on observing whether

the transient response was improved or not with the goal

of reducing C

to improve settling time. As the system

thermal poles can vary between “identical” laser modules

(i.e., same manufacturer and model), care must be taken

to ensure that the values selected provide the desired

response even with these thermal term variations. Com-

pensation should also be tailored for each unique laser

module as thermal terms can vary significantly between

different brands. C

rolls off high frequency gain , mini-

mizing noise in the outputs. It is typically about 25 times

smaller than C

. C

, C

and C

should be film capacitors.

Temperature Stability

It is important to differentiate between temperature accu-

racy and stability. Since each laser’s output maximizes at

some temperature, temperature setpoint is typically

incremented until this peak is achieved. After this, only

temperature stability is required. The predominant param-

eters which affect temperature stability are the thermistor,

the thermistor biasing resistor and any offset drift of the

front-end electrical circuitry. Sufficient loop gain ensures

that any downstream variations do not contribute signifi-

cantly to temperature stability. The relatively mild operat-

ing conditions inside the laser module promote good long-

term thermistor stability. A high quality, low temperature

coefficient resistor should be selected to bias the ther-

mistor. If the 10k resistor has a 100ppm/°C temperature

coefficient, this translates into a 0.18°C setpoint tempera-

ture differential over a 0°C to 70°C ambient for a desired

25°C laser setpoint. Depending upon the temperature

stability requirements of the system, this is very signifi-

cant. A lower temperature coefficient resistor may there-

fore be desired. The LTC2053 has maximum offset drift to

50nV/°C which translates into less than 0.001°C change

for a 0°C to 70°C ambient.

The offset drift of the LTC1923 error amplifier divided by

the gain of the LTC2053 also affects temperature stability.

The offset drift of the LTC1923 (see characteristic curves)

is typically 1mV over a 0°C to 70°C ambient. After attenu-

ation by the LTC2053 gain, this translates into a tempera-

ture setpoint variation of 0.004°C. Neither of these offsets

drifts significantly with aging. Depending upon the setpoint

temperature stability requirements of the system, the

LTC2053 instrumentation amplifier may not be necessary.

Figure 13 shows a simplified schematic with the LTC2053

omitted.

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

Noise and Slew Rate Control

One disadvantage of switching regulators is that the

switching creates wideband harmonic energy. The high

frequency content can pose problems to associated cir-

cuitry. To combat this issue, the LTC1923 offers a pin

called R

SLEW

that controls the slew rate of the output drive

waveforms. Slowing down the transition interval reduces

the harmonic frequency content by spreading out the

energy over a longer time period. The additional transition

time causes some efficiency loss (on the order of 2% to

3%) but significantly improves the high frequency noise

reflected onto the input supply.

Slew rate control is engaged by placing a resistor from

SLEW

to AGND. If slew rate control is not desired, the R

SLEW

pin should be tied to V

allowing the output drivers to

transition at their fastest rate. The resistor value should be

set between 10k (fastest transition) and 300k (slowest tran-

sition). This provides about a 10:1 slew rate range to op-

timize noise performance. The “break-before-make” time

may need to be increased if slew control is implemented,

especially for slower transition rates. Adjustment can be

done by increasing the value of R

can be reduced to

maintain the same frequency of operation), to ensure that

the bridge MOSFETs receive nonoverlapping drive.

Power MOSFET Selection

Four external MOSFETs must be selected for use with the

LTC1923; a pair of N-channel MOSFETs for the bottom of

the bridge and a pair of P-channel MOSFETs for the top

diagonals of the bridge. The MOSFETs should be selected

for their R

DS(ON)

, gate charge and maximum V

DS,

ratings. A maximum V

rating of 20V is more than

sufficient for 5V and 12V bridge applications, but as

mentioned in the High Voltage Application section, a 12V

maximum V

rating is insufficient and higher voltage

MOSFETs must be selected. There is a trade-off between

DS(ON)

and gate charge. The R

DS(ON)

affects the conduc-

tion losses (I

TEC2

• R

DS(ON)

), while gate charge is a

dominant contributor to switching losses. A higher R

DS(ON)

MOSFET typically has a smaller gate capacitance and thus

requires less current to charge the gate for the same

DSS

. For 1A TEC applications, the Si9801DY or Si9928DY

complimentary N- and P-channel MOSFETs provide a

good trade-off between switching and conduction losses.

Above this TEC current level the MOSFETs selected should

have lower R

DS(ON)

to maintain the high end efficiency.

Efficiency Considerations

Unlike typical voltage regulators, where the output voltage

is fixed, independent of load current, the output voltage of

this regulator changes with load current. This is because

the TEC appears resistive and the current through the TEC

sets the voltage. The output power of the regulator is

defined as:

OUT

= I

TEC2

• R

TEC

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%.

Often it is useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most significant improvement. Efficiency can

be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + …)

where L1, L2, etc. are the individual losses as a percentage

of input power.

For this application, the main efficiency concern is typi-

cally at the high end of output power. A higher power loss

translates into a greater system temperature rise, result-

ing in the need for heat sinking, increasing both the system

size and cost.

There are three main sources which usually account for

most of the losses in the application shown on the front

page of the data sheet: Input supply current, MOSFET

switching losses and I

R losses.

1) The input supply current is comprised of the quiescent

current draw from the LTC1658, LTC2053, LTC1923 and

any additional circuitry added. The total maximum supply

current for these devices is on the order of 5mA, which

gives a total power dissipation of 25mW. This power loss

is independent of TEC current.

2) The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time a gate

is switched from low to high to low again, a packet of

charge dQ moves from V

to ground. The gate charging

current, I

GATECHG

= 2 • f • (Q

+ Q

), where Q

and Q

are

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

the total gate charges of the NMOS and PMOS on one side

of the bridge, and f is the oscillator frequency. The factor

of 2 arises from there being two sets of MOSFETs that

make up the full bridge. Note that increasing the switching

frequency will increase the dynamic current and therefore

power dissipation by the same factor. This power loss is

independent of TEC current.

Example: Q

= 10nC max, Q

= 15nC max, f = 225kHz,

= 5V

Power loss = 2 • f • (Q

+ Q

) • V

= 56mW

3) The DC resistances of the external bridge MOSFETs,

filter inductors and sense resistor are typically the domi-

nant loss mechanism at the high end TEC current. The

conduction path of the current includes one NMOS, one

PMOS, two inductors and the sense resistor so the DC

resistances associated with the components dissipate

power.

Example:

DS(ON)NMOS

at 5V = 0.055Ω max

DS(ON)PMOS

at 5V = 0.08Ω max

= 0.1Ω

= 0.1Ω,

TEC

= 1A

TEC

= 2.5Ω

Total series resistance = 0.055 + 0.08 + 2 • 0.1 + 0.1

= 0.435Ω

Power Loss = (1A)

• 0.435Ω = 0.435W

Output Power = (1A)

• 2.5Ω = 2.5W

This represents a 17% efficiency loss due to conduction

losses. The other two power loss mechanisms comprise

a little more than a 3% efficiency loss at this output power

level. This may sound alarming if electrical efficiency is the

primary concern and can be easily improved by choosing

lower R

DS(ON)

MOSFETs, lower series resistance induc-

tors and a smaller valued sense resistor. If temperature

rise is the primary concern, this power dissipation may be

acceptable. At higher current levels, this example does

illustrate that lower resistance components should be

selected.

Low Voltage Requirements

All components shown on the front page of this data sheet

will operate with a 2.7V input supply. Minor modifications

are required to guarantee correct operation. The voltage

on the REF input of the LTC2053 should be at least 1V

below V

. Figure 14 shows how to implement this. By

dividing down the 2.5V reference with 500Ω of imped-

ance, feeding this to the REF input of the LTC2053 and the

integrating resistor of the LTC1923 error amplifier, any

common mode issues will be avoided.

REF

OUT

LTC1658

10k

NTC

A = 10

100k

1923 F14

4.7µF

10M

REF

10k

1µF

2.7V TO 3.3V

CNTRL V

REF

EAOUT

SET

THRM

250Ω

1µF

–

LTC2053

LTC1923GN

Figure 14. Low Input Supply Voltage Circuit

LTC1923

1923f

APPLICATIO S I FOR ATIO

WUUU

Higher Voltage Applications

A bank of TECs can be wired in series to minimize board

real estate utilized by the application. A higher voltage

supply may be required depending upon how many TECs

are placed in series and what their maximum voltage

drop␣ is. In other applications, only one high current

supply may be available, with the output voltage of this

supply being greater than the LTC1923’s absolute maxi-

mum voltage rating. The absolute maximum input voltage

for the LTC1923 is 6V. Since the current drawn by the

LTC1923 is small, it can be powered from a low current,

5V (or less) supply. A 12V application for driving the full

bridge is shown in Figure 15. Two LTC1693-1 high speed

dual MOSFET drivers are used to step up the lower voltage

produced by the LTC1923 drivers to the higher voltage

levels required to drive the full bridge. The LTC1693

requires proper bypassing and grounding due to its high

switching speed and large AC currents. Mount the low

ESR bypass capacitors as close to the pins as possible,

shortening the leads as much as possible to reduce

inductance. Refer to the LTC1693 data sheet for more

information. Since the LTC1693-1 low-to-high and high-

to-low propagation delays are almost identical (typically

35ns), there is minimal skew introduced by the addition

of these drivers. Sufficient dead time (typically 50ns)

between one leg of the bridge shutting off and the other

turning on, as set up by the LTC1923, will be maintained.

If this dead time is insufficient, the resistor tied to the RT

pin can be increased to increase this time.

Care must be taken to ensure that the external MOSFETs

are properly selected based on the maximum drain-source

voltage, V

, gate-source voltage, V

, and R

DS(ON)

. Many

MOSFETs that have an absolute maximum V

of 20V

have a maximum V

of only 12V, which is insufficient for

12V applications. Even the 14V maximum V

rating of the

Si9801DY may not provide adequate margin for a 12V

bridge supply voltage. Refer to Efficiency Considerations

for more discussion about selecting a MOSFET with

DS(ON).

Two pairs of resistors, R

and R

T2,

must be added to

ensure that the absolute maximum input voltage is not

exceeded on the TEC

and TEC

–

inputs. The maximum

voltage on TEC

and TEC

–

must be less than the V

input

supply to the LTC1923 which, for this example, is 5V. The

following equation will guarantee this:

BRIDGE

TDD

1100









<

where V

BRIDGE

is the supply voltage to the external bridge

circuitry and V

is the input supply to the LTC1923.

These additional level shifting resistors affect some pa-

rameters in the data sheet. The direction comparator

thresholds are increased to:

(1 + R

+ R

/100k) • 50mV and

(1 + R

+ R

/100k) • –50mV

The output voltage on the V

TEC

pin represents the voltage

across the TEC (V

TECOOLER

) reduced by a factor of

(1 + R

+ R

/100k) or:

VTEC

= V

TECOOLER

/(1 + R

+ R

/100k)

The term containing 100k is the loading error introduced

by the input impedance of the differential amplifier. Typi-

cally this value will be 100k, but can vary due to normal

process tolerances and temperature (up to ±30%). Due to

this variability, it may be desirable to minimize the loading

effect to try to keep a tight tolerance on the TEC clamp

voltage. Although it will increase quiescent current draw,

this can be accomplished by making the value of R

small as possible.

As a result of this level shifting, the TEC voltage necessary

to activate the clamp is raised. The voltage across the TEC

where the voltage clamp activates will be:

TECOOLER

= (1 + R

+ R

/100k) • 2.5V

One drawback with using the LTC1693 MOSFET drivers is

the inability to adjust the slew rate of the output drivers to

reduce system noise.

LTC1923

1923f

Figure 15. Higher Voltage Applications with the LTC1923

PLLLPF

SLEW

SDSYNCB

CNTRL

EAOUT

AGND

LIM

SET

FAULT

THRM

H/C

TEC

REF

PDRVB

NDRVB

PGND

NDRVA

PDRVA

–

TEC

–

LTC1923

1µF

IN1

GND1

IN2

GND2

CC1

OUT1

CC2

OUT2

LTC1693-1

IN1

GND1

IN2

GND2

CC1

OUT1

CC2

OUT2

LTC1693-1

4.7µF

12V

10µF47µF

0.1µF

4.7µF

0.1µFTEC

1923 F15

APPLICATIO S I FOR ATIO

WUUU

LTC1923

1923f

PLLLPF

SLEW

SDSYNC

CNTRL

EAOUT

AGND

LIM

SET

FAULT

THRM

H/C

TEC

REF

PDRVB

NDRVB

PGND

NDRVA

PDRVA

–

TEC

–

LTC1923EGN

–

LTC2053IMS8

LTC1658IMS8

14 BIT

REF

OUT

C5 330pF

C6 1µF

L1 10µHTEC–TEC+ L2 10µH

R15

0.1Ω

0.5W 1%

C2, C3, C4, C7, C8: AVX 0603YC104KAT1A (X7R, 16V)

C5: AVX 06035A331KAT1A (NPO, 50V)

C6, C14, C18, C19: AVX 06036D105KAT2A (X5R, 6.3V)

C9: TAIYO YUDEN JMK316BJ106ML-T (X7R, 6.3V)

C10, C11: PANASONIC ECP-U1C104MA5 (SM FILM, 16V)

C13: AVX TAJA475M020R (TANTALUM, 20V)

C15, C16, C17: TAIYO YUDEN JMK325BJ226MM-T (X7R, 6.3V)

D3 (OPTIONAL): PANASONIC LN1251-C-TR (RED)

D4 (OPTIONAL): PANASONIC LN1851-C-TR (ORANGE)

D5 (OPTIONAL): PANASONIC LN1351-C-TR (GREEN)

L1, L2: SUMIDA CDRH6D28-100NC

Q1, Q2: SILICONIX Si9801DY

Q3, Q4, Q5, Q6 (OPTIONAL): 2N7002

R3: KOA RN73T2AT1002B O.1%

R15: KOA SR73H2ER100F

ALL RESISTORS 5% TOLERANCE UNLESS NOTED

R10, R13, C13 MAY NEED TO BE CHANGED TO ACHIEVE DESIRED LOOP RESONSE

1923 TA02

C14

1µF

R14

1k 1%

R1 10k

GNDD

OUT

CLK

CS/LD

CLK

CS/LD

C18 1µF

SET

C15

22µF

6.3V

0.1µF

C17

22µF

6.3V

TEC

SET

Si9801DY

10k 1%

R13

100k 1%

R20

100k

R4 82k

C13

4.7µF

20V

10k

NTC+

RT1

THERMISTOR

10k NTC

NTC–

0.1µF

Si9801DY

2N7002

C16

22µF 6.3V

C10

0.1µF

SM FILM

C19

1µF

SET

9.09K

R10

10M

0.1µF

C11

0.1µF

FILM

R20

100k

2N7002

R19

200Ω

FAULT

LED (RED)

R23

100k

2N7002

R26

100k

2N7002

OPTIONAL FOR VISUAL HEATING/COOLING INDICATION

R27

200Ω

COOL

LED (GRN)

R25

200Ω

HEAT

LED (ORN)

OPTIONAL FOR VISUAL FAULT INDICATION

10k

0.1%

10µF

6.3V

Laser Temperature Control Loop Achieving Set Point Stability of 0.01°C

TYPICAL APPLICATIO

LTC1923

1923f

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

0.386 – 0.393*

(9.804 – 9.982)

GN28 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

345678 9 10 11 12

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

202122232425262728 19 18 17

13 14

1615

0.016 – 0.050

(0.406 – 1.270)

0.015 ± 0.004

(0.38 ± 0.10) × 45°

0° – 8° TYP

0.0075 – 0.0098

(0.191 – 0.249)

0.053 – 0.069

(1.351 – 1.748)

0.008 – 0.012

(0.203 – 0.305)

0.004 – 0.009

(0.102 – 0.249)

0.0250

(0.635)

BSC

0.033

(0.838)

REF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1923

1923f

 LINEAR TECHNOLOGY CORPORATION 2001

LT/TP 0502 2K • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1658 14-Bit Rail-to-Rail Micropower DAC 3V or 5V Single Supply Operation, I

= 270µA,

8-Lead MSOP Package

LTC1693-1 High Speed Dual N-Channel MOSFET Driver 1.5A Peak Output Current, 1GΩ Electrical Isolation, SO-8 Package

LTC2053 Zero Drift Instrumentation Amp Max Gain Error 0.01%, Input Offset Drift of 50nV/°C, Input Offset Voltage of 10µV

PACKAGE DESCRIPTIO

5.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

PIN 1

TOP MARK

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

3.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.23 ± 0.05

(UH) QFN 0102

0.50 BSC

0.200 REF

0.00 – 0.05

0.57 ±0.05

3.45 ±0.05

(4 SIDES)

4.20 ±0.05

5.35 ±0.05

0.23 ± 0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)