CY22150 One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator Features Nonvolatile reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. Parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. The CY22150 can be programmed at the package level. In-house programming of samples and prototype quantities is available using the CY3672 Development Kit. Production quantities are available through Cypress's value added distribution partners or by using third party programmers from BP MicrosystemsTM, HiLo SystemsTM, and others. Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source. The CY22150 provides an industry standard interface for volatile, system level customization of unique frequencies and options. Serial programming and reprogramming allows quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. Performance guaranteed for applications that require an extended temperature range. High performance suited for commercial, industrial, networking, telecom, and other general purpose applications. Application compatibility in standard and low power systems. Industry standard packaging saves on board space. Integrated phase-locked loop (PLL) Commercial and industrial operation Flash programmable Field programmable 2 Two-wire I C interface Low skew, low jitter, high accuracy outputs 3.3 V operation with 2.5 V output option 16-pin TSSOP Benefits Part Number Outputs Input Frequency Range Output Frequency Range Specifications CY22150KFZXC 6 8 MHz to 30 MHz (external crystal) 1 MHz to 133 MHz (driven clock) 80 kHz to 200 MHz (3.3 V) 80 KHz to 166.6 MHz (2.5 V) Field programmable Serially programmable Commercial temperature CY22150KFZXI 6 8 MHz to 30 MHz (external crystal) 1 MHz to 133 MHz (driven clock) 80 kHz to 166.6 MHz (3.3 V) 80 KHz to 150 MHz (2.5 V) Field programmable Serially programmable Industrial temperature Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-07104 Rev. *M * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 19, 2012 CY22150 Contents Pin Configuration .............................................................3 Frequency Calculation and Register Definitions ...........4 Default Startup Condition for the CY22150 ....................5 Frequency Calculations and Register Definitions using the I2C Interface .................................5 Reference Frequency ..................................................5 PLL Frequency, Q Counter [42H(6..0)] .......................6 PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) .....................................................6 PLL Post Divider Options [0CH(7..0)], [47H(7..0)] .......7 Charge Pump Settings [40H(2..0)] ..............................7 Clock Output Settings: CLKSRC - Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] .............................8 Test, Reserved, and Blank Registers ..........................8 I2C Interface Timing .........................................................9 Data Valid ....................................................................9 Data Frame .................................................................9 Acknowledge Pulse .....................................................9 Document Number: 38-07104 Rev. *M Applications ....................................................................11 Controlling Jitter .........................................................11 Absolute Maximum Conditions .....................................12 Recommended Operating Conditions ..........................12 DC Electrical Characteristics .........................................12 AC Electrical Characteristics .........................................13 Device Characteristics ...................................................13 Ordering Information ......................................................14 Possible Configurations .............................................14 Ordering Code Definitions .........................................15 Package Diagram ............................................................15 Acronyms ........................................................................16 Document Conventions .................................................16 Units of Measure .......................................................16 Document History Page .................................................17 Sales, Solutions, and Legal Information ......................18 Worldwide Sales and Design Support .......................18 Products ....................................................................18 PSoC Solutions .........................................................18 Page 2 of 18 CY22150 Pin Configuration Figure 1. 16-Pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD 3 14 SDAT 4 13 CLK6 CLK5 VSS AVSS 5 12 VSSL 6 11 LCLK1 LCLK2 7 10 8 9 LCLK4 VDDL SCLK LCLK3 Table 1. Pin Definitions Name Number Description XIN 1 Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, regardless of manufacturer, process, performance, or quality VDD 2 3.3 V Voltage Supply AVDD 3 3.3 V Analog Voltage Supply SDAT 4 I2C Serial Data Input AVSS 5 Analog Ground VSSL 6 LCLK Ground LCLK1 7 Configurable Clock Output 1 at VDDL level (3.3 V or 2.5 V) LCLK2 8 Configurable Clock Output 2 at VDDL level (3.3 V or 2.5 V) LCLK3 9 Configurable Clock Output 3 at VDDL level (3.3 V or 2.5 V) SCLK 10 I2C Serial Clock Output VDDL 11 LCLK Voltage Supply (2.5 V or 3.3 V) LCLK4 12 Configurable Clock Output 4 at VDDL level (3.3 V or 2.5 V) VSS 13 Ground CLK5 14 Configurable Clock Output 5 (3.3 V) CLK6 15 Configurable Clock Output 6 (3.3 V) 16 Reference Output [1] XOUT Note 1. Float XOUT if XIN is driven by an external clock source. Document Number: 38-07104 Rev. *M Page 3 of 18 CY22150 Frequency Calculation and Register Definitions The CY22150 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, and the post divider, which can be a fixed or calculated value. There are three formulas to determine the final output frequency of a CY22150 based design: CLK = ((REF * P)/Q)/Post Divider CLK = REF/Post Divider CLK = REF. The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs on the CY22150 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups. The post divider options can be applied to the calculated VCO frequency ((REF*P)/Q) or to the REF directly. In addition to the six post divider output options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Figure 2. Basic Block Diagram of CY22150 PLL DIV1N [OCH] CLKSRC Crosspoint Switch Matrix DIV1SRC [OCH] 1 Qtotal (Q+2) PFD VCO [42H] Ptotal DIV1CLK REF 0 /DIV1N /2 /3 (2(PB+4)+PO) LCLK1 [44H] LCLK2 [44H,45H] LCLK3 [45H] LCLK4 [45H] CLK5 [45H,46H] CLK6 Divider Bank 1 Divider Bank 2 [40H], [41H], [42H] 1 DIV2CLK 0 [44H] /4 /2 /DIV2N DIV2SRC [47H] DIV2N [47H] CLKOE [09H] Document Number: 38-07104 Rev. *M Page 4 of 18 CY22150 Table 2 lists the I2C registers and their definitions. Specific register definitions and their allowable values are listed below. Default Startup Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific JEDEC file produced by CyClocksRT. Parts shipped from the factory are blank and unprogrammed. In this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. Reference Frequency The REF can be a crystal or a driven frequency. For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 133 MHz. While you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use CyClocksRT to produce the required register setting file. Using a Crystal as the Reference Input The input crystal oscillator of the CY22150 is an important feature because of the flexibility it allows the user in selecting a crystal as a REF source. The input oscillator has programmable gain, allowing maximum compatibility with a reference crystal, regardless of manufacturer, process, performance, and quality. The serial interface address of the CY22150 is 69H. If there is a conflict with any other devices in your system, then this can also be changed using CyClocksRT. Programmable Crystal Input Oscillator Gain Settings Frequency Calculations and Register Definitions using the I2C Interface The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H and are set according to Table 3 on page 6. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal startup. The CY22150 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 3 on page 6. All other bits in the register are reserved and should be programmed as shown in Table 4 on page 6. The I2C Interface provides volatile programming. This means when the target system is powered down, the CY22150 reverts to its pre-I2C state, as defined above (programmed or unprogrammed). When the system is powered back up again, the I2C registers must be reconfigured again. Using an External Clock as the Reference Input The CY22150 also accepts an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 5 on page 6. All programmable registers in the CY22150 are addressed with eight bits and contain eight bits of data. The CY22150 is a slave device with an address of 1101001 (69H). Table 2. Summary Table - CY22150 Programmable Registers Register Description 09H CLKOE control OCH DIV1SRC mux and DIV1N divider 12H Input crystal oscillator drive control 13H Input load capacitor control 40H 41H Charge pump and PB counter 42H PO counter, Q counter 44H Crosspoint switch matrix control D7 D6 D5 D4 D3 D2 D1 D0 0 0 CLK6 CLK5 LCLK4 LCLK3 LCLK2 LCLK1 DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 0 0 1 XDRV(1) XDRV(0) 0 0 0 CapLoad (7) CapLoad (6) CapLoad (5) CapLoad (4) CapLoad (3) CapLoad (2) CapLoad (1) CapLoad (0) 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3 45H CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6 46H CLKSRC1 CLKSRC0 for CLK6 for CLK6 47H DIV2SRC mux and DIV2N divider DIV2SRC Document Number: 38-07104 Rev. *M DIV2N(6) 1 1 1 1 1 1 DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Page 5 of 18 CY22150 Table 3. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings 00H - 80H 80H - C0H C0H - FFH Effective Load Capacitance (CapLoad) 6 pF to 12 pF 12 pF to 18 pF 18 pF to 30 pF Crystal Input Frequency Crystal ESR 30 60 30 60 30 60 8 to 15 MHz 00 01 01 10 01 10 15 to 20 MHz 01 10 01 10 10 10 20 to 25 MHz 01 10 10 10 10 11 25 to 30 MHz 10 10 10 11 11 N/A Table 4. Crystal Oscillator Gain Bit Locations and Values Address D7 D6 D5 D4 D3 D2 D1 D0 12H 0 0 1 XDRV(1) XDRV(0) 0 0 0 Table 5. Programmable External Reference Input Oscillator Drive Settings Reference Frequency 1 to 25 MHz 25 to 50 MHz 50 to 90 MHz 90 to 133 MHz 00 01 10 11 Drive Setting Input Load Capacitors PLL Frequency, Q Counter [42H(6..0)] Input load capacitors allow the user to set the load capacitance of the CY22150 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7 bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: CapLoad = (CL- CBRD - CCHIP)/0.09375 pF where: Qtotal = Q + 2 CL = specified load capacitance of your crystal. The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRT, this value defaults to 2 pF. Stable operation of the CY22150 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 7 on page 7. CCHIP = 6 pF. 0.09375 pF = the step resolution available due to the 8-bit register. In CyclocksRT, only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula given earlier is used to calculate a new CapLoad value and programmed into register 13H. In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22150. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 6 on page 7 for CapLoad bit locations and values. The input load capacitors are placed on the CY22150 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. Document Number: 38-07104 Rev. *M PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings. The 3 MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining seven bits of 42H are used to define the Q counter, as shown in Table 7. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Page 6 of 18 CY22150 of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. Stable operation of the CY22150 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. DIV1SRC is a single bit variable, controlled by register 0CH. The remaining seven bits of register 0CH determine the value of post divider DIV1N. PLL Post Divider Options [0CH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. DIV2SRC is a single bit variable, controlled by register 47H. The remaining seven bits of register 47H determine the value of post divider DIV2N. Register 0CH and 47H are defined in Table 8. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see "PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]"). Table 9 on page 7 summarizes the proper charge pump settings, based on Ptotal. The divider banks have four unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the two divider banks. The minimum value of DIVxN is 4. The maximum value See Table 10 on page 7 for register 40H bit locations and values. Table 6. Input Load Capacitor Register Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 13H CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) D5 D4 D3 D2 D1 D0 Table 7. P Counter and Q Counter Register Definition Address D7 D6 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) 41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) Table 8. PLL Post Divider Options Address D7 D6 D5 D4 D3 D2 D1 D0 0CH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Table 9. Charge Pump Settings Charge Pump Setting - Pump(2..0) Calculated Ptotal 000 16 - 44 001 45 - 479 010 480 - 639 011 640 - 799 100 800 - 1023 101, 110, 111 Do not use - device will be unstable Table 10. Register 40H Change Pump Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) Although using the above table guarantees stability, it is recommended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. Document Number: 38-07104 Rev. *M Page 7 of 18 CY22150 Clock Output Settings: CLKSRC - Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). CLKOE - Clock Output Enable Control [09H(5..0)] Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6). Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13 on page 8. The output swing of LCLK1 through LCLK4 is set by VDDL. The output swing of CLK5 and CLK6 is set by VDD. When DIV1N is divisible by four, then CLKSRC(0,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). Writing to any of the following registers causes the part to exhibit abnormal behavior, as follows. Test, Reserved, and Blank Registers [00H to 08H] [0AH to 0BH] [0DH to 11H] [14H to 3FH] [43H] [48H to FFH] When DIV2N is divisible by four, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by eight, then - Reserved - Reserved - Reserved - Reserved - Reserved - Reserved. Table 11. Clock Output Setting CLKSRC2 CLKSRC1 CLKSRC0 Definition and Notes 0 0 0 Reference input. 0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. 0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. 0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. 1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. 1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. 1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. 1 1 1 Reserved - do not use. Table 12. Clock Output Register Setting Address D7 D6 D5 D4 D3 D2 D1 D0 44H CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for LCLK1 LCLK1 LCLK1 LCLK2 LCLK2 LCLK2 LCLK3 LCLK3 45H CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for LCLK3 LCLK4 LCLK4 LCLK4 CLK5 CLK5 CLK5 CLK6 46H CLKSRC1 for CLKSRC0 for CLK6 CLK6 1 1 1 1 1 1 Table 13. CLKOE Bit Setting Address D7 D6 D5 D4 D3 D2 D1 D0 09H 0 0 CLK6 CLK5 LCLK4 LCLK3 LCLK2 LCLK1 Document Number: 38-07104 Rev. *M Page 8 of 18 CY22150 I2C Interface Timing The CY22150 uses a two-wire I2C-interface that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); eight-bit Memory Address (MA); ACK; eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK; eight-bit data in MA+2; ACK; and so on until STOP bit.The basic serial format is illustrated in Figure 4 on page 9. Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 3. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 5 on page 10. . Start Sequence - Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next eight-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence - Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY22150 responds with an ACK pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 6 on page 10. (N = the number of eight-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master Figure 3. Data Valid and Data Transition Periods Data valid Transition to next bit SDAT CLKHIGH tDH tSU VIH SCLK VIL CLKLOW Figure 4. Data Frame Architecture SDAT Write Multiple Contiguous Registers 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) 1-bit Slave ACK 1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master R/W = 1 ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1) 1-bit Master ACK 1-bit Slave ACK 8-bit Register Data (FFH) 1-bit Slave ACK 8-bit Register Data (00H) Start Signal SDAT Read Multiple Contiguous Registers Start Signal Document Number: 38-07104 Rev. *M 1-bit Master ACK 8-bit Register Data (FFH) 1-bit Master ACK 8-bit Register Data (00H) 1-bit Slave ACK Stop Signal 1-bit Master ACK Stop Signal Page 9 of 18 CY22150 Figure 5. Start and Stop Frame SDAT Transition to next bit START SCLK STOP Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data SDAT + START DA6 SCLK DA5DA0 + R/W ACK RA6RA1 RA0 ACK D7 + + Parameter fSCLK RA7 + Description Frequency of SCLK Start mode time from SDA LOW to SCL LOW D6 D1 D0 ACK STOP + Min Max Unit - 400 kHz 0.6 - s CLKLOW SCLK LOW period 1.3 - s CLKHIGH SCLK HIGH period 0.6 - s tSU Data transition to SCLK HIGH 100 - ns tDH Data hold (SCLK LOW to data transition) 100 - ns Rise time of SCLK and SDAT - 300 ns Fall time of SCLK and SDAT - 300 ns Stop mode time from SCLK HIGH to SDAT HIGH 0.6 - s Stop mode to Start mode 1.3 - s Document Number: 38-07104 Rev. *M Page 10 of 18 CY22150 Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deterministic. These jitter terms are usually given in terms of rms, peak to peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise is mitigated by proper power supply decoupling (0.1 F ceramic cap 0.25") of the clock and ensuring a low impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise is poor. Therefore, to improve long term jitter and phase noise, reducing Q to a minimum is advisable. This technique increases the speed of the Phase Frequency Detector which in turn drive the input voltage of the VCO. In a similar manner increasing P till the VCO is near its maximum rated speed also decreases long term jitter and phase noise. For example: Input Reference of 12 MHz; desired output frequency of 33.3 MHz. The following solution is possible: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results is Q = 2, P = 50, Post Div = 9. For more information, contact your local Cypress field applications engineer. Figure 7. Test Circuit VDD CLK out 0.1 mF C LOAD OUTPUTS AVDD VDDL 0.1 F 0.1 mF GND Figure 8. Duty Cycle Definition; DC = t2/t1 Figure 9. Rise and Fall Time Definitions t1 t3 t4 t2 80% CLK CLK 50% 50% 20% Figure 10. Peak-to-Peak Jitter t6 Document Number: 38-07104 Rev. *M Page 11 of 18 CY22150 Absolute Maximum Conditions Parameter Min Max Unit VDD Supply Voltage Description -0.5 7.0 V VDDL I/O Supply Voltage -0.5 7.0 V TS Storage Temperature[2] -65 125 C TJ Junction Temperature - 125 C Package Power Dissipation - Commercial Temp - 450 mW - 380 mW AVSS - 0.3 AVDD + 0.3 V Package Power Dissipation - Industrial Temp Digital Inputs ESD Digital Outputs Referred to VDD VSS - 0.3 VDD + 0.3 V Digital Outputs Referred to VDDL VSS - 0.3 VDDL +0.3 V - 2000 V Static Discharge Voltage per MIL-STD-833, Method 3015 Recommended Operating Conditions Parameter Description Min Typ. Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI[3] Operating Voltage 3.135 3.3 3.465 V Operating Voltage 2.375 2.5 2.625 V 0 - 70 C -40 - 85 C - - 15 pF VDDLLO [3] TAC Ambient Commercial Temp TAI Ambient Industrial Temp CLOAD Max. Load Capacitance, VDD/VDDL = 3.3 V CLOAD Max. Load Capacitance, VDDL = 2.5 V - - 15 pF fREFD Driven REF 1 - 133 MHz fREFC Crystal REF 8 - 30 MHz 0.05 - 500 ms tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) DC Electrical Characteristics Parameter[4] Name IOH3.3 Output High Current Description Min Typ. Max Unit VOH = VDD - 0.5, VDD/VDDL = 3.3 V (sink) 12 24 - mA IOL3.3 Output Low Current VOL = 0.5, VDD/VDDL = 3.3 V (source) 12 24 - mA IOH2.5 Output High Current VOH = VDDL - 0.5, VDDL = 2.5 V (source) 8 16 - mA IOL2.5 Output Low Current VOL = 0.5, VDDL = 2.5 V (sink) 8 16 - mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 - - VDD VIL Input Low Voltage CMOS levels, 30% of VDD - - 0.3 VDD CIN Input Capacitance SCLK and SDAT Pins - - 7 pF IIZ Input Leakage Current SCLK and SDAT Pins - 5 - A VHYS Hysteresis of Schmitt triggered inputs SCLK and SDAT Pins 0.05 - - VDD IVDD[5,6] Supply Current AVDD/VDD Current - 45 - [5,6] Supply Current VDDL Current (VDDL = 3.465 V) - 25 - IVDDL3.3 Supply Current VDDL Current (VDDL = 2.625 V) - 17 - IVDDL2.5[5,6] Notes 2. Rated for 10 years. 3. VDDLis only specified and characterized at 3.3 V 5% and 2.5 V 5%. VDDLmay be powered at any value between 3.465 V and 2.375 V. 4. Not 100% tested. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. Document Number: 38-07104 Rev. *M mA mA mA Page 12 of 18 CY22150 AC Electrical Characteristics Parameter[7] Min Typ. Max Unit Output Frequency, Commercial Temp Clock output limit, 3.3 V 0.08 (80 kHz) - 200 MHz Clock output limit, 2.5 V 0.08 (80 kHz) - 166.6 MHz Output Frequency, Industrial Temp Clock output limit, 3.3 V 0.08 (80 kHz) - 166.6 MHz Clock output limit, 2.5 V 0.08 (80 kHz) - 150 MHz t2LO Output Duty Cycle Duty cycle is defined in Figure 8 on page 11; t1/t2 fOUT < 166 MHz, 50% of VDD 45 50 55 % t2HI Output Duty Cycle Duty cycle is defined in Figure 8; t1/t2 fOUT > 166 MHz, 50% of VDD 40 50 60 % t3LO Rising Edge Slew Rate (VDDL = 2.5 V) Output clock rise time, 20% to 80% of VDDL. Defined in Figure 9 0.6 1.2 - V/ns t4LO Falling Edge Slew Rate (VDDL = 2.5 V) Output dlock fall time, 80% to 20% of VDDL. Defined in Figure 9 0.6 1.2 - V/ns t3HI Rising Edge Slew Rate (VDDL = 3.3 V) Output dlock rise time, 20% to 80% of VDD/VDDL. Defined in Figure 9 0.8 1.4 - V/ns t4HI Falling Edge Slew Rate (VDDL = 3.3 V) Output dlock fall time, 80% to 20% of VDD/VDDL. Defined in Figure 9 0.8 1.4 - V/ns t5[8] Skew Output-output skew between related outputs - - 250 ps t6[9] Clock Jitter Peak-to-peak period jitter - 250 - ps t10 PLL Lock Time - 0.30 3 ms t1 Name Description Device Characteristics Parameter JA Complexity Name Theta JA Transistor Count Value 115 74,600 Unit C/W Transistors 7. Not 100% tested, guaranteed by design. 8. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram on page 1 for more information. 9. Jitter measurements vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL, (2.5 V or 3.3 V jitter). Document Number: 38-07104 Rev. *M Page 13 of 18 CY22150 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY22150KFZXC 16-Pin TSSOP Commercial (0 to 70 C) 3.3 V CY22150KFZXCT 16-Pin TSSOP - Tape and Reel Commercial (0 to 70 C) 3.3 V CY22150KFZXI 16-Pin TSSOP Industrial (-40 to 85 C) 3.3 V CY22150KFZXIT 16-Pin TSSOP - Tape and Reel Industrial (-40 to 85 C) 3.3 V Pb-Free Programmer CY3672-USB Programmer with USB interface CY3695 CY22150 Adapter Socket for CY3672-USB Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information. Possible Configurations Ordering Code Package Type Operating Range CY22150KZXC-xxx[10] 16-Pin TSSOP Commercial (0 to 70 C) Operating Voltage 3.3 V CY22150KZXC-xxxT[10] 16-Pin TSSOP - Tape and Reel Commercial (0 to 70 C) 3.3 V CY22150KZXI-xxx[10] 16-Pin TSSOP Industrial (-40 to 85 C) 3.3 V CY22150KZXI-xxxT[10] 16-Pin TSSOP - Tape and Reel Industrial (-40 to 85 C) 3.3 V Notes 10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document Number: 38-07104 Rev. *M Page 14 of 18 CY22150 Ordering Code Definitions Package Diagram Figure 11. 16-Pin TSSOP 4.40 mm Body Z16.173 51-85091 *D Document Number: 38-07104 Rev. *M Page 15 of 18 CY22150 Acronyms Table 14. Acronyms Used in this Documnent Acronym ACK BSC CLKOE CMOS DA ESD ESR FAE I/O I2C JEDEC Description acknowledge basic spacing between centers clock output enable complementary metal oxide semiconductor device address electrostatic discharge equivalent series resistance field applications engineer input / output inter integrated circuit joint electron device engineering council Acronym LSB MA MSB PFD PLL SCLK SDAT TSSOP USB VCO Description least significant bit memory address most significant bit phase frequency detector phase locked loop serial interface clock serial interface data thin shrunk small outline package universal serial bus voltage-controlled oscillator Symbol Vrms W mA mm ms mV nA ns nV pA pF pp ppm ps sps Unit of Measure microvolts root-mean-square microwatt milliampere millimeter millisecond millivolt nano ampere nanosecond nano volt ohm pico ampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation Document Conventions Units of Measure Table 15. Units of Measure Symbol C dB dBc/Hz fC fF Hz KB Kbit kHz k MHz M A F H s V Unit of Measure degrees Celsius decibels decibels relative to the carrier per Hertz femto Coulomb femto Farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad micro henry microsecond microvolt Document Number: 38-07104 Rev. *M Page 16 of 18 CY22150 Document History Page Document Title: CY22150 One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator Document Number: 38-07104 Revision ECN Orig. of Change Submission Description of Change Date ** 107498 CKN 08/08/01 New Data Sheet *A 110043 CKN 02/06/02 Preliminary to Final *B 113514 CKN 05/01/02 Removed overline on Figure 6 Register Address Register Data Changed CLKHIGH unit from ns to s in parameter description table Added (sink) to rows 1 and 4 and added (source) to rows 2 and 3 in the DC Electrical Characteristics table (Figure ) *C 121868 RBI 12/14/02 Power up requirements added to Operating Conditions Information *D 125453 CKN 05/19/03 Changed 0 to 1 under 12H/D5 of Table 2 and Table 4. Reworded and reformatted Programmable Crystal Input Oscillator Gain Settings text. *E 242808 RGL See ECN Minor Change: Fixed the broken line in the block diagram *F 252352 RGL See ECN Corrected Table 2 specs. *G 296084 RGL See ECN Added Pb-Free Devices *H 2440846 AESA See ECN Updated template. Added Note "Not recommended for new designs." Added part number CY22150KFC, CY22150KFCT, CY22150KFI, CY22150KFZXC, CY22150KFZXCT, CY22150KFZXI, CY22150KFZXIT, CY22150KZXI-xxxT, and CY22150KZI-xxxT in ordering information table. Replaced Lead Free with Pb-Free. *I 2649578 KVM/PYRS 01/29/09 Removed reference to note "Not recommended for new designs" for the following parts: CY22150KFC, CY22150KFCT, CY22150KFI Added CY22150KZI-xxx to the Ordering Information Table Removed CY22150ZC-xxx, CY22150ZC-xxxT and CY22150ZI-xxx from the Ordering Information Table Changed CY3672 to CY3672-USB, and moved to the bottom of the table *J 2900690 KVM 03/29/2010 Changed title from "One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator" to "One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator" Updated table on page 1. Changed references to Serial Programming Interface (SPI) to I2C Interface in Features and Logic Block Diagram. Removed inactive parts from Ordering Information. Added Possible Configurations table for "xxx" parts. *K 3210225 CXQ 03/30/2011 Changed tDH min spec from 0 ns to 100 ns. Updated package diagram. Added ordering code definitions, Acronyms and units of measure. *L 3402048 AJU 10/11/2011 Removed the pruned part CY22150KFI from the Ordering Information table. *M 3846671 PURU 12/19/2012 Updated Ordering Information: Removed all Non-K Devices and added K Devices in Possible Configurations. Document Number: 38-07104 Rev. *M Page 17 of 18 CY22150 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07104 Rev. *M Revised December 19, 2012 Page 18 of 18 BP Microsystems is a trademark of BP Microsystems. HiLo Systems is a trademark of Hi-Lo Systems, Inc. CyClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.