LM5085QMYNOPB - NATIONAL SEMICONDUCTOR

LM5085

LM5085 75V Constant On-Time PFET Buck Switching Controller

Literature Number: SNVS565D

LM5085

December 17, 2009

75V Constant On-Time PFET Buck Switching Controller

General Description

The LM5085 is a high efficiency PFET switching regulator

controller that can be used to quickly and easily develop a

small, efficient buck regulator for a wide range of applications.

This high voltage controller contains a PFET gate driver and

a high voltage bias regulator which operates over a wide 4.5V

to 75V input range. The constant on-time regulation principle

requires no loop compensation, simplifies circuit implemen-

tation, and results in ultra-fast load transient response. The

operating frequency remains nearly constant with line and

load variations due to the inverse relationship between the

input voltage and the on-time. The PFET architecture allows

100% duty cycle operation for a low dropout voltage. Either

the RDS(ON) of the PFET or an external sense resistor can be

used to sense current for over-current detection.

Features

■LM5085Q is an Automotive Grade product that is AEC-

Q100 grade 1 qualified (-40°C to 125°C operating junction

temperature)

■Wide 4.5V to 75V input voltage range

■Adjustable current limit using RDS(ON) or a current sense

resistor

■Programmable switching frequency to 1MHz

■No loop compensation required

■Ultra-Fast transient response

■Nearly constant operating frequency with line and load

variations

■Adjustable output voltage from 1.25V

■Precision ±2% feedback reference

■Capable of 100% duty cycle operation

■Internal soft-start timer

■Integrated high voltage bias regulator

■Thermal shutdown

Package

■MSOP-8EP

■MSOP-8

■LLP-8 (3 mm x 3 mm)

Typical Application, Basic Step Down Controller

30057701

LM5085 75V Constant On-Time PFET Buck Switching Controller

Connection Diagrams

30057702

Top View

8-Lead MSOP-EP

30057703

Top View

8-Lead MSOP

30057704

Top View

8-Lead LLP

Ordering Information

Order Number Package

Type

NSC Package

Drawing

Junction

Temperature Range

Supplied As Feature

LM5085QMYE MSOP-8EP MUY08A

-40°C to +125°C

250 units on tape and reel AEC-Q100 Grade 1

qualified. Automotive

Grade Production Flow*

LM5085QMY MSOP-8EP MUY08A 1000 units on tape and reel

LM5085QMYX MSOP-8EP MUY08A 3500 units on tape and reel

LM5085MYE MSOP-8EP MUY08A

-40°C to +125°C

250 units on tape and reel

LM5085MY MSOP-8EP MUY08A 1000 units on tape and reel

LM5085MYX MSOP-8EP MUY08A 3500 units on tape and reel

LM5085MME MSOP-8 MUA08A 250 units on tape and reel

LM5085MM MSOP-8 MUA08A 1000 units on tape and reel

LM5085MMX MSOP-8 MUA08A 3500 units on tape and reel

LM5085SDE LLP-8 SDA08A 250 units on tape and reel

LM5085SD LLP-8 SDA08A 1000 units on tape and reel

LM5085SDX LLP-8 SDA08A 4500 units on tape and reel

*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.

Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified

with the letter Q. For more information go to http://www.national.com/automotive.

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LM5085

Pin Descriptions

No.

Name Description Application Information

1 ADJ Current Limit Adjust The current limit threshold is set by an external resistor from VIN to ADJ in

conjunction with the external sense resistor or the PFET’s RDS(ON).

2 RT On-time control and shutdown An external resistor from VIN to RT sets the buck switch on-time and switching

frequency. Grounding this pin shuts down the controller.

3 FB Voltage Feedback from the

regulated output

Input to the regulation and over-voltage comparators. The regulation level is

1.25V.

4 GND Circuit Ground Ground reference for all internal circuitry

5 ISEN Current sense input for current

limit detection.

Connect to the PFET drain when using RDS(ON) current sense. Connect to the

PFET source and the sense resistor when using a current sense resistor.

6 PGATE Gate Driver Output Connect to the gate of the external PFET.

7 VCC Output of the gate driver bias

regulator

Output of the negative voltage regulator (relative to VIN) that biases the PFET

gate driver. A low ESR capacitor is required from VIN to VCC, located as close

as possible to the pins.

8 VIN Input supply voltage The operating input range is from 4.5V to 75V. A low ESR bypass capacitor must

be located as close as possible to the VIN and GND pins.

EP Exposed Pad Exposed pad on the underside of the package (MSOP-8EP and LLP only). This

pad is to be soldered to the PC board ground plane to aid in heat dissipation.

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LM5085

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN to GND -0.3V to 76V

ISEN to GND -0.3V to VIN + 0.3V

ADJ to GND -0.3V to VIN + 0.3V

RT, FB to GND -0.3V to 7V

VIN to VCC, VIN to PGATE -0.3V to 10V

ESD Rating (Note 2)

Human Body Model 2kV

Storage Temperature Range -65°C to +150°C

Operating Ratings (Note 1)

VIN Voltage 4.5V to 75V

Junction Temperature −40°C to + 125°C

Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the

junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.

Unless otherwise stated the following conditions apply: VIN = 48V, RT = 100 kΩ.

Symbol Parameter Conditions Min Typ Max Units

VIN Pin

IIN Operating current Non-switching, FB = 1.4V (Note 6) 1.3 1.8 mA

IQShutdown current RT = 0V (Note 6) 200 345 µA

VCC Regulator (Note 3)

VCC(reg) VIN - VCC Vin = 9V, FB = 1.4V, ICC = 0 mA 6.9 7.7 8.5 V

Vin = 9V, FB = 1.4V, ICC = 20 mA 7.7 V

Vin = 75V, FB = 1.4V, ICC = 0 mA 7.7 V

UVLOVcc VCC under-voltage lock-out threshold VCC increasing 3.8 V

UVLOVcc hysteresis VCC decreasing 260 mV

VCC(CL) VCC Current Limit FB = 1.4V 20 40 mA

PGATE Pin

VPGATE(HI) PGATE High voltage PGATE Pin = Open VIN -0.1 VIN V

VPGATE(LO) PGATE Low voltage PGATE Pin = Open VCC VCC

+0.1

VPGATE(HI)4.5 PGATE High Voltage at Vin = 4.5V PGATE Pin = Open VIN -0.1 VIN V

VPGATE(LO)4.5 PGATE Low Voltage at Vin = 4.5V PGATE Pin = Open VCC VCC

+0.1

IPGATE Driver Output Source Current VIN = 12V, PGATE = VIN - 3.5V 1.75 A

Driver Output Sink Current VIN = 12V, PGATE = VIN - 3.5V 1.5 A

RPGATE Driver Output Resistance Source current = 500 mA 2.3 Ω

Sink current = 500 mA 2.3 Ω

Current Limit Detection

IADJ ADJUST pin current source VADJ = 46.5V 32 40 48 µA

VCL OFFSET Current limit comparator offset VADJ = 46.5V, VADJ - VISEN -9 09mV

RT Pin

RTSD Shutdown threshold RT Pin voltage rising 0.73 V

RTHYS Shutdown threshold hysteresis 50 mV

On-Time

tON – 1 On-time VIN = 4.5V, RT = 100 kΩ3.5 57.15 µs

tON – 2 VIN = 48V, RT = 100 kΩ276 360 435 ns

tON - 3 VIN = 75V, RT = 100 kΩ177 235 285 ns

tON - 4 Minimum on-time in current limit (Note 7) VIN = 48V, 25 mV overdrive at ISEN 55 140 235 ns

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LM5085

Symbol Parameter Conditions Min Typ Max Units

Off-Time

tOFF(CL1)

Off-time (current limit) (Note 7)

VIN = 12V, VFB = 0V 5.35 7.9 10.84 µs

tOFF(CL2) VIN = 12V, VFB = 1V 1.42 1.9 3.03 µs

tOFF(CL3) VIN = 48V, VFB = 0V 16 24 32.4 µs

tOFF(CL4) VIN = 48V, VFB = 1V 3.89 5.7 8.67 µs

Regulation and Over-Voltage Comparators (FB Pin)

VREF FB regulation threshold 1.225 1.25 1.275 V

VOV FB over-voltage threshold Measured with respect to VREF 350 mV

IFB FB bias current 10 nA

Soft-Start Function

tSS Soft-start time 1.4 2.5 4.3 ms

Thermal Shutdown

TSD Junction shutdown temperature Junction temperature rising 170 °C

THYS Junction shutdown hysteresis 20 °C

Thermal Resistance

θJA Junction to ambient, 0 LFPM air flow (Note

MSOP-8 package 126 °C/W

MSOP-8EP package 46

LLP-8 package 54

θJC Junction to case, 0 LFPM air flow (Note 5) MSOP-8 package 29 °C/W

MSOP-8EP package 5.5

LLP-8 package 9.1

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 3: VCC provides self bias for the internal gate drive.

Note 4: For detailed information on soldering plastic MSOP and LLP packages refer to the Packaging Data Book available from National Semiconductor

Corporation.

Note 5: Tested on a 4 layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7.

Note 6: Operating current and shutdown current do not include the current in the RT resistor.

Note 7: The tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through (tOFF(CL4)) track each other over process and temperature

variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its range.

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LM5085

Typical Performance Characteristics

Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V.

Efficiency (Circuit of Figure 4)

30057705

Input Operating Current vs. VIN

30057706

Shutdown Current vs. VIN

30057707

VCC vs. VIN

30057708

VCC vs. ICC

30057709

On-Time vs. RT and VIN

30057711

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LM5085

Off-Time vs. VIN and VFB

30057712

Voltage at the RT Pin

30057713

ADJ Pin Current vs. VIN

30057717

Input Operating Current vs. Temperature

30057718

Shutdown Current vs. Temperature

30057753

VCC vs. Temperature

30057754

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LM5085

On-Time vs. Temperature

30057755

Minimum On-Time vs. Temperature

30057756

Off-Time vs. Temperature

30057757

Current Limit Comparator Offset vs. Temperature

30057758

ADJ Pin Current vs. Temperature

30057714

PGATE Driver Output Resistance vs. Temperature

30057759

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LM5085

Feedback Reference Voltage vs. Temperature

30057715

Soft-Start Time vs. Temperature

30057716

RT Pin Shutdown Threshold vs. Temperature

30057760

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LM5085

Block Diagram

30057719

Sense resistor method shown for current limit detection.

Minimum output ripple configuration shown.

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LM5085

Functional Description

OVERVIEW

The LM5085 is a PFET buck (step-down) DC-DC controller

using the constant on-time (COT) control principle. The input

operating voltage range of the LM5085 is 4.5V to 75V. The

use of a PFET in a buck regulator greatly simplifies the gate

drive requirements and allows for 100% duty cycle operation

to extend the regulation range when operating at low input

voltage. However, PFET transistors typically have higher on-

resistance and gate charge when compared to similarly rated

NFET transistors. Consideration of available PFETs, input

voltage range, gate drive capability of the LM5085, and ther-

mal resistances indicate an upper limit of 10A for the load

current for LM5085 applications. Constant on-time control is

implemented using an on-time one-shot that is triggered by

the feedback signal. During the off-time, when the PFET (Q1)

is off, the load current is supplied by the inductor and the out-

put capacitor. As the output voltage falls, the voltage at the

feedback comparator input (FB) falls below the regulation

threshold. When this occurs Q1 is turned on for the one-shot

period which is determined by the input voltage (VIN) and the

RT resistor. During the on-time the increasing inductor current

increases the voltage at FB above the feedback comparator

threshold. For a buck regulator the basic relationship between

the on-time, off-time, input voltage and output voltage is:

(1)

where Fs is the switching frequency. Equation 1 is valid only

in continuous conduction mode (inductor current does not

reach zero). Since the LM5085 controls the on-time inversely

proportional to VIN, the switching frequency remains relatively

constant as VIN is varied. If the input voltage falls to a level

that is equal to or less than the regulated output voltage Q1

is held on continuously (100% duty cycle) and VOUT is ap-

proximately equal to VIN.

The COT control scheme, with the feedback signal applied to

a comparator rather than an error amplifier, requires no loop

compensation, resulting in very fast load transient response.

The LM5085 is available in both an 8 pin MSOP package and

an 8 pin LLP package with an exposed pad to aid in heat dis-

sipation. An 8 pin MSOP package without an exposed pad is

also available.

REGULATION CONTROL CIRCUIT

The LM5085 buck DC-DC controller employs a control

scheme based on a comparator and a one-shot on-timer, with

the output voltage feedback compared to an internal refer-

ence voltage (1.25V). When the FB pin voltage falls below the

feedback reference, Q1 is switched on for a time period de-

termined by the input voltage and a programming resistor

(RT). Following the on-time Q1 remains off until the FB voltage

falls below the reference. Q1 is then switched on for another

on-time period. The output voltage is set by the feedback re-

sistors (RFB1, RFB2 in the Block Diagram). The regulated

output voltage is calculated as follows:

VOUT = 1.25V x (RFB2+ RFB1)/ RFB1 (2)

The feedback voltage supplied to the FB pin is applied to a

comparator rather than a linear amplifier. For proper opera-

tion sufficient ripple amplitude is necessary at the FB pin to

switch the comparator at regular intervals with minimum delay

and noise susceptibility. This ripple is normally obtained from

the output voltage ripple attenuated through the feedback re-

sistors. The output voltage ripple is a result of the inductor’s

ripple current passing through the output capacitor’s ESR, or

through a resistor in series with the output capacitor. Multiple

methods are available to ensure sufficient ripple is supplied

to the FB pin, and three different configurations are discussed

in the Applications Information section.

When in regulation, the LM5085 operates in continuous con-

duction mode at medium to heavy load currents and discon-

tinuous conduction mode at light load currents. In continuous

conduction mode the inductor’s current is always greater than

zero, and the operating frequency remains relatively constant

with load and line variations. The minimum load current for

continuous conduction mode is one-half the inductor’s ripple

current amplitude. In discontinuous conduction mode, where

the inductor’s current reaches zero during the off-time, the

operating frequency is lower than in continuous conduction

mode and varies with load current. Conversion efficiency is

maintained at light loads since the switching losses are re-

duced with the reduction in load and frequency.

If the voltage at the FB pin exceeds 1.6V due to a transient

overshoot or excessive ripple at VOUT the internal over-volt-

age comparator immediately switches off Q1. The next on-

time period starts when the voltage at FB falls below the

feedback reference voltage.

ON-TIME TIMER

The on-time of the PFET gate drive output (PGATE pin) is

determined by the resistor (RT) and the input voltage (VIN),

and is calculated from:

(3)

where RT is in kΩ.

The minimum on-time, which occurs at maximum VIN, should

not be set less than 150 ns (see Current Limiting section). The

buck regulator effective on-time, measured at the SW node

(junction of Q1, L1, and D1) is typically longer than that cal-

culated in Equation 3 due to the asymmetric delay of the

PFET. The on-time difference caused by the PFET switching

delay can be estimated as the difference of the turn-off and

turn-on delays listed in the PFET data sheet. Measuring the

difference between the on-time at the PGATE pin versus the

SW node in the actual application circuit is also recommend-

ed.

In continuous conduction mode, the inverse relationship of

tON with VIN results in a nearly constant switching frequency

as VIN is varied. The operating frequency can be calculated

from:

(4)

where RT is in kΩ, and tD is equal to 50 ns plus the PFET’s

delay difference. To set a specific continuous conduction

mode switching frequency (FS), the RT resistor is determined

from the following:

(5)

where RT is in kΩ. A simplified version of Equation 5 at VIN =

12V, and tD = 100 ns, is:

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LM5085

For VIN = 48V and tD = 100 ns, the simplified equation is:

SHUTDOWN

The LM5085 can be shutdown by grounding the RT pin (see

Figure 1). In this mode the PFET is held off, and the VCC

regulator is disabled. The internal operating current is re-

duced to the value shown in the graph “Shutdown current vs.

VIN”. The shutdown threshold at the RT pin is ≊0.73V, with

≊50 mV of hysteresis. Releasing the pin enables normal op-

eration. The RT pin must not be forced high during normal

operation.

30057724

FIGURE 1. Shutdown Implementation

CURRENT LIMITING

The LM5085 current limiting operates by sensing the voltage

across either the RDS(ON) of Q1, or a sense resistor, during the

on-time and comparing it to the voltage across the resistor

RADJ (see Figure 2). The current limit function is much more

accurate and stable over temperature when a sense resistor

is used. The RDS(ON) of a MOSFET has a wide process vari-

ation and a large temperature coefficient.

If the voltage across RDS(ON) of Q1, or the sense resistor, is

greater than the voltage across RADJ, the current limit com-

parator switches to turn off Q1. Current sensing is disabled

for a blanking time of ≊100 ns at the beginning of the on-time

to prevent false triggering of the current limit comparator due

to leading edge current spikes. Because of the blanking time

and the turn-on and turn-off delays created by the PFET, the

on-time at the PGATE pin should not be set less than 150 ns.

An on-time shorter than that may prevent the current limit de-

tection circuit from properly detecting an over-current condi-

tion. The duration of the subsequent forced off-time is a

function of the input voltage and the voltage at the FB pin, as

shown in the graph “Off-time vs. VIN and VFB”. The longer-

than-normal forced off-time allows the inductor current to

decrease to a low level before the next on-time. This cycle-

by-cycle monitoring, followed by a forced off-time, provides

effective protection from output load faults over a wide range

of operating conditions.

The voltage across the RADJ resistor is set by an internal 40

µA current sink at the ADJ pin. When using Q1’s RDS(ON) for

sensing, the current at which the current limit comparator

switches is calculated from:

ICL = 40 µA x RADJ/RDS(ON) (6)

When using a sense resistor (RSEN) the threshold of the cur-

rent limit comparator is calculated from:

ICL = 40 µA x RADJ/RSEN (7)

When using equation 6 or 7, the tolerances for the ADJ pin

current sink and the offset of the current limit comparator

should be included to ensure the resulting minimum current

limit is not less than the required maximum switch current.

Simultaneously increasing the values of RADJ and RSEN de-

creases the effects of the current limit comparator offset, but

at the expense of higher power dissipation. When using a

sense resistor, the RSEN resistor value should be chosen with-

in the practical limitations of power dissipation and physical

size. For example, for a 10A current limit, setting RSEN =

0.005Ω results in a power dissipation as high as 0.5W. Cur-

rent sense connections to the RSEN resistor, or to Q1, must

be Kelvin connections to ensure accuracy.

The CADJ capacitor filters noise from the ADJ pin, and helps

prevent unintended switching of the current limit comparator

due to input voltage transients. The recommended value for

CADJ is 1000 pF.

CURRENT LIMIT OFF-TIME

When the current through Q1 exceeds the current limit thresh-

old, the LM5085 forces an off-time longer than the normal off-

time defined by Equation 1. See the graph “Off-Time vs. VIN

and VFB”, or calculate the current limit off-time from the fol-

lowing equation:

(8)

where VIN is the input voltage, and VFB is the voltage at the

FB pin at the time current limit was detected. This feature is

necessary to allow the inductor current to decrease sufficient-

ly to offset the current increase which occurred during the on-

time. During the on-time, the inductor current increases an

amount equal to:

(9)

During the off-time the inductor current decreases due to the

reverse voltage applied across the inductor by the output volt-

age, the freewheeling diode’s forward voltage (VFD), and the

voltage drop due to the inductor’s series resistance (VESR).

The current decrease is equal to:

(10)

The on-time in Equation 9 is shorter than the normal on-time

since the PFET is shut off when the current limit threshold is

crossed. If the off-time is not long enough, such that the cur-

rent decrease (Equation 10) is less than the current increase

(Equation 9), the current levels are higher at the start of the

next on-time. This results in a further decrease in on-time,

since the current limit threshold is crossed sooner. A balance

is reached when the current changes in Equations 9 and 10

are equal. The worst case situation is that of a direct short

circuit at the output terminals, where VOUT = 0 volts, as that

results in the largest current increase during the on-time, and

the smallest decrease during the off-time. The sum of the

diode’s forward voltage and the inductor’s ESR voltage must

be sufficient to ensure current runaway does not occur. Using

Equations 9 and 10, this requirement can be stated as:

(11)

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LM5085

For tON in Equation 11 use the minimum on-time at the SW

node. To determine this time period add the “Minimum on-

time in current limit” specified in the Electrical Characteristics

(tON-4) to the difference of the turn-off and turn-on delays of

the PFET. For tOFF use the value in the graph “Off-Time vs.

VIN and VFB”, or use Equation 8, where VFB is equal to zero

volts. When using the minimum or maximum limits of those

specifications to determine worst case situations, the toler-

ance of the minimum on-time (tON-4) and the current limit off-

times (tOFF(CL1) through tOFF(CL4)) track each other over the

process and temperature variations. A device which has an

on-time at the high end of the range will have an off-time that

is at the high end of its range.

30057725

FIGURE 2. Current Limit Sensing

VCC REGULATOR

The VCC regulator provides a regulated voltage between the

VIN and the VCC pins to provide the bias and gate current for

the PFET gate driver. The 0.47 µF capacitor at the VCC pin

must be a low ESR capacitor, preferably ceramic as it pro-

vides the high surge current for the PFET’s gate at each turn-

on. The capacitor must be located as close as possible to the

VIN and VCC pins to minimize inductance in the PC board

traces.

Referring to the graph “VCC vs. VIN”, the voltage across the

VCC regulator (VIN – VCC) is equal to VIN until VIN reaches

approximately 8.5V. At higher values of VIN, the voltage at

the VCC pin is regulated at approximately 7.7V below VIN.

The VCC regulator has a maximum current capability of at

least 20 mA. The regulator is disabled when the LM5085 is

shutdown using the RT pin, or when the thermal shutdown is

activated.

PGATE DRIVER OUTPUT

The PGATE pin output swings between VIN (Q1 off) and the

VCC pin voltage (Q1 on). The rise and fall times depend on

the PFET gate capacitance and the source and sink currents

provided by the internal gate driver. See the Electrical Chara-

teristics for the current capability of the driver.

P-CHANNEL MOSFET SELECTION

The PFET must be rated for the maximum input voltage, with

some margin above that to allow for transients and ringing

which can occur on the supply line and the switching node.

The gate-to-source voltage (VGS) normally provided to the

PFET is 7.7 volts for VIN greater than 8.5V. However, if the

circuit is to be operated at lower values of VIN, the selected

PFET must be able to fully turn-on with a VGS voltage equal

to VIN. The minimum input operating voltage for the LM5085

is 4.5V.

Similar to NFETs, the case or exposed thermal pad for a

PFET is electrically connected to the drain terminal. When

designing a PFET buck regulator the drain terminal is con-

nected to the switching node. This situation requires a trade-

off between thermal and EMI performance since increasing

the PC board area of the switching node to aid the PFET

power dissipation also increases radiated noise, possibly dis-

rupting the circuit operation. Typically the switching node area

is kept to a reasonable minimum and the PFET peak current

is derated to stay within the recommended temperature rating

of the PFET. The RDS(ON) of the PFET determines a portion

of the power dissipation in the PFET. However, PFETs with

very low RDS(ON) usually have large values of gate charge. A

PFET with a higher gate charge has a corresponding slower

switching speed, leading to higher switching losses and af-

fecting the PFET power dissipation.

If the PFET RDS(ON) is used for current limit detection, note

that it typically has a positive temperature coefficient. At 100°

C the RDS(ON) may be as much as 50% higher than the value

at 25°C which could result in incorrect current limiting if not

accounted for when determining the value of the RADJ resistor.

The PFET Total Gate Charge determines most of the power

dissipation in the LM5085 due to the repetitive charge and

discharge of the PFET’s gate capacitance by the gate driver

(powered from the VCC regulator). The LM5085’s internal

power dissipation can be calculated from the following:

PDISS = VIN x ((QG x FS) + IIN) (12)

where QG is the PFET's Total Gate Charge obtained from its

datasheet, FS is the switching frequency, and IIN is the

LM5085's operating current obtained from the graph "Input

Operating Current vs. VIN". Using the Thermal Resistance

specifications in the Electrical Characteristics table, the ap-

proximate junction temperature can be determined. If the

calculated junction temperature is near the maximum oper-

ating temperature of 125°C, either the switching frequency

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LM5085

must be reduced, or a PFET with a smaller Total Gate Charge

must be used.

SOFT-START

The internal soft-start feature of the LM5085 allows the reg-

ulator to gradually reach a steady state operating point at

power up, thereby reducing startup stresses and current

surges. Upon turn-on, when Vcc reaches its under-voltage

lockout threshold, the internal soft-start circuit ramps the feed-

back reference voltage from 0V to 1.25V, causing VOUT to

ramp up in a proportional manner. The soft-start ramp time is

typically 2.5 ms.

In addition to controlling the initial power up cycle, the soft-

start circuit also activates when the LM5085 is enabled by

releasing the RT pin, and when the circuit is shutdown and

restarted by the internal Thermal Shutdown circuit.

If the voltage at FB is below the regulation threshold value

due to an over-current condition or a short circuit at Vout, the

internal reference voltage provided by the soft-start circuit to

the regulation comparator is reduced along with FB. When the

over-current or short circuit condition is removed, VOUT re-

turns to the regulated value at a rate determined by the soft-

start ramp. This feature helps prevent the output voltage from

over-shooting following an overload event.

THERMAL SHUTDOWN

The LM5085 should be operated such that the junction tem-

perature does not exceed 125°C. If the junction temperature

increases above that, an internal Thermal Shutdown circuit

activates at 170°C (typical) to disable the VCC regulator and

the gate driver, and discharge the soft-start capacitor. This

feature helps prevent catastrophic failures from accidental

device overheating. When the junction temperature falls be-

low 150°C (typical hysteresis = 20°C), the gate driver is

enabled, the soft-start circuit is released, and normal opera-

tion resumes.

Applications Information

EXTERNAL COMPONENTS

The procedure for calculating the external components is il-

lustrated with the following design example. Referring to the

Block Diagram, the circuit is to be configured for the following

specifications:

VOUT = 5V

VIN = 7V to 55V, 12V nominal

Maximum load current (IOUT(max)) = 5A

Minimum load current (IOUT(min)) = 600 mA (for continuous

conduction mode)

Switching Frequency (FSW) = 300 kHz

Maximum allowable output ripple (VOS) = 5 mVp-p

Selected PFET: Vishay Si7465

RFB1 and RFB2: These resistors set the output voltage. The

ratio of these resistors is calculated from:

RFB2/RFB1 = (VOUT/1.25V) - 1

For this example, RFB2/RFB1 = 3. Typically, RFB1 and RFB2

should be chosen from standard value resistors in the range

of 1 kΩ to 20 kΩ which satisfy the above ratio. For this ex-

ample, RFB2 = 10 kΩ, and RFB1 = 3.4 kΩ.

RT, PFET: Before selecting the RT resistor, the PFET must be

selected as its turn-on and turn-off delays affect the calculated

value of RT. For the Vishay Si7465 PFET, the difference of its

typical turn-off and turn-on delays is 57 ns. Using equation 5

at nominal input voltage, RT calculates to be:

A standard value 90.9 kΩ resistor is selected. Using equation

3 the minimum on-time at the PGATE pin, which occurs at

maximum input voltage (55V), is calculated to be 300 ns. This

minimum one-shot period is sufficiently longer than the mini-

mum recommended value of 150 ns. The minimum on-time

at the SW node is longer due to the delay added by the PFET

(57 ns). Therefore the minimum SW node on-time is 357 ns

at 55V. At the SW node the maximum on-time is calculated

to be 2.55 µs at 7V.

L1: The main parameter controlled by the inductor value is

the current ripple amplitude (IOR). See Figure 3. The minimum

load current for continuous conduction mode is used to de-

termine the maximum allowable ripple such that the inductor

current’s lower peak does not fall below 0 mA. Continuous

conduction mode operation at minimum load current is not a

requirement of the LM5085, but serves as a guideline for se-

lecting L1. For this example, the maximum ripple current is:

IOR(max) = 2 x IOUT(min) = 1.2 Amp (13)

If an application’s minimum load current is zero, a good initial

estimate for the maximum ripple current (IOR(max)) is 20% of

the maximum load current. The ripple calculated in equation

13 is then used in the following equation to calculate L1:

(14)

A standard value 15 µH inductor is selected. Using this in-

ductance value, the maximum ripple current amplitude, which

occurs at maximum input voltage, calculates to 1.19 Ap-p.

The peak current (IPK) at maximum load current is 5.6A. How-

ever, the current rating of the selected inductor must be based

on the maximum current limit value calculated below.

30057732

FIGURE 3. Inductor Current Waveform

RSEN, RADJ: To achieve good current limit accuracy and avoid

over designing the power stage components, the sense re-

sistor method is used for current limiting in this example. A

standard value 10 mΩ resistor is selected for RSEN, resulting

in a 50 mV drop at maximum load current, and a maximum

0.25W power dissipation in the resistor. Since the LM5085

uses peak current detection, the minimum value for the cur-

rent limit threshold must be equal to the maximum load cur-

rent (5A) plus half the maximum ripple amplitude calculated

above:

ICL(min) = 5A + 1.19A/2 = 5.6A

At this current level the voltage across RSEN is 56 mV. Adding

the current limit comparator offset of 9 mV (max) increases

the required current limit threshold to 6.5A. Using equation 7

www.national.com 14

LM5085

with the minimum value for the ADJ pin current (32 µA), the

required RADJ resistor calculates to:

A standard value 2.1 kΩ resistor is selected. The nominal

current limit threshold calculates to:

Using the tolerances for the ADJ pin current and the current

limit comparator offset, the maximum current limit threshold

calculates to:

The minimum current limit thresholds calculate to:

The load current in each case is equal to the current limit

threshold minus half the current ripple amplitude. The recom-

mended value of 1000 pF for CADJ is used in this example.

COUT: Since the maximum allowed output ripple voltage is

very low in this example (5 mVp-p), the minimum ripple con-

figuration (R3, C1, and C2 in the Block Diagram) must be

used. The resulting ripple at VOUT is then due to the inductor’s

ripple current passing through COUT. This capacitor’s value

can be selected based on the maximum allowable ripple volt-

age at VOUT, or based on transient response requirements.

The following calculation, based on ripple voltage, provides a

first order result for the value of COUT:

where IOR(max) is the maximum ripple current calculated

above, and VRIPPLE is the allowable ripple at VOUT.

A 100 µF capacitor is selected. Typically the ripple amplitude

will be higher than the calculations indicate due to the

capacitor’s ESR.

R3, C1, C2: The minimum ripple configuration uses these

three components to generate the ripple voltage required at

the FB pin since there is insufficient ripple at VOUT. A minimum

of 25 mVp-p must be applied to the FB pin to obtain stable

constant frequency operation. R3 and C1 are selected to

generate a sawtooth waveform at their junction, and that

waveform is AC coupled to the FB pin via C2. The values of

the three components are determined using the following pro-

cedure:

Calculate VA = VOUT - (VSW x (1 – (VOUT/VIN(min))))

where VSW is the absolute value of the voltage at the SW node

during the off-time, typically 0.5V to 1V depending on the

diode D1. Using a typical value of 0.65V, VA calculates to

4.81V. VA is the nominal DC voltage at the R3/C1 junction,

and is used in the next equation:

where tON is the maximum on-time (at minimum input volt-

age), and ΔV is the desired ripple amplitude at the R3/C1

junction, typically 25 mVp-p. For this example

R3 and C1 are then selected from standard value compo-

nents to produce the product calculated above. Typical values

for C1 are 3000 pF to 10,000 pF, and R3 is typically from 10

kΩ to 300 kΩ. C2 is then chosen large compared to C1, typ-

ically 0.1 µF. For this example, 3300 pF is chosen for C1,

requiring R3 to be 67.7 kΩ. A standard value 66.5 kΩ resistor

is selected.

CIN, CBYP: These capacitors limit the voltage ripple at VIN by

supplying most of the switch current during the on-time. At

maximum load current, when Q1 is switched on, the current

through Q1 suddenly increases to the lower peak of the

inductor’s ripple current, then ramps up to the upper peak,

and then drops to zero at turn-off. The average current during

the on-time is the load current. For a worst case calculation,

these capacitors must supply this average load current during

the maximum on-time, while limiting the voltage drop at VIN.

For this example, 0.5V is selected as the maximum allowable

droop at VIN. Their minimum value is calculated from:

A 33 µF electrolytic capacitor is selected for CIN, and a 1 µF

ceramic capacitor is selected for CBYP. Due to the ESR of

CIN, the ripple at VIN will likely be higher than the calculation

indicates, and therefore it may be desirable to increase CIN to

47 µF or 68 µF. CBYP must be located as close as possible to

the VIN and GND pins of the LM5085. The voltage rating for

both capacitors must be at least 55V. The RMS ripple current

rating for the input capacitors must also be considered. A

good approximation for the required ripple current rating is

IRMS > IOUT/2.

D1: A Schottky diode is recommended. Ultra-fast recovery

diodes are not recommended as the high speed transitions at

the SW pin may affect the regulator’s operation due to the

diode’s reverse recovery transients. The diode must be rated

for the maximum input voltage, and the worst case current

limit level. The average power dissipation in the diode is cal-

culated from:

PD1 = VF x IOUT x (1-D)

where VF is the diode’s forward voltage drop, and D is the on-

time duty cycle. Using Equation 1, the minimum duty cycle

occurs at maximum input voltage, and is calculated to be

≊9.1% in this example. The diode power dissipation calcu-

lates to be:

PD1 = 0.65V x 5A x (1- 0.091) = 2.95W

15 www.national.com

LM5085

CVCC: The capacitor at the VCC pin (from VIN to VCC) pro-

vides not only noise filtering and stability for the VCC regula-

tor, but also provides the surge current for the PFET gate

drive. The typical recommended value for CVCC is 0.47 µF. A

good quality, low ESR, ceramic capacitor is recommended.

CVCC must be located as close as possible to the VIN and

VCC pins. If the selected PFET has a Total Gate Charge

specification of 100 nC or larger, or if the circuit is required to

operate at input voltages below 7 volts, a larger capacitor may

be required. The maximum recommended value for CVCC is

1 µF.

IC Power Dissipation: The maximum power dissipated in the

LM5085 package is calculated using Equation 12 at the max-

imum input voltage. The Total Gate Charge for the Si7465

PFET is specified to be 40 nC (max) in its data sheet. There-

fore the total power dissipation within the LM5085 is calcu-

lated to be:

PDISS = 55V x ((40 nC x 300 kHz) + 1.4 mA) = 737 mW

Using an MSOP-8EP package with a θJA of 46°C/W produces

a temperature rise of 34°C from junction to ambient.

Final Design Example Circuit

The final circuit is shown in Figure 4, and its performance is

presented in Figure 5 through Figure 8.

30057742

FIGURE 4. Example Circuit

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LM5085

30057705

FIGURE 5. Efficiency vs. Load Current and VIN

(Circuit of Figure 4)

30057744

FIGURE 6. Frequency vs. VIN

(Circuit of Figure 4)

30057745

FIGURE 7. Current Limit vs. VIN

(Circuit of Figure 4)

30057746

FIGURE 8. LM5085 Power Dissipation

(Circuit of Figure 4)

17 www.national.com

LM5085

Alternate Output Ripple

Configurations

The minimum ripple configuration, employing C1, C2, and R3

in figure 4, results in a low ripple amplitude at VOUT deter-

mined mainly by the characteristics of the output capacitor

and the ripple current in L1. This configuration allows multiple

ceramic capacitors to be used for VOUT if the output voltage

is provided to several places on the PC board. However, if a

slightly higher level of ripple at VOUT is acceptable in the ap-

plication, and distributed capacitance is not used, the ripple

required for the FB comparator pin can be generated with

fewer external components using the circuits shown below.

a) Reduced ripple configuration: In Figure 9, R3, C1 and

C2 are removed (compared to Figure 4). A low value resistor

(R4) is added in series with COUT, and a capacitor (Cff) is

added across RFB2. Ripple is generated at VOUT by the

inductor’s ripple current flowing through R4, and that ripple

voltage is passed to the FB pin via Cff. The ripple at VOUT can

be set as low as 25 mVp-p since it is not attenuated by RFB2

and RFB1. The minimum value for R4 is calculated from:

where IOR(min) is the minimum ripple current, which occurs at

minimum input voltage. The minimum value for Cff is deter-

mined from:

where tON(max) is the maximum on-time, which occurs at min-

imum VIN. The next larger standard value capacitor should

be used for Cff.

30057749

FIGURE 9. Reduced Ripple Configuration

b) Lowest cost configuration: This configuration, shown in

Figure 10, is the same as Figure 9 except Cff is removed.

Since the ripple voltage at VOUT is attenuated by RFB2 and

RFB1, the minimum ripple required at VOUT is equal to:

VRIP(min) = 25 mV x (RFB2 + RFB1)/RFB1

The minimum value for R4 is calculated from:

where IOR(min) is the minimum ripple current, which occurs at

minimum input voltage.

30057751

FIGURE 10. Lowest Cost Ripple Generating Configuration

www.national.com 18

LM5085

PC Board Layout

In most applications, the heat sink pad or tab of Q1 is con-

nected to the switch node, i.e. the junction of Q1, L1 and D1.

While it is common to extend the PC board pad from under

these devices to aid in heat dissipation, the pad size should

be limited to minimize EMI radiation from this switching node.

If the PC board layout allows, a similarly sized copper pad can

be placed on the underside of the PC board, and connected

with as many vias as possible to aid in heat dissipation.

The voltage regulation, over-voltage, and current limit com-

parators are very fast and can respond to short duration noise

pulses. Layout considerations are therefore critical for opti-

mum performance. The layout must be as neat and compact

as possible with all the components as close as possible to

their associated pins. Two major current loops conduct cur-

rents which switch very fast, requiring the loops to be as small

as possible to minimize conducted and radiated EMI. The first

loop is that formed by CIN, Q1, L1, COUT, and back to CIN. The

second loop is that formed by D1, L1, COUT, and back to D1.

The connection from the anode of D1 to the ground end of

CIN must be short and direct. CIN must be as close as possible

to the VIN and GND pins, and CVCC must be as close as pos-

sible to the VIN and VCC pins.

If the anticipated internal power dissipation of the LM5085 will

produce excessive junction temperatures during normal op-

eration, a package option with an exposed pad must be used

(MSOP-8EP or LLP-8). Effective use of the PC board ground

plane can help dissipate heat. Additionally, the use of wide

PC board traces, where possible, helps conduct heat away

from the IC. Judicious positioning of the PC board within the

end product, along with the use of any available air flow

(forced or natural convection) also helps reduce the junction

temperature.

19 www.national.com

LM5085

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead MSOP-EP Package

NS Package Number MUY08A

8-Lead MSOP Package

NS Package Number MUA08A

www.national.com 20

LM5085

8-Lead LLP Package

NS Package Number SDA08A

21 www.national.com

LM5085

Notes

LM5085 75V Constant On-Time PFET Buck Switching Controller

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